GB2214038A - Image display system - Google Patents
Image display system Download PDFInfo
- Publication number
- GB2214038A GB2214038A GB8816895A GB8816895A GB2214038A GB 2214038 A GB2214038 A GB 2214038A GB 8816895 A GB8816895 A GB 8816895A GB 8816895 A GB8816895 A GB 8816895A GB 2214038 A GB2214038 A GB 2214038A
- Authority
- GB
- United Kingdom
- Prior art keywords
- tile
- image
- memory
- address
- display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 claims abstract description 66
- 239000011521 glass Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000002457 bidirectional effect Effects 0.000 description 2
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T3/00—Geometric image transformations in the plane of the image
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/12—Frame memory handling
- G09G2360/122—Tiling
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/14—Display of multiple viewports
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
An image display system is described in which a raster-scanned display is divided into tiles. A pair of counters 30, 31 keep track of which tile the scan is currently passing through. These counters address a tile memory 23, so as to read out a base address and a length code. Another counter 26 maintains a line count indicating which line within the tile is being scanned. The line count is multiplied by the length code and the result added (27) to the base address, to produce an address for an image memory 20, so as to access a data word for display. The use of the tile memory allows the image to be manipulated (e.g. to scroll, pan or produce a window or spy-glass effect) simply by changing the contents of the tile memory 23, without re-writing the image memory. <IMAGE>
Description
IMAGE DISPLAY SYSTEM background to the invention
This invention relates to image display systems.
More specifically, the invention is concerned with an image display system for producing images on a raster-scanned display device, such as a cathode ray tube (CRT). In such a system, the image data may be stored in a memory, referred to as the image memory, which holds data defining each picture element (pixel) of the image. For example, in a monochrome display, each pixel is represented by a single bit signifying black/white.
In such a system, it is often desired to perform various manipulations on the image. For example, it may be desired to pan (i.e. move the image from side to side) or scroll (i.e. move it up and down). Another possible image manipulation is to create a window or spy-glass, allowing a specified portion of the image to be displayed on an enlarged scale.
In conventional systems of this kind, these image manipulations generally involve re-writing the contents of the image memory so as to define the new image to be displayed. For example, in order to pan or scroll the image it is necessary to shift the contents of the image memory by a predetermined amount in the required direction. This can be a complex operation, taking a significant length of time.
One object of the present invention is to provide a way of removing or alleviating this problem.
Summary of the invention
According to the invention there is provided an image display system comprising a raster-scanned display device for displaying an image comprising an array of picture elements (pixels), and an image memory for holding data representing the pixels, characterised in that the image is divided into tiles, each tile comprising a sub-array of the pixels, and the system comprises:: (a) a tile memory having a plurality of locations
each holding a base address, (b) means for producing a first signal indicating
which tile is currently being scanned in the
raster, and a second signal indicating which
raster line of that tile is currently being
scanned, (c) means for utilising the first signal to address
the tile memory to read out a base address for
the tile currently being scanned, (d) means for combining said base address with said
second signal to produce a memory address, and (e) means for utilising said memory address to
access the image memory to read out data
representing a portion of the current raster
line, and for applying that data to the display
device.
As will be shown, the provision of a tile memory greatly facilitates manipulation of the image, since the image can be manipulated simply by changing the contents of the tile memory, rather than by re-writing the whole image memory. For example, in order to pan or scroll the image, it is simply necessary to add a predetermined constant to each entry in the tile memory.
One image display system in accordance with the invention will now be described by way of example with reference to the accompanying drawings.
Brief description of the drawings
Figure 1 is an overall view of the image display system.
Figure 2 is a detailed block diagram of an image generator circuit forming part of the display system.
Figure 3 is a schematic diagram illustrating the way in which the image is divided into tiles.
Figure 4 is a schematic diagram showing the data in an image memory and a tile memory forming part of the image generator.
Description of an embodiment of the invention
Referring to Figure 1, the image display system comprises a host computer 10, a display generator 11, and a display monitor 12.
The host computer 10 may be a known computer or micro-computer. The host 10 is connected to the display generator by means of a 32-bit data bus 13 and a 24-bit address bus 14.
The display monitor 12 may be a conventional high-definition interlaced CRT monitor having, for example, a resolution of 200 pixels (picture elements) per inch.
The display generator 11 comprises an image generator 15 for generating graphical displays, and a character generator 16 for generating character displays. The character generator 16 may be a conventional circuit and so will not be described in further detail. The image generator 15 is described in detail below.
Both the image generator 15 and character generator 16 are connected to a bidirectional data bus
DG-DATA, which in turn is connected to the host data bus 13 by way of a dual-port data buffer 17. Both of the generators 15,16 receive an address signal BUS-ADDR from the host address bus 14, by way of a receiver circuit 18. These connections allow the host processor to address locations within the image generator and
character generator, to read or update data in them.
The image generator 15 can also output image
data, by way of the data bus DG-DATA, to a display output
circuit 19. This circuit converts the data from parallel
to serial form, and produces a video signal for the
display monitor 12. The output circuit also receives -character data from the character generator 16 for
display on the monitor 12. The output circuit also
generates the conventional horizontal and vertical
synchronisation signals HZSY and VTSY for the display.
The display output circuit 19 may be conventional and so
will not be described in further detail.
Referring now to Figure 2, this shows the image
generator 15 in detail.
The image generator comprises an image memory
20, comprising two random-access memory banks, each of
which holds 256K thirty-two bit words. Each bit
represents the display value of a pixel (black or white)
and the bits of each word represent 32 successive pixels
along a raster scan line of the display. The image
memory can hold a number of data frames, each
representing an image to be displayed.
The image memory has a 32-bit wide data input/
output port, which is connected to the data bus DG-DATA.
The image memory also has a 9-bit wide address
input path, which is connected to a display address
register 21 and to a bus address register 22. Each of
these address registers 21,22 holds a 18-bit address,
comprising a 9-bit row address and a 9-bit column address.
In order to address the image memory from either
of these address registers 21,22, the row address is
first read out of the register on to the address path,
and is gated into an internal row address register (not
shown) within the image memory, by means of a row address
strobe (RAS) signal. The column address is then read out
of the address register 21 or 22 and is gated into an
internal column address register within the image memory
by means of a column address strobe (CAS) signal. This
form of row and column addressing is well known and so
need not be described in further detail.
When the image memory is addressed in this way,
one of the 32-bit words in the memory is accessed and can
be read or written to by way of the data bus DG-DATA.
-Alternate words are accessed from alternate banks of the memory so as to increase access speed.
The bus address register 22 receives the address
signal BUS-ADDR from the host computer by way of the
receiver circuit 18. This allows tne host computer to
address the image memory so as to write data into it or
read its contents over the data bus DG-DATA.
The display address register 21 receives a display address DSP-AD which is used for addressing the
image memory when reading out a sequence of image data
forming a display. This data is fed to the display monitor 19 by way of the data bus DG-DATA.
The display address DSP-AD is generated using a tile memory 23. This comprises a random-access memory having 4K word locations. Each of these locations contains a 20-bit base address BASE, and a 7-bit length
code LC, representing the number L of image memory words
for each scan line of the display, minus an offset of 32,
so that the actual line length L= LC + 32.
Referring to Figure 3, this is a schematic diagram of an image generated by the image generator.
The image consists of a number of tiles TILE 00,
TILE 01--- arranged in rows and columns. Each of the
tiles consists of a sub-array of 32 x 32 pixels. Thus,
it can be seen that each row of tiles comprises 32 complete raster scan lines of the display.
Referring now to Figure 4, this illustrates the data held in the image and tile memories.
Each location in the tile memory corresponds to one of the tiles, the sequence of locations corresponding
to the sequence of tiles in the image in row order, i.e.
all the tiles in the first row, followed by all the tiles in the second row, and so on.
The base address BASE in each location of the tile memory points to the location in the image memory that holds the data representing the first scan line of the tile. Thus, for example, the base address in the location corresponding to tile 00 points to the location containing the data for line 0 of tile 00. Subsequent scan lines of the tile are held in locations of the image memory at address BASE + L, BASE + 2L and so on.
Thus, it can be seen that the data for scan line
N of a given tile is held in the image memory at address
BASE + (N x L).
Returning now to Figure 2, the tile memory 23 has a data input/output port connected to a bidirectional data bus TILE-DATA.
This bus TILE-DATA is connected to the input of a tile register 24, which thus receives the base address
BASE and length code LC read out of the tile memory. The length code LC from the register 24 is fed to the address input of a read-only memory (ROM) 25, along with a five-bit line number N from a tile line counter 26. The counter 26 is a five-stage counter and is incremented by the horizontal synchronisation signal HZSY of the display. Hence, it can be seen that the line number N indicates which scan line within the current row of tiles is currently being scanned.
The ROM 25 is programmed in a known manner to add the offset value (32 in this example) to the length code LC to give the actual line length L, and to multiply the result by the line number N. The result N x L is obtained from the data output of the ROM, and is fed to one input of an adder 27. The other input of the adder 27 receives the base address BASE from the register 24.
The output of the adder 27 is the display address DSP-AD which is fed to the display address register 21 for addressing the image memory as described above.
In summary, it can be seen that the display address DSP-AD is equal to
BASE + (N x L) which, as shown above, is the required address for accessing the image memory to read out the current scan line of the currently addressed tile.
The bus TILE DATA is also connected by way of a two-port tile data buffer 28, to the data bus DG-DATA.
The tile memory 23 has an address input which receives a 12-bit address signal from a multiplexer/ register 29. The first input of this multiplexer 29 is connected to receive 12 bits of the address signal
BUS-ADDR from the host computer. Thus, when this input is selected, the host computer can address the tile memory 23, and read or write the data in the addressed location by way of the data bus DG-DATA.
The second input of the multiplexer 29 receives a 12-bit address ADH, ADL. The six low-order bits ADL of this address come from a six-stage horizontal tile counter 30. This counter is incremented by a clock signal SRQ having a frequency equal to one 32nd of the pixel clock rate of the system, corresponding to the rate at which the tiles are scanned horizontally in each raster line. The address bits ADL thus indicate the horizontal position of the tile through which the scan is currently passing.
The six high-order bits ADL come from a six-stage vertical tile counter 31. This counter is incremented by an overflow signal OVF from the tile line counter 26, i.e. it is incremented after every 32 raster scan lines. Hence, it can be seen that the address bits
ADH represent the vertical position of the tile through which the scan is currently passing. The counter 31 is reset by the vertical synchronisation signal VTSY of the display.
In summary, it can be seen that, as the display is scanned in the conventional raster pattern, the
counters 30,31 keep track of which tile the scan is
currently passing through. These counters 30,31 are used
to address the tile memory, so as to read out the
contents of the location corresponding to this tile. The
base address BASE and length code L of this location are
combined with the line count L, to produce the address
DSP-AD which indicates the position in the image memory
of the data for the position of the current raster scan
line which lies within this tile. This data is read out
of the image memory, and is fed to the display monitor to
produce the required display.
It can be seen that, in order to pan the image
by one tile width, it is necessary merely to add or
subtract one from each base address in the tile store.
Similarly, in order to scroll the image by one raster
line, it is necessary simply to add or subtract to form
each base address held in the tile store. Windows can
also be produced in a simple manner, by re-writing the
base addresses in a selected portion of the tile store to
point to another area of the image memory containing, for
example, a magnified portion of the display. It is not
necessary to re-write the contents of the image store for
these operations.
Claims (7)
1. An image display system comprising a raster-scanned display device for displaying an image comprising an array of picture elements (pixels), and an image memory for holding data representing the pixels, characterised in that the image is divided into tiles, each tile comprising a sub-array of the pixels, and the system comprises::
(a) a tile memory having a plurality of locations
each holding a base address,
(b) means for producing a first signal indicating
which tile is currently being scanned in the
raster, and a second signal indicating which
raster line of that tile is currently being
scanned,
(c) means for utilising the first signal to address
the tile memory to read out a base address for
the tile currently being scanned,
(d) means for combining said base address with said
second signal to produce a memory address, and (e) means for utilising said memory address to
access the image memory to read out data
representing a portion of the current raster
line, and for applying that data to the display
device.
2. A system according to Claim 1 wherein the means for combining the base address with the second signal comprises means for multiplying said second signal by a length code and then adding the product to the base address.
3. A system according to claim 2 wherein said means for multiplying comprises a read-only memory having inputs for receiving said second signal and said length value.
4. A system according to claim 2 or 3 wherein the length code is held in the tile memory along with the base address.
5. A method of displaying an image comprising an array of picture elements (pixels),the method comprising the steps (a) storing image data words in a memory, (b) generating a sequence of tile addressess, each of which identifies a tile consisting of a sub-array of said pixels, (c) using each tile address to access a table, to
obtain a base address for the corresponding tile, (d) generating a sequence of line numbers each of
which identifies a scan line within a tile, (e) combining the base address obtained from the
table with the line numbers, to produce a memory
address, (f) using the memory address to access the memory,
to read out an image data word for display.
6. An image display system substantially as hereinbefore described with reference to the accompanying drawings.
7. A method of displaying an image substantially as hereinbefore described with reference to the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10450587A | 1987-10-05 | 1987-10-05 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8816895D0 GB8816895D0 (en) | 1988-08-17 |
| GB2214038A true GB2214038A (en) | 1989-08-23 |
| GB2214038B GB2214038B (en) | 1991-07-03 |
Family
ID=22300856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8816895A Expired - Fee Related GB2214038B (en) | 1987-10-05 | 1988-07-15 | Image display system |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2214038B (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2223651A (en) * | 1988-10-07 | 1990-04-11 | Sun Microsystems Inc | Overwriting display memory without clearing speeds computer animation |
| GB2231471A (en) * | 1989-04-25 | 1990-11-14 | Quantel Ltd | Image processing system with individual transformations for image tiles |
| WO1991006065A2 (en) * | 1989-10-10 | 1991-05-02 | Unisys Corporation | Image data processor system |
| US5043923A (en) * | 1988-10-07 | 1991-08-27 | Sun Microsystems, Inc. | Apparatus for rapidly switching between frames to be presented on a computer output display |
| WO1992003798A1 (en) * | 1990-08-20 | 1992-03-05 | Eastman Kodak Company | Offset-based dma mechanism |
| US5140444A (en) * | 1989-10-10 | 1992-08-18 | Unisys Corporation | Image data processor |
| EP0561076A2 (en) * | 1992-03-19 | 1993-09-22 | Hudson Soft Co., Ltd. | Method for scrolling images on a screen |
| EP0577102A2 (en) * | 1992-07-02 | 1994-01-05 | Nec Corporation | Address formation circuit for image processing and method of generating address |
| GB2269293A (en) * | 1992-07-30 | 1994-02-02 | Sony Broadcast & Communication | Apparatus for performing video effects manipulations upon image data |
| US5305398A (en) * | 1989-10-10 | 1994-04-19 | Unisys Corporation | Method and apparatus for scaling image data |
| US5708763A (en) * | 1993-12-21 | 1998-01-13 | Lexmark International, Inc. | Tiling for bit map image |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0197413A2 (en) * | 1985-04-05 | 1986-10-15 | Tektronix, Inc. | Frame buffer memory |
-
1988
- 1988-07-15 GB GB8816895A patent/GB2214038B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0197413A2 (en) * | 1985-04-05 | 1986-10-15 | Tektronix, Inc. | Frame buffer memory |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2223651B (en) * | 1988-10-07 | 1993-03-31 | Sun Microsystems Inc | Apparatus for rapidly clearing the output display of a computer sytem |
| US5043923A (en) * | 1988-10-07 | 1991-08-27 | Sun Microsystems, Inc. | Apparatus for rapidly switching between frames to be presented on a computer output display |
| GB2223651A (en) * | 1988-10-07 | 1990-04-11 | Sun Microsystems Inc | Overwriting display memory without clearing speeds computer animation |
| GB2231471A (en) * | 1989-04-25 | 1990-11-14 | Quantel Ltd | Image processing system with individual transformations for image tiles |
| GB2231471B (en) * | 1989-04-25 | 1994-03-30 | Quantel Ltd | An electronic image processing apparatus |
| WO1991006065A3 (en) * | 1989-10-10 | 1992-01-09 | Unisys Corp | Image data processor system |
| US5140444A (en) * | 1989-10-10 | 1992-08-18 | Unisys Corporation | Image data processor |
| WO1991006065A2 (en) * | 1989-10-10 | 1991-05-02 | Unisys Corporation | Image data processor system |
| US5305398A (en) * | 1989-10-10 | 1994-04-19 | Unisys Corporation | Method and apparatus for scaling image data |
| WO1992003798A1 (en) * | 1990-08-20 | 1992-03-05 | Eastman Kodak Company | Offset-based dma mechanism |
| EP0561076A2 (en) * | 1992-03-19 | 1993-09-22 | Hudson Soft Co., Ltd. | Method for scrolling images on a screen |
| EP0561076A3 (en) * | 1992-03-19 | 1993-12-15 | Hudson Soft Co Ltd | Method for scrolling images on a screen |
| EP0577102A2 (en) * | 1992-07-02 | 1994-01-05 | Nec Corporation | Address formation circuit for image processing and method of generating address |
| EP0577102A3 (en) * | 1992-07-02 | 1994-07-20 | Nec Corp | Address formation circuit for image processing and method of generating address |
| US5455908A (en) * | 1992-07-02 | 1995-10-03 | Nec Corporation | Address formation circuit and method for continuously performing an address-based memory access into a rectangular area |
| GB2269293A (en) * | 1992-07-30 | 1994-02-02 | Sony Broadcast & Communication | Apparatus for performing video effects manipulations upon image data |
| GB2269293B (en) * | 1992-07-30 | 1996-04-24 | Sony Broadcast & Communication | Apparatus and method for processing image data |
| US5708763A (en) * | 1993-12-21 | 1998-01-13 | Lexmark International, Inc. | Tiling for bit map image |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8816895D0 (en) | 1988-08-17 |
| GB2214038B (en) | 1991-07-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20020715 |