WO1992003798A1 - Offset-based dma mechanism - Google Patents

Offset-based dma mechanism Download PDF

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Publication number
WO1992003798A1
WO1992003798A1 PCT/US1991/005911 US9105911W WO9203798A1 WO 1992003798 A1 WO1992003798 A1 WO 1992003798A1 US 9105911 W US9105911 W US 9105911W WO 9203798 A1 WO9203798 A1 WO 9203798A1
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WO
WIPO (PCT)
Prior art keywords
tile
storage locations
tiles
address
row
Prior art date
Application number
PCT/US1991/005911
Other languages
French (fr)
Inventor
James Morgan Gotta, Iii
David William Dellert
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Eastman Kodak Company
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Publication date
Application filed by Eastman Kodak Company filed Critical Eastman Kodak Company
Publication of WO1992003798A1 publication Critical patent/WO1992003798A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management

Definitions

  • the present invention relates in general to information storage and retrieval systems and is particularly directed to a direct memory access mechanism for rapidly accessing a selected portion of a data base, such as a plurality of tiles within an image bit map memory, by means of a dedicated, offset-based, address control architecture.
  • Accessing discrete portions of a large data base such as a bit map memory which may have a storage capacity that accommodates a 3200 by 3000 pixel matrix, is typically accomplished in one of two ways:
  • this processor overhead burden is removed by means of a dedicated address generation architecture which controllably combines a single starting address supplied by the processor with a set of predefined 'offsets' and steps through each of the tiles of a block of tiles corresponding to that portion of the data base involved in the transfer.
  • the address generation architecture of the present invention contains a line address storage register which is coupled to receive, from the host processor, an address code representative of a first set of addressable storage locations of a first row of a first one of the block of tiles involved in the transfer.
  • a respective row of a tile is subdivided into sets of address words, each of which is associated with, a plurality of pixel locations .e.g..
  • the address generator couples the adder to a second 'line offset' code modifier which, when combined with the contents of said line address store, yields an address code representative of a first set of addressable storage locations of another (e.g. the second or next) row of the tile, which now becomes the base address stored in the .line address register.
  • a fourth strip offset is stored.
  • This code is representative of the sequential address displacement between the first set of addressable storage locations of the last row of a last tile of one strip of tiles and the first set of addressable storage locations of the first row of addressable storage locations of a first tile of another strip of tiles.
  • the fourth offset is used as an offset to the line address register to specify the starting address of the next strip. This sequential offset reference and stepping process is continued through all the strips of the block to complete the DMA transfer.
  • Figure 1 diagrammatically shows an information storage and retrieval system in which the memory access mechanism of the present invention may be employed;
  • Figure 2 diagrammatically shows the configuration of a direct memory access unit 41 of Figure 1;
  • Figure 3 diagrammatically illustrates the hierarchical relationship among a frame store matrix and respective components of a block of addresses to be accessed by the DMA unit of the present invention
  • Figure 5 diagrammatically shows the storage space of destination frame store 21 subdivided into a plurality of tiles 27-1...27-16.
  • the present invention resides primarily in a novel structural combination of conventional digital signal processing circuits and components and not in the particular detailed configurations thereof. Accordingly, the structure, control and arrangement of these conventional circuits and components have been illustrated in the drawings in readily understandable block diagram format to show only those specific details that are pertinent to the present invention, so as not to obscure the disclosure with structural details which will be readily apparent to those skilled in the art having the benefit of the description herein. Thus, the block diagram il. .trations do not necessarily represent the mechanical structural arrangement of the exemplary system, but are primarily intended to illustrate the major structural components of the system in a convenient functional grouping, whereby the present invention may be more readily understood.
  • FIG. 1 a non- limiting example of an information storage and retrieval system in which the offset-based direct memory access mechanism of the present invention may be employed is diagrammatically shown as comprising an imagery data processing system having a first, or source, frame store 11, which contains data representative of a bit map image 13 to be displayed by an associated display terminal 15.
  • the bit map itself comprises an M row by N column array or matrix of pixels and, as a simplified illustration, may be considered to comprise a 256X256 array of pixels, subdividable into a plurality (e.g. sixteen) of pixel 'tiles' 17-1 ...17-16, each tile comprising a 64X64 pixel sub-array, or sub-matrix.
  • FIG. 1 Also shown in Figure 1 is a second, or destination, frame store 21 which, like frame store 11, is capable of storing data representative of an MXN bit map array that may be displayed on an associated display terminal, such as display terminal 21, or a separate device (not shown) .
  • Each of frame stores 11 and 21 has its data port coupled to a data bus 25 through which imagery-representative data, accessed from either of frame stores 11 and 21, may be coupled to an digital-analog converter 26, which converts the pixel control codes on bus 25 into analog format for defining the energization of the respective pixels of display 15.
  • the storage and retrieval system of Figure 1 further includes a data orientation device, such as a conventional data rotator unit 31, which is coupled to data bus 25 and rotates (e.g. performs a 90° rotation of) a block of data supplied to its data port 33.
  • DMA unit 41 In accordance with the present invention, addressing of the respective storage locations of each of frame stores 11 and 21, for reading and writing data to and from memory, is effected by means of a Direct Memory Access (DMA) unit 41, shown in detail in Figure 2 to be described below.
  • DMA unit 41 employs a set of offsets that are used to sequentially update the base address with a line address register, in the course of generation address signals only for storage locations associated with those tiles that make up the portion of the frame store to be accessed.
  • the operation to be performed involves a transfer, a translation and a rotation of a portion of the bit map imagery data within frame store 11 to frair '.ore 21.
  • translation is meant that the dest ..tion location, within the bit map of frame store 21, of the transferred portion of the image is different from its original location within the bit map in frame store 11.
  • bit map 17 within frame store 11
  • a destination location within the bit map 27 stored by frame store 21 denoted by a block 52 of tiles 27-11, 27-12, 27-15 and 27-16.
  • the location of 'destination' block 52 in the bit map 27 of frame store 21 is in the lower right-hand corner of the bit map 27, whereas the location of 'source' block 51 is in the upper left-hand corner of bit map 17 of frame store 11, so that the transfer between frame stores effectively performs a translation of the location of the selected portion of the image.
  • the ir gery data within source block 51 is also to undergo a 90° clockwise rotation relative to its orientation within frame store 11.
  • the imagery data within each of the tiles of frame store 11 be represented by an enlarged reference numeral associated with the numerical position of the tile within the sixteen tile matrix, then an associated set of vertically oriented number images 1, 2, 5, and 6 shown within respective tiles 17-1, 17-2, 17-5 and 17-6 of source block 51, after being when rotated clockwise 90°, will be transferred to tiles 27-12, 27-16, 27-11 and 27-15, respectively, of destination block 52 in horizontal orientation, as shown.
  • DMA unit 41 is diagrammatically shown as having an input port 61 which is coupled to the control bus 63 of an attendant control processor (not shown) .
  • the control processor supplies a starting address code representative of the starting address of the block of tiles involved in the data transfer.
  • port 61 receives a starting address code representative of a starting address in the first row of tile 17-1.
  • data is accessed as multi-bit words or sets, so that the starting address will be the address where the first word in the first line of the tile is stored.
  • pixel data may be accessed in words of sixteen pixel addresses per word address, so that there are four words per tile row.
  • Input port 61 is coupled to a first input 71 of a multiplexer 70, the output port 74 of which is coupled to- an output register 73 and to a line register 75.
  • Output register 73 is coupled to output port 81, while line register 75 is coupled to a first port 83 of an address code combiner (here an adder) 80, a second port 85 of which is coupled to output port 95 of a 4:1 multiplexer 90.
  • Adder 80 combines or sums the address code stored in line register 75 with an address code modifier supplied from multiplexer 90 and couples the resulting sum or 'modified' address code to a second input port 72 of multiplexer 70.
  • multiplexer 70 couples input port 72 to its output port 74, so that the modified address code generated by adder 80 is coupled to output register 73 for application to output port 81.
  • output port 74 of multiplexer 70 is also coupled to line address register 75, line address register 75 is not updated in the same manner as output register 73. Instead, the contents of line address register 75 are sequentially incremented only when one of a set of input ports 92-94 of multiplexer 90, to which line, file and offset codes are respectively supplied, is selected. The selected offset code is summed in adder 90 with the contents of the line address register 75 and then rewritten back into register 75 (by way of multiplexer 70) , in order to effectively step through successive address of the block of files involved in the transfer.
  • the input ports to multiplexer 90 include an input port 91 coupled to the output of a tile width up-counter 111, the input of which is coupled to a tile width register 101.
  • Each of tile width counter 111 and tile width register 101 is also coupled to a comparator 113, which generates an output in response to the contents of tile width counter 111 matching the tile width code stored in tile width register 101.
  • 'tile width' is meant the number of words that are contained in a row of a tile. As pointed out above, data is normally accessed as multi-bit words. In the present example of sixty-four pixels per row, with sixteen bits per word, the total word width of an individual tile is four words.
  • up-counter 111 is successively incremented from an initial (reset) value of zero until its count value matches the value (e.g. three for the present example of four words per row) stored in tile width register 101.
  • comparator 113 produces an output which causes tile width counter 111 to be reset and causes multiplexer 90 to select one of its other input ports (92, 93 and 94) depending upon where in the block of tile the address scan is currently located.
  • counter 111 As counter 111 is being incremented, it generates a sequence of address code modifiers which are summed in adder 83 with the contents of line address register 75 to yield a sequence of modified address codes associated with respectively different words of address space within that one of the rows of a respective tile currently pointed to by line address register 75.
  • a second input 92 is coupled to line offset register 102 which stores a line offset code representative of the displacement (in words) between the same word address location for successive rows of a tile. For a matrix line vidth of 256 bits, 1 » displacement between the first word address or. row i and row itl of a respective tile is 16 words.
  • a third input port 93 of multiplexer 90 is coupled to a tile offset register 103, which stores a 'tile offset' address code modifier.
  • the value of the tile offset modifier is such that when combined in adder 80 with the contents of line address register 75, the resulting sum yields an address code representative of the first row or line another (the next successive) tile of the block of tiles involved in the transfer.
  • the value of the strip offset modifier represents the sequential address displacement between the address of the last or Jth row of the last tile in one strip of tiles and that of the next strip of tiles within the block of interest.
  • a tile strip is a subdivision of the tile block in a selected address scan direction (e.g. horizontally, or parallel to the rows or lines of the matrix) .
  • block 51 is comprised of two adjacent tile strips SI and S2, each strip containing two tiles.
  • Strip SI contains tiles 17-1 and 17-2, while strip S2 contains tiles 17-5 and 17-6.
  • Figure 3 diagrammatically illustrates the hierarchical relationship among the frame store matrix and the respective components of a block of addresses to be accessed by the DMA unit of the present invention.
  • block 51 is comprised of two strips SI and S2, strip SI containing two tiles
  • a respective tile has a 'height' of sixty-four rows, as exemplified by tile 17-1.
  • a respective row of sixty- four pixel locations or columns contains four words, each of which comprises sixteen pixel locations.
  • a 'strip' down-counter 120 is employed. At the start of the DMA process, counter 120 is loaded with the number of tile strips in the block (two in the present example) . Counter 120 is then successively decremented as each strip of tiles is processed. When counter 120 expires, or is decremented to zero, it is determined that there are no further strips to be processed for that block. Similarly, to determine when address codes have been generated for all of the tiles in a respective strip of tiles, a 'tile' down-counter 122 and an associated 'tile' register 124 are employed.
  • tile register 124 is initially loaded with the number of tiles per strip (two in the present example) , and the tile code is entered into tile counter 122. Like strip counter 120, tile down-counter 122 is successively decremented as each strip of tiles is processed. When counter 122 expires or is decremented to zero it is determined that there are no further tiles to be processed for that strip. The contents of tile register 124 are then transferred to c inter 122 for processing the next strip.
  • a 'tile height' down-counter 126 and an associated 'tile count' register 128 are employed.
  • 'Tile height' register 126 is initialized with the number of rows per tile (sixty-four in the present example) , and this tile height code is loaded into tile height counter 126.
  • Tile height down-counter 126 is successively decremented as each row of a tile is processed. When counter 126 expires or is decremented to zero it is determined that there are no further rows in the tile to be processed. The contents of tile height register 128 are then transferred to counter 126 for processing the next tile.
  • multiplexer 90 controllably couples the contents of selected ones of tile width counter 111 and offset registers 102, 103 and 104 to its output port 95, so that, when summed with the contents of line address register 75, there is produced a modification of the original address code coupled to input port 61 that effects a rapid scan through only those storage locations in the frame store associated with the tiles in the block of interest. Other entries in the memory are ignored.
  • the addressable storage locations of a respective row are addressable in successive sets or words of sixteen locations (columns) , so that each row of a tile contains four consecutive words (W0-W3) .
  • the control processor supplies to input port 61 an address code representative of the first word WO of the first row of the block of tiles to be involved in the DMA transfer.
  • the processor supplies the address of word WO of the first row of tile 17-1, which is coupled through multiplexer 70 and loaded into line address register 75.
  • Address code offset multiplexer 90 is controlled to select tile width counter 111, which is currently reset.
  • the output of adder 80 is simply the initial address code that has been loaded into line address register 75.
  • This combined address code is coupled through multiplexer 70 and loaded into output register 73, so that the output address code at port 81 points to the upper left- hand corner address of tile 17-1, at row 0, address word W0.
  • Tile width up-counter 111 is then sequentially incremented, so that adder 80, in turn, will sequentially produce increasingly larger sums, thereby modifying the address code supplied to output register 73 and stepping through the successive address words W0-W3 of row R0 of tile 17-1.
  • comparator 113 produces an output, which resets tile width counter 111 to be reset, causes tile height counter 126 to be decremented to a value of 63 from its pre-loaded value of 64 and causes address code offset multiplexer 90 to select input port 92, to which the contents of line offset register 102 are coupled.
  • line offset address register 102 stores a line offset value of sixteen which, when combined with the contents of line address register 75, will point produce an address that points to the first address of the second row Rl of tile 17-1. This new line address is then stored in line address register 75.
  • the multiplexer 90 is controlled to select input port 91 and the above sequence operation is repeated, thereby producing successive addresses that step through the four words W0-W3 of the second row Rl of tile 17-1.
  • tile offset register 103 is a value representative of the sequential address displacement between the first word WO of row R63 of tile 17-1 (the current value of line address register 75) and the first word WO of the first row R0 of tile 17-2, namely the next tile in the strip.
  • tile offset register 103 contains the value (-1004) which, when summed with the current contents of line address register 75, points to word W0 in row R0 of tile 17-2, namely the fifth word address in the first line of the matrix. This value is loaded into line address register 75. Multiplexer 90 is then controlled to select input port 91. Addresses are now generated for tile 17-2 in the same sequential manner as described above for tile 17.
  • tile height down- counter 126 has again been decremented to zero, its output changes state, causing the contents of tile down-counter 122 to be decremented.
  • Tile counter 122 now has been decremented to zero, so that its output also changes state, which, in turn, decrements strip down-counter 120 and causes offset multiplexer 90 to select input port 94, to which the contents of strip offset register 104 are coupled.
  • strip offset register 104 contains a value representative of the sequential address displacement between the first word W0 of row R63 of tile 17-2 (the current value of line address register 75) and the first word WO of the first row R0 of tile 17-5, namely the first tile in the next strip S2 of the block.
  • strip offset register 104 contains a value (12) which, when summed with the current contents of line address register 75, points to word WO in row R0 of tile 17-5. This new offset sum is loaded into line address register 75.
  • Multiplexer 90 is controlled to select input port 91 and addresses are now generated for tiles 17-5 and 17-6 of strip S2 in the same sequential manner as described above for tiles 17-1 and 17-2 of strip SI. When address codes have been generated for each of tiles of strip S2, each of counters 120, 122 and 126 will have been decremented to zero, indicating to the processor that the entire block has been processed.
  • the data read out of block 51 of frame store 11 is rotated (via data rotation device 31, Figure 1) and translated into a block of tiles 27-11, 27-12, 27-15 and 27- 16 of frame store 21.
  • the DMA transfer operation involved only a translation
  • the generation of write addresses for writing data into the memory space of frame store 21 would involve essentially the same tile processing sequence described above, except for the starting address.
  • the contents of the first tile (17-1) read out from block 51 are written into a tile location in destination block 52 (upper right-hand corner tile 27-12) that is displaced relative to the location of tile 71 in source block 51 (upper left-hand corner) .
  • the offset parameters that are stored in line and tile offset registers 102 and 103 are different from those involved in the read operation.
  • the storage space of frame store 21 is subdivided into a plurality of sixteen tiles 27-1...
  • the addressable storage locations of a respective row are addressable in successive sets or words of sixteen locations (columns) , so that each row of a tile contains four consecutive words (W0-W3) .
  • the control processor supplies to input port 61 an address code representative of the first word W0 of the first row of the block of tiles to be involved in the DMA write operation.
  • the processor supplies the address of word WO of the first row of tile 27-12, which is coupled through multiplexer 70 and loaded into line address register 75.
  • address code offset multiplexer 90 selects input port 91, i.e., tile width counter ill, which is currently reset. As a consequence, the output of adder 80 is simply the address code that has been loaded into line address register 75.
  • This address code is coupled through multiplexer 70 and loaded into output register 73, so that the output address code at port 81 points to the upper left-hand corner address of tile 27- 12, at row 0, address word WO.
  • Tile width up-counter 111 is then sequentially incremented, so that adder 80 will modify the address code supplied to output register 73, stepping through the successive address words W0-W3 of row R0 of tile 27-12.
  • comparator 113 produces an output, which resets tile width counter 111, causes tile height counter 126 to be decremented and causes address code offset multiplexer 90 to be coupled to line offset register 102.
  • line offset address register 102 stores a line offset value of (16) which, when combined with the contents of line address register 75, will point produce an address that points to the first address of the second row Rl of tile 27-12.
  • This new line address is then stored in line address register 75, multiplexer 90 again selects input port 91 and the above sequence repeated, thereby producing successive addresses that step through the four words W0-W3 of the second row Rl of tile 27-12. These steps are repeated for each of the sixty-four rows of tile 27-12 until address codes have been generated for all of its 64 rows.
  • tile height down-counter 126 has been decremented to zero, its output changes state.
  • the signal causes the contents of tile down-counter 122 to be decremented and offset multiplexer 90 to be coupled to tile offset register 103.
  • the contents of tile offset register 103 contain an offset value representative of the sequential address displacement between the first word W0 of row R63 of tile 27-12 (the current value of line address register 75) and the first word W0 of the first row R0 of tile 27-16, namely the next tile in the (vertical due to the 90° rotation) strip SI containing tile 27-12.
  • tile offset register 103 contains a value here (+16 words) which, when summed with the current contents of line address register 75, points to word W0 in row R0 of tile 27-16, namely the first word address in line 193 of the matrix.
  • This new base address is loaded into line address register 75 and multiplexer 90 controlled to select input port 91. Addresses are now generated for tile 27-16 in the same sequential manner as described above for tile 27- 12.
  • address codes have been generated for all 64 rows of tile 27-16, the contents of line address counter 75 will again point to the first word W0 of row R63. Since tile height down- counter 126 has again been decremented to zero, its output changes state, causing the contents of tile down-counter 122 to be decremented.
  • Tile counter 122 - too now has been decremented to zero, so that its output changes state.
  • This signal decre-rtents strip down-counter 120 and causes offset multiplexer 90 to select input port 94 to which strip offset r gister 104 is coupled.
  • the contents of strij. offset register 104 contain a value representative of the sequential address displacement between the first word WO of row R63 of tile 27-16 (the current value of line address register 75) and the first word WO of the first row R0 of tile 27-11, namely the first tile in the next strip of the block (here vertical strip 52) .
  • strip offset register 104 contains the value (-2036 words) which, when summed with the current contents of line address register 75, points to word W0 in row R0 of tile 27-11. The offset sum is loaded into line address register, so that its address contents now point toward W0 in row R0 of tile 27-11.
  • Multiplexer 90 is again controlled to select input port 91. Addresses are now generated for tiles 27-11 and 27-15 of strip S2 in the same sequential manner as described above for tiles 27-12 and 27-16 of strip SI. When address codes have been generated for each of the tiles of strip S2, each of counters 120, 122 and 126 will have been decremented to zero, indicating to the processor that the entire block has been processed.
  • the DMA transfer operation of the present example involves a transfer, translation and rotation of a portion of the bit map imagery data from one frame store to another
  • the example has been presented for purposes of a non- limitative illustration.
  • the transfer could just as easily take place between other source and destination entities (e.g. between source and destination locations of the same storage space, such as frame store 11) .
  • the intervening orientation change (via rotation device 31) is not an essential part of the DMA mechanism of the present invention. Data may be transferred, as is.

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Abstract

A DMA mechanism for accessing a selected portion of an information storage matrix subdivides the matrix into a plurality of tiles, each containing a sub-matrix of addressable storage locations. Address codes for accessing a block of tiles that correspond to the selected portion of the matrix are generated by storing the starting address of a first row of a first prescribed tile of the block and successively addressing groups of storage locations within each of the successive rows of that tile, by combining word and line address modifiers with the starting line address. Using additional codes which delineate the size of the block, this process is repeated, as necessary, on a tile-by-tile basis, for each tile in the block.

Description

OFFSET-BASED DMA MECHANISM
FIELD OF THE INVENTION
The present invention relates in general to information storage and retrieval systems and is particularly directed to a direct memory access mechanism for rapidly accessing a selected portion of a data base, such as a plurality of tiles within an image bit map memory, by means of a dedicated, offset-based, address control architecture.
BACKGROUND OF THE INVENTION
Accessing discrete portions of a large data base, such as a bit map memory which may have a storage capacity that accommodates a 3200 by 3000 pixel matrix, is typically accomplished in one of two ways:
1. Building a linked list of addresses through which a block of tiles that make up the desired portion of the image are effectively 'chained' together. Because such a list requires the host processor to generate a vector-based sequence of addresses, any change in the parameters of the portion of the data base to be accessed requires a substantial amount of processing time for 'restructuring' the pointers of the list.
2. The CPU calculating the address of each pixel.
SUMMARY OF THE TVEN IQN
In accordance with the present invention, this processor overhead burden is removed by means of a dedicated address generation architecture which controllably combines a single starting address supplied by the processor with a set of predefined 'offsets' and steps through each of the tiles of a block of tiles corresponding to that portion of the data base involved in the transfer. To this end the address generation architecture of the present invention contains a line address storage register which is coupled to receive, from the host processor, an address code representative of a first set of addressable storage locations of a first row of a first one of the block of tiles involved in the transfer. A respective row of a tile is subdivided into sets of address words, each of which is associated with, a plurality of pixel locations .e.g.. 16 pixel locations for Bitoneal Images) in the bit map data base. By successively incrementing a first up-counter until its stored value reaches that of a first 'offset' and combining (summing) the contents of the up-counter with the starting address supplied by the processor in an address code modifier (adder) there is produced a sequence of address codes respectively associated with successive sets of storage locations of that row. After stepping through the addresses of the first row, the address generator couples the adder to a second 'line offset' code modifier which, when combined with the contents of said line address store, yields an address code representative of a first set of addressable storage locations of another (e.g. the second or next) row of the tile, which now becomes the base address stored in the .line address register. This process is repeated until each row of the tile has been processed. Once the first tile has been proce. id, the contents of the line address register are again offset, by summing its currently stored address with a third 'tile offset' code modifier representative of the sequential address displacement between the first set of addressable storage locations of the last row of the first tile and the first set of addressable storage locations of the first row of the next tile of one strip of tiles within the block and that value is loaded into the line address register as a new base address. This process is repeated until the last tile in the strip has been processed.
Since the block contains adjacent strips of tiles, a fourth strip offset is stored. This code is representative of the sequential address displacement between the first set of addressable storage locations of the last row of a last tile of one strip of tiles and the first set of addressable storage locations of the first row of addressable storage locations of a first tile of another strip of tiles. Again, the fourth offset is used as an offset to the line address register to specify the starting address of the next strip. This sequential offset reference and stepping process is continued through all the strips of the block to complete the DMA transfer.
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 diagrammatically shows an information storage and retrieval system in which the memory access mechanism of the present invention may be employed; Figure 2 diagrammatically shows the configuration of a direct memory access unit 41 of Figure 1;
Figure 3 diagrammatically illustrates the hierarchical relationship among a frame store matrix and respective components of a block of addresses to be accessed by the DMA unit of the present invention;
Figure 4 diagrammatically illustrates a pixel matrix subdivided into a plurality of tiles 17-1...17-16, each tile corresponding to a sub- matrix of J=64 rows by K=64 columns of addressable storage locations; and
Figure 5 diagrammatically shows the storage space of destination frame store 21 subdivided into a plurality of tiles 27-1...27-16.
DETAILED DESCRIPTION
Before describing in detail the particular improved direct memory accessing mechanism in accordance with the present invention, it should be observed that the present invention resides primarily in a novel structural combination of conventional digital signal processing circuits and components and not in the particular detailed configurations thereof. Accordingly, the structure, control and arrangement of these conventional circuits and components have been illustrated in the drawings in readily understandable block diagram format to show only those specific details that are pertinent to the present invention, so as not to obscure the disclosure with structural details which will be readily apparent to those skilled in the art having the benefit of the description herein. Thus, the block diagram il. .trations do not necessarily represent the mechanical structural arrangement of the exemplary system, but are primarily intended to illustrate the major structural components of the system in a convenient functional grouping, whereby the present invention may be more readily understood.
Referring now to Figure 1, a non- limiting example of an information storage and retrieval system in which the offset-based direct memory access mechanism of the present invention may be employed is diagrammatically shown as comprising an imagery data processing system having a first, or source, frame store 11, which contains data representative of a bit map image 13 to be displayed by an associated display terminal 15. The bit map itself comprises an M row by N column array or matrix of pixels and, as a simplified illustration, may be considered to comprise a 256X256 array of pixels, subdividable into a plurality (e.g. sixteen) of pixel 'tiles' 17-1 ...17-16, each tile comprising a 64X64 pixel sub-array, or sub-matrix. Also shown in Figure 1 is a second, or destination, frame store 21 which, like frame store 11, is capable of storing data representative of an MXN bit map array that may be displayed on an associated display terminal, such as display terminal 21, or a separate device (not shown) . Each of frame stores 11 and 21 has its data port coupled to a data bus 25 through which imagery-representative data, accessed from either of frame stores 11 and 21, may be coupled to an digital-analog converter 26, which converts the pixel control codes on bus 25 into analog format for defining the energization of the respective pixels of display 15. The storage and retrieval system of Figure 1 further includes a data orientation device, such as a conventional data rotator unit 31, which is coupled to data bus 25 and rotates (e.g. performs a 90° rotation of) a block of data supplied to its data port 33.
In accordance with the present invention, addressing of the respective storage locations of each of frame stores 11 and 21, for reading and writing data to and from memory, is effected by means of a Direct Memory Access (DMA) unit 41, shown in detail in Figure 2 to be described below. Rather than generate frame store address signals which effectively perform a read/write transfer sequence, on a line by line basis, which requires addressing all N columns of every row that contains data to be transferred, DMA unit 41 employs a set of offsets that are used to sequentially update the base address with a line address register, in the course of generation address signals only for storage locations associated with those tiles that make up the portion of the frame store to be accessed. By using this set of offsets to generate address signals on a tile by tile basis, and only for those tiles associated with storage locations to be accessed, direct data transfers from one memory location to another and between different devices can be rapidly effected.
More particularly, in the exemplary imagery data storage and retrieval system of Figure 1, it will be assumed that the operation to be performed involves a transfer, a translation and a rotation of a portion of the bit map imagery data within frame store 11 to frair '.ore 21. By translation is meant that the dest ..tion location, within the bit map of frame store 21, of the transferred portion of the image is different from its original location within the bit map in frame store 11.
Specifically, with reference to the sixteen tile bit map 17 within frame store 11, it will be assumed that it is desired to transfer that portion of the bit map, which is definable as a block 51 of tiles 17-1, 17-2, 17-5 and 17-6, to a destination location within the bit map 27 stored by frame store 21, denoted by a block 52 of tiles 27-11, 27-12, 27-15 and 27-16. As shown in Figure 1, the location of 'destination' block 52 in the bit map 27 of frame store 21 is in the lower right-hand corner of the bit map 27, whereas the location of 'source' block 51 is in the upper left-hand corner of bit map 17 of frame store 11, so that the transfer between frame stores effectively performs a translation of the location of the selected portion of the image. It should be noted that the presently described example of a transfer between separate frame stores is for purposes of a non-limitative illustration. The transfer could just as easily take place between other source and destination entities (e.g. between source and destination locations of the same storage space such as within frame store 11, per se) .
In addition to a translation of the transferred portion of the image, the ir gery data within source block 51 is also to undergo a 90° clockwise rotation relative to its orientation within frame store 11. Letting the imagery data within each of the tiles of frame store 11 be represented by an enlarged reference numeral associated with the numerical position of the tile within the sixteen tile matrix, then an associated set of vertically oriented number images 1, 2, 5, and 6 shown within respective tiles 17-1, 17-2, 17-5 and 17-6 of source block 51, after being when rotated clockwise 90°, will be transferred to tiles 27-12, 27-16, 27-11 and 27-15, respectively, of destination block 52 in horizontal orientation, as shown.
Referring now to Figure 2, DMA unit 41 is diagrammatically shown as having an input port 61 which is coupled to the control bus 63 of an attendant control processor (not shown) . Via control bus 63, the control processor supplies a starting address code representative of the starting address of the block of tiles involved in the data transfer. Thus, in the present example, for initiating a read-out of block 51 of bit map 17, port 61 receives a starting address code representative of a starting address in the first row of tile 17-1. Normally, data is accessed as multi-bit words or sets, so that the starting address will be the address where the first word in the first line of the tile is stored. In the present example of 64 pixel locations per row of an individual tile, pixel data may be accessed in words of sixteen pixel addresses per word address, so that there are four words per tile row.
Input port 61 is coupled to a first input 71 of a multiplexer 70, the output port 74 of which is coupled to- an output register 73 and to a line register 75. Output register 73 is coupled to output port 81, while line register 75 is coupled to a first port 83 of an address code combiner (here an adder) 80, a second port 85 of which is coupled to output port 95 of a 4:1 multiplexer 90. Adder 80 combines or sums the address code stored in line register 75 with an address code modifier supplied from multiplexer 90 and couples the resulting sum or 'modified' address code to a second input port 72 of multiplexer 70. During the generation of successive address codes for accessing the respective tiles of a block involved in a DMA transfer, multiplexer 70 couples input port 72 to its output port 74, so that the modified address code generated by adder 80 is coupled to output register 73 for application to output port 81.
Although output port 74 of multiplexer 70 is also coupled to line address register 75, line address register 75 is not updated in the same manner as output register 73. Instead, the contents of line address register 75 are sequentially incremented only when one of a set of input ports 92-94 of multiplexer 90, to which line, file and offset codes are respectively supplied, is selected. The selected offset code is summed in adder 90 with the contents of the line address register 75 and then rewritten back into register 75 (by way of multiplexer 70) , in order to effectively step through successive address of the block of files involved in the transfer.
The input ports to multiplexer 90 include an input port 91 coupled to the output of a tile width up-counter 111, the input of which is coupled to a tile width register 101. Each of tile width counter 111 and tile width register 101 is also coupled to a comparator 113, which generates an output in response to the contents of tile width counter 111 matching the tile width code stored in tile width register 101. By 'tile width' is meant the number of words that are contained in a row of a tile. As pointed out above, data is normally accessed as multi-bit words. In the present example of sixty-four pixels per row, with sixteen bits per word, the total word width of an individual tile is four words. As a result, to step through (or sequentially scan) the four words of a respective tile row, up-counter 111 is successively incremented from an initial (reset) value of zero until its count value matches the value (e.g. three for the present example of four words per row) stored in tile width register 101. When a match occurs, comparator 113 produces an output which causes tile width counter 111 to be reset and causes multiplexer 90 to select one of its other input ports (92, 93 and 94) depending upon where in the block of tile the address scan is currently located. Thus, as counter 111 is being incremented, it generates a sequence of address code modifiers which are summed in adder 83 with the contents of line address register 75 to yield a sequence of modified address codes associated with respectively different words of address space within that one of the rows of a respective tile currently pointed to by line address register 75. A second input 92 is coupled to line offset register 102 which stores a line offset code representative of the displacement (in words) between the same word address location for successive rows of a tile. For a matrix line vidth of 256 bits, 1 » displacement between the first word address or. row i and row itl of a respective tile is 16 words.
A third input port 93 of multiplexer 90 is coupled to a tile offset register 103, which stores a 'tile offset' address code modifier. The value of the tile offset modifier is such that when combined in adder 80 with the contents of line address register 75, the resulting sum yields an address code representative of the first row or line another (the next successive) tile of the block of tiles involved in the transfer.
A fourth input port 94 of multiplexer 90 i? coupled to a strip offset register 104, which st„res a 'strip offset' address code modifier.
The value of the strip offset modifier represents the sequential address displacement between the address of the last or Jth row of the last tile in one strip of tiles and that of the next strip of tiles within the block of interest. A tile strip is a subdivision of the tile block in a selected address scan direction (e.g. horizontally, or parallel to the rows or lines of the matrix) . In the present example, block 51 is comprised of two adjacent tile strips SI and S2, each strip containing two tiles. Strip SI contains tiles 17-1 and 17-2, while strip S2 contains tiles 17-5 and 17-6. When the 'strip offset' code is summed with the contents of the line address store, the contents of output register 73 are updated with an address code representative of the firπt row of the first tile in the next strip.
Figure 3 diagrammatically illustrates the hierarchical relationship among the frame store matrix and the respective components of a block of addresses to be accessed by the DMA unit of the present invention. In the present example of a frame store having a 256X256 pixel matrix, block 51 is comprised of two strips SI and S2, strip SI containing two tiles
17-1, 17-2 and strip S2 containing two tiles 17-5 and 17-6. A respective tile, in turn, has a 'height' of sixty-four rows, as exemplified by tile 17-1. Finally, a respective row of sixty- four pixel locations or columns contains four words, each of which comprises sixteen pixel locations.
To determine when DMA address codes have been generated for the entire block of tiles, a 'strip' down-counter 120 is employed. At the start of the DMA process, counter 120 is loaded with the number of tile strips in the block (two in the present example) . Counter 120 is then successively decremented as each strip of tiles is processed. When counter 120 expires, or is decremented to zero, it is determined that there are no further strips to be processed for that block. Similarly, to determine when address codes have been generated for all of the tiles in a respective strip of tiles, a 'tile' down-counter 122 and an associated 'tile' register 124 are employed. 'Tile' register 124 is initially loaded with the number of tiles per strip (two in the present example) , and the tile code is entered into tile counter 122. Like strip counter 120, tile down-counter 122 is successively decremented as each strip of tiles is processed. When counter 122 expires or is decremented to zero it is determined that there are no further tiles to be processed for that strip. The contents of tile register 124 are then transferred to c inter 122 for processing the next strip.
To determine when DMA address codes have been generated for all rows of a respective tile, a 'tile height' down-counter 126 and an associated 'tile count' register 128 are employed. 'Tile height' register 126 is initialized with the number of rows per tile (sixty-four in the present example) , and this tile height code is loaded into tile height counter 126. Tile height down-counter 126 is successively decremented as each row of a tile is processed. When counter 126 expires or is decremented to zero it is determined that there are no further rows in the tile to be processed. The contents of tile height register 128 are then transferred to counter 126 for processing the next tile.
As will be described below, as the contents of tile width, tile height, tile and strip counters 111, 126, 122 and 120 are successively changed, multiplexer 90 controllably couples the contents of selected ones of tile width counter 111 and offset registers 102, 103 and 104 to its output port 95, so that, when summed with the contents of line address register 75, there is produced a modification of the original address code coupled to input port 61 that effects a rapid scan through only those storage locations in the frame store associated with the tiles in the block of interest. Other entries in the memory are ignored. OPERATION DMA READ As pointed out above, for purposes of providing an illustrative example, each of frame stores 11 and 21 is presumed to have a storage space that will accommodate a matrix of M=256 rows by N=256 columns of pixel locations. As diagrammatically illustrated in Figure 4, such a matrix may be subdivided into a plurality of sixteen tiles 17-1...17-16, each tile corresponding to a sub-matrix of J=64 rows by K=64 columns of addressable storage locations. The addressable storage locations of a respective row are addressable in successive sets or words of sixteen locations (columns) , so that each row of a tile contains four consecutive words (W0-W3) .
At the start of the process, the control processor supplies to input port 61 an address code representative of the first word WO of the first row of the block of tiles to be involved in the DMA transfer. For the illustrative example, of transferring block 51 containing tiles 17-1, 17-2, 17-5 and 17-6, the processor supplies the address of word WO of the first row of tile 17-1, which is coupled through multiplexer 70 and loaded into line address register 75. Address code offset multiplexer 90 is controlled to select tile width counter 111, which is currently reset. As a consequence, the output of adder 80 is simply the initial address code that has been loaded into line address register 75. This combined address code is coupled through multiplexer 70 and loaded into output register 73, so that the output address code at port 81 points to the upper left- hand corner address of tile 17-1, at row 0, address word W0.
Tile width up-counter 111 is then sequentially incremented, so that adder 80, in turn, will sequentially produce increasingly larger sums, thereby modifying the address code supplied to output register 73 and stepping through the successive address words W0-W3 of row R0 of tile 17-1. When the count value in counter 111 reaches the tile width count value (3) that has been pre-loaded into tile width register 101, comparator 113 produces an output, which resets tile width counter 111 to be reset, causes tile height counter 126 to be decremented to a value of 63 from its pre-loaded value of 64 and causes address code offset multiplexer 90 to select input port 92, to which the contents of line offset register 102 are coupled. For the present example of an overall line width of sixteen words (four words per row of four tiles per width of the matrix) , line offset address register 102 stores a line offset value of sixteen which, when combined with the contents of line address register 75, will point produce an address that points to the first address of the second row Rl of tile 17-1. This new line address is then stored in line address register 75. The multiplexer 90 is controlled to select input port 91 and the above sequence operation is repeated, thereby producing successive addresses that step through the four words W0-W3 of the second row Rl of tile 17-1.
These steps are repeated for each of the sixty-four rov-_ of tile 17-1, until address codes have been generated for all 64 rows of tile 17-1. At the completion of the sixty-fourth row (R63), the contents of line address counter 75 will point o the first word W0 of row R63. Since tile height down-counter 126 has been decremented to zero, its output changes state. The signal causes address the contents of tile down-counter 122 to be decremented and offset multiplexer 90 to select input port 93 to which the contents of tile offset register 103 are coupled. The contents of tile offset register 103 is a value representative of the sequential address displacement between the first word WO of row R63 of tile 17-1 (the current value of line address register 75) and the first word WO of the first row R0 of tile 17-2, namely the next tile in the strip. Using the parameters of the present example, tile offset register 103 contains the value (-1004) which, when summed with the current contents of line address register 75, points to word W0 in row R0 of tile 17-2, namely the fifth word address in the first line of the matrix. This value is loaded into line address register 75. Multiplexer 90 is then controlled to select input port 91. Addresses are now generated for tile 17-2 in the same sequential manner as described above for tile 17. When address codes have been generated for all 64 rows of tile 17-2, the contents of line address counter 75 will again point to the first word W0 of row R63. Since tile height down- counter 126 has again been decremented to zero, its output changes state, causing the contents of tile down-counter 122 to be decremented. Tile counter 122 now has been decremented to zero, so that its output also changes state, which, in turn, decrements strip down-counter 120 and causes offset multiplexer 90 to select input port 94, to which the contents of strip offset register 104 are coupled. The contents of strip offset register 104 contain a value representative of the sequential address displacement between the first word W0 of row R63 of tile 17-2 (the current value of line address register 75) and the first word WO of the first row R0 of tile 17-5, namely the first tile in the next strip S2 of the block. For the parameters of the present example, strip offset register 104 contains a value (12) which, when summed with the current contents of line address register 75, points to word WO in row R0 of tile 17-5. This new offset sum is loaded into line address register 75. Multiplexer 90 is controlled to select input port 91 and addresses are now generated for tiles 17-5 and 17-6 of strip S2 in the same sequential manner as described above for tiles 17-1 and 17-2 of strip SI. When address codes have been generated for each of tiles of strip S2, each of counters 120, 122 and 126 will have been decremented to zero, indicating to the processor that the entire block has been processed.
In the present example, the data read out of block 51 of frame store 11 is rotated (via data rotation device 31, Figure 1) and translated into a block of tiles 27-11, 27-12, 27-15 and 27- 16 of frame store 21. If the DMA transfer operation involved only a translation, then the generation of write addresses for writing data into the memory space of frame store 21 would involve essentially the same tile processing sequence described above, except for the starting address. However, because of the rotation, the contents of the first tile (17-1) read out from block 51 are written into a tile location in destination block 52 (upper right-hand corner tile 27-12) that is displaced relative to the location of tile 71 in source block 51 (upper left-hand corner) . As a consequence, in addition to a new initial value of the first address of the destination block 52 that is coupled to input port 61, the offset parameters that are stored in line and tile offset registers 102 and 103 are different from those involved in the read operation.
DMA WRITE
More specifically, as diagrammatically shown in Figure 5, the storage space of frame store 21 is subdivided into a plurality of sixteen tiles 27-1...
27-16, each tile corresponding to a sub-matrix of J=64 rows by K=64 columns of addressable storage locations. Like frame store 11, the addressable storage locations of a respective row are addressable in successive sets or words of sixteen locations (columns) , so that each row of a tile contains four consecutive words (W0-W3) .
At the start of the process, the control processor supplies to input port 61 an address code representative of the first word W0 of the first row of the block of tiles to be involved in the DMA write operation. For the illustrative example of writing to block 52 (tiles 27-11, 27- 12, 27-15 and 27-16), because of the rotation, the processor supplies the address of word WO of the first row of tile 27-12, which is coupled through multiplexer 70 and loaded into line address register 75. Again, at the start of the operation, address code offset multiplexer 90 selects input port 91, i.e., tile width counter ill, which is currently reset. As a consequence, the output of adder 80 is simply the address code that has been loaded into line address register 75. This address code is coupled through multiplexer 70 and loaded into output register 73, so that the output address code at port 81 points to the upper left-hand corner address of tile 27- 12, at row 0, address word WO. Tile width up-counter 111 is then sequentially incremented, so that adder 80 will modify the address code supplied to output register 73, stepping through the successive address words W0-W3 of row R0 of tile 27-12. When the count value in counter 111 reaches the tile width count value (3) that has been pre-loaded into tile width register 101, comparator 113 produces an output, which resets tile width counter 111, causes tile height counter 126 to be decremented and causes address code offset multiplexer 90 to be coupled to line offset register 102. For an overall line width of sixteen words (four words per row of four tiles per width of the matrix) , line offset address register 102 stores a line offset value of (16) which, when combined with the contents of line address register 75, will point produce an address that points to the first address of the second row Rl of tile 27-12. This new line address is then stored in line address register 75, multiplexer 90 again selects input port 91 and the above sequence repeated, thereby producing successive addresses that step through the four words W0-W3 of the second row Rl of tile 27-12. These steps are repeated for each of the sixty-four rows of tile 27-12 until address codes have been generated for all of its 64 rows. At the completion of the .sixty-fourth row, the contents of line address counter 75 will point to the first word W0 of row R63. Since tile height down-counter 126 has been decremented to zero, its output changes state. The signal causes the contents of tile down-counter 122 to be decremented and offset multiplexer 90 to be coupled to tile offset register 103. The contents of tile offset register 103 contain an offset value representative of the sequential address displacement between the first word W0 of row R63 of tile 27-12 (the current value of line address register 75) and the first word W0 of the first row R0 of tile 27-16, namely the next tile in the (vertical due to the 90° rotation) strip SI containing tile 27-12. Using the parameters of the present example, tile offset register 103 contains a value here (+16 words) which, when summed with the current contents of line address register 75, points to word W0 in row R0 of tile 27-16, namely the first word address in line 193 of the matrix. This new base address is loaded into line address register 75 and multiplexer 90 controlled to select input port 91. Addresses are now generated for tile 27-16 in the same sequential manner as described above for tile 27- 12. When address codes have been generated for all 64 rows of tile 27-16, the contents of line address counter 75 will again point to the first word W0 of row R63. Since tile height down- counter 126 has again been decremented to zero, its output changes state, causing the contents of tile down-counter 122 to be decremented. Tile counter 122 - too now has been decremented to zero, so that its output changes state. This signal, in turn, decre-rtents strip down-counter 120 and causes offset multiplexer 90 to select input port 94 to which strip offset r gister 104 is coupled. The contents of strij. offset register 104 contain a value representative of the sequential address displacement between the first word WO of row R63 of tile 27-16 (the current value of line address register 75) and the first word WO of the first row R0 of tile 27-11, namely the first tile in the next strip of the block (here vertical strip 52) . For the parameters of the present example, strip offset register 104 contains the value (-2036 words) which, when summed with the current contents of line address register 75, points to word W0 in row R0 of tile 27-11. The offset sum is loaded into line address register, so that its address contents now point toward W0 in row R0 of tile 27-11. Multiplexer 90 is again controlled to select input port 91. Addresses are now generated for tiles 27-11 and 27-15 of strip S2 in the same sequential manner as described above for tiles 27-12 and 27-16 of strip SI. When address codes have been generated for each of the tiles of strip S2, each of counters 120, 122 and 126 will have been decremented to zero, indicating to the processor that the entire block has been processed.
As pointed out previously, although the DMA transfer operation of the present example involves a transfer, translation and rotation of a portion of the bit map imagery data from one frame store to another, it is to be observed that the example has been presented for purposes of a non- limitative illustration. The transfer could just as easily take place between other source and destination entities (e.g. between source and destination locations of the same storage space, such as frame store 11) . Moreover, the intervening orientation change (via rotation device 31) is not an essential part of the DMA mechanism of the present invention. Data may be transferred, as is.
While we have shown and described an embodiment in accordance with the present invention, it is to be understood that the same is not limited thereto, but is susceptible to numerous changes and modifications as known to a person skilled in the art, and we therefore, do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.

Claims

WHAT IS CLAIMED;
1. For use with an information storage device containing a matrix of M rows by N columns of addressable storage locations, said matrix being subdividable into a plurality of tiles of addressable storage locations, each tile corresponding to a sub-matrix of J rows by K columns of addressable storage locations, the addressable storage locations of a respective row being addressable in successive words of storage addresses, a method for generating address codes for accessing a selected portion of said matrix of addressable storage locations in terms of a block made up of one or more strips of said tiles, comprising the steps of:
(a) storing, in a line address store, an address code representative of a first word of addressable storage locations of a first row of one of the tiles of said block;
(b) providing a plurality of offset codes respectively representative of the geometries of said one or more strips, the tiles of a strip, the rows of a tile, and the words of a row; and
(c) controllably modifying the address code stored in step (a) with selected ones of the offset codes provided in step (b) , so as to produce a sequence of modified address codes associated with respectively different storage locations within said block.
2. A method according to claim 1, wherein step (b) includes the step of providing a row offset code representative of the displacement from the first word of a row of a tile to the first word of the next row of that tile.
3. A method according to claim 2, wherein step (b) includes the step of providing a tile offset code representative of the displacement from the first word of the last row of a tile of a respective strip to the first word of the first row of the next tile in said respective strip.
4. A method according to claim 3, wherein step (b) includes the step of providing a strip offset code representative of the displacement from the first word of the last row of a tile of one strip to the first word of the first row of the first tile in another strip.
5. For use with an information storage device containing a matrix of M rows by N columns of addressable storage locations, a method of accessing a portion of said storage device comprising the steps of:
(a) subdividing said portion of said storage device into a plurality of tiles of addressable storage locations, each tile containing a sub-matrix of J rows by K columns of addressable storage locations;
(b) subdividing each of said J rows into a plurality of successive groups of addressable storage locations;
(c) beginning with a first prescribed tile of said plural tiles, successively addressing the groups of storage locations within each of the successive J rows thereof; (d) for a r* spective additional tile _»f said plurality of tiles, successively addressing the groups of storage locations within each of the successive J rows thereof;
(e) repeating step (d) , as necessary, on a tile-by-tile basis, for each tile of said plurality of tiles, until all storage locations of each tile of said plurality of tiles have been addressed.
6. For use with an information storage device containing a matrix of M rows by N columns of addressable storage locations, a method of accessing a portion of said storage device comprising the steps of:
(a) subdividing said storage device into a plurality of tiles of addressable storage locations, each tile containing a sub-matrix of J rows by K columns of addressable storage locations;
(b) subdividing each of said J rows into a plurality of successive groups of addressable storage locations;
(c) generating an address code representative of a first group of addressable storage locations of one of the J rows of one of said plurality of tiles, said one tile being contained within said portion of said storage device to be accessed; (d) sequentially modifying the address code generated in step (c) , so as successively address successive groups of storage locations within said one of the successive J rows of said first one tile; (e) generating an address code representative of a first group of addressable storage locations of another of the J rows of said one tile; (f) sequentially modifying the address code generated in step (e) so as successively address successive groups of storage locations within said another of the J rows of said one tile; (g) repeating, as necessary, steps (e) and (f) , until address codes have been generated for all of the storage locations of the J rows of said one tile;
(h) repeating steps (c)-(g) for a respective one or more additional tiles, as necessary on a tile-by-tile basis, each of which additional tiles is contained within said portion of said storage device, until address codes have been generated for all storage locations of each tile contained within said portion of said storage device.
7. A method according to claim 6, wherein step (e) comprises modifying the address code generated in step (c) by a value representative of the number of said groups of addressable storage locations contained within one of the M rows of said storage device, thereby generating an address code representative of a first group of addressable storage locations of another of the J rows of said one tile.
8. A method according to claim 7, wherein step (h) includes the step of modifying the address code associated with the first group of addressable storage locations of the Jth row of said one tile by a value representative of the sequential address displacement between said first group of addressable storage locations of said Jth row and the first group of addressable storage locations of the first row of addressable storage locations of said another tile, thereby generating the address of said first group of addressable storage locations of the first row of said another tile.
9. A method according to claim 8, wherein step (h) comprises:
(hi) repeating steps (c)-(g) for each respective tile of a strip of adjacent tiles, until address codes have been generated for all storage locations of each of said adjacent tiles, and
(h2) modifying the address code associated with the first group of addressable storage locations of the Jth row of the last tile of said strip of adjacent tiles by a value representative of the sequential address displacement between said first group of addressable storage locations of said Jth row of said last tile and the first group of addressable storage locations of the first row of addressable storage locations of a first tile of another strip of adjacent tiles, thereby generating the address of said first group of addressable storage locations of the first row of said first tile of said another strip of adjacent tiles.
10. A method according to claim 9, wherein strips of adjacent tiles are contiguous with one another.
11. For use with an information storage device containing a matrix of M rows by N columns of addressable storage locations, said matrix being subdividable into a plurality of tiles of addressable storage locations, each tile corresponding to a sub-matrix of J rows by K columns of addressable storage locations, the addressable storage locations of a respective row being addressable in successive sets of storage addresses, a method of generating address codes for accessing a selected portion of said matrix of addressable storage locations in terms of a block of said tiles, comprising the steps of:
(a) generating an address code representative of a first set of addressable storage locations of one of the J rows of one of said block of tiles;
(b) sequentially modifying the address code generated in step (a) , so as successively address successive sets of storage locations within said one of the successive J rows of said one tile;
(c) generating an address code representative of a first set of addressable storage locations of another of the J rows of said one tile;
(d) sequentially modifying the address code generated in step (c) , so as successively address successive sets of storage locations within said another o4 the J rows of said one tile; (e) repeating, as necessary, steps (c) and (d) , until address codes have been generated for all of the storage locations of the J rows of said one tile;
(f) repeating steps (a) -(e) , as necessary, for one or more additional tiles of said block until address codes have been generated for all storage locations of each tile of said block.
12. A method according to claim 11, wherein step (c) comprises modifying the address code generated in step (a) by a value representative of the number of said sets of addressable storage locations contained within one of the M rows of said storage device, thereby generating an address code representative of a first set of addressable storage locations of another of the J rows of said one tile.
13. A method according to claim 12, wherein step (f) includes the step of modifying the address code associated with the first set of addressable storage locations of the Jth row of said one tile by a value representative of the sequential address displacement between said first set of addressable storage locations of said Jth row and the first set of addressable storage locations of the first row of addressable storage locations of said another tile, thereby generating the address of said first set of addressable storage locations of the first row of said another tile.
14. A method according to claim 13, wherein said block of tiles comprises plural strips of tiles, said strips being adjacent to one another, and step (f) comprises: (fl) repeating steps (a)-(e) for each respective tile of a respective strip, until address codes have been generated for all storage locations of each tile in the strip; and (f2) modifying the address code associated with the first set of addressable storage locations of the Jth row of the last tile of said strip by a value representative of the sequential address displacement between said first set of addressable storage locations of said Jth row of said last tile and the first set of addressable storage locations of the first row of addressable storage locations of a first tile of another strip of tiles, thereby generating the address of said first set of addressable storage locations of the first row of said first tile of said another strip of tiles.
15. For use with an information storage device containing a matrix of M rows by N columns of addressable storage locations, said matrix being subdividable into a plurality of tiles of addressable storage locations, each tile corresponding to a sub-matrix of J rows by K columns of addressable storage locations, the addressable storage locations of a respective row being addressable in successive sets of storage addresses, a method for generating address codes for accessing a selected portion of said matrix of addressable storage locations in terms of a block of said tiles, comprising the steps of: (a) storing, in a line address store, an address code representative of a first set of addressable storage locations of a first of the J rows of one of said block of tiles; (b) generating a sequence of first address code modifiers, each of which is representative of a value which, when combined with the contents of said line address store, yields an address code associated with a respectively different set of storage locations within said one of the J rows of a tile;
(c) storing a second address code modifier which, when combined with the contents of said line address store, yields an address code representative of a first set of addressable storage locations of another of the J rows of said one tile;
(d) storing a third address code modifier representative of the sequential address displacement between said first set of addressable storage locations of said Jth row and the first set of addressable storage locations of the first row of addressable storage locations of said another tile, so that, when combined with the contents of said line address store, yields an address code representative of the first set of addressable storage locations of the first row of said another tile; and
(e) combining a selected one of the first, second and third address code modifiers with the contents of said line address store and coupling the combined address code to an output port, as a generated output address code.
16. A method according to claim 15, wherein said block of tiles comprises plural strips of tiles, said strips being adjacent to one another, and further including the step of: (f) storing a fourth address code modifier representative of the sequential address displacement between said first set of addressable storage locations of said Jth row of a last tile of one strip of tiles and the first set of addressable storage locations of the first row of addressable storage locations of a first tile of another strip of tiles, and wherein step (e) includes combining a selected one of the first, second, third and fourth address code modifiers with the contents of said line address store and coupling the combined address code to said output port.
17. A method according to claim 16, wherein step (b) comprises successively changing the contents of a first counter from an initial prescribed value, so as to generate said sequence of first address code modifiers.
18. A method according to claim 17, wherein step (e) includes successively changing the contents of a second counter from an initial predetermined value until said second counter has been changed J times corresponding to the number of J rows in a tile, and thereupon combining said third address code modifier with the address code stored in said line address store.
19. A method according to claim 18, wherein step (e) further includes successively changing the contents of a third counter from an initial predetermined value until said third counter has been changed by a value corresponding to the number of tiles in a strip, and thereupon combining said fourth address code modifier with the address code stored in said line address store.
20. A method according to claim 19, further including the step of:
(g) successively changing the contents of a fourth counter from an initial value, representative of the number of strips in said block of tiles, until address codes have been generated for each of the strips of said block.
21. For use with video display apparatus having a matrix of M rows by N columns of pixels which are controllably energized by video control signals representative of image information stored in memory, said memory containing a plurality of addressable storage locations respectively associated with the pixels of said array, a method of transferring a portion of an image displayed by the matrix of pixels of said video display apparatus from one portion of the matrix of pixels of said display to another portion of the display pixel matrix, with a given orientation, comprising the steps of: (a) subdividing said one portion of said matrix of pixels into a first block of a plurality of pixel tiles, each pixel tile containing a sub-matrix of pixels;
(b) beginning with a first prescribed tile within said first block, successively reading out the contents of storage locations of said memory associated with the pixels of said tile;
(c) for a respective additional tile of block, successively reading out the contents of storage locations of said memory associated with the pixels of said respective additional tile;
(d) repeating step (c) , as necessary, on a tile-by-tile basis, for each tile of said plurality of tiles, until the contents of all storage locations of said memory associated with each tile of said plurality of tiles have been read out;
(e) defining the orientation in which said portion of said image is to be displayed at said another portion of said display pixel matrix;
(f) subdividing said another portion of said matrix of pixels into a second block of a plurality of pixel tiles, each tile containing a sub-matrix of pixels; (g) beginning with a first prescribed tile of said second block, successively writing imagery data representative of said portion of said image, having the orientation defined in step (e) , into storage locations of said memory associated with the pixels of said the first prescribed tile of said second block;
(h) for a respective additional tile of said second block, successively writing imagery data into storage locations of said memory associated with the pixels of said additional tile; and
(i) repeating step (h) , as necessary, on a tile-by-tile basis, for each tile of the second block, until imagery data having the orientation defined in step (f) has been written into those storage locations of said memory associated with each tile of the second block.
22. A method according to claim 21, wherein step (e) comprises defining the orientation in which said portion of said image is to be displayed at said another portion of said display pixel matrix as being different from the orientation of said portion of said image at said one portion of said display pixel matrix.
23. For use with an information storage device containing a matrix of M rows by N columns of addressable storage locations, said matrix being subdividable into a plurality of tiles of addressable storage locations, each tile correspond ig to a sub-matrix of J rows by K columns of addressable storage locations, the addressable storage locations of a respective row being addressable in successive sets of storage addresses, an apparatus for generating address codes for accessing a selected portion of said matrix of addressable storage locations in terms of a block of said tiles, comprising: an input port to which an address code representative of a first set of addressable storage locations of a first of the J rows of one of said block of tiles is coupled; an output port from which address codes for accessing said selected portion of said matrix of addressable storage locations are supplied; a line address store for storing the address code coupled to said input port; an address code combiner, coupled to combine the address code stored in said line address store with a selected one of a plurality of address code modifiers, the output of said adder being coupled to said output port; first means for generating a sequence of first address code modifiers, each of which is representative of a value which, when combined with the contents of said line address store, yields an address code associated with a respectively different set of storage locations within said one of the J rows of a tile; second means for storing a second address code modifier which, when combined with the contents of said line address store, yields an address code representative of a first set of addressable storage locations of another of the J rows of said one tile; third means for storing a third address code modifier representative of the sequential address displacement between said first set of addressable storage locations of said Jth row and the first set of addressable storage locations of the first row of addressable storage locations of said another tile, so that, when combined with the contents of said line address store, yields an address code representative of the first set of addressable storage locations of the first row of said another tile; and fourth means for controllably coupling a selected one of the first, second and third address code modifiers to said address code combiner to be combined with the contents of said line address store and coupled to said output port.
24. An apparatus according to claim 23, wherein said block of tiles comprises plural strips of tiles, said strips being adjacent to one another, and further including: fifth means for storing a fourth address code modifier representative of the sequential address displacement between said first set of addressable storage locations of said Jth row of a last tile of one strip of tiles and the first set of addressable storage locations of the first row of addressable storage locations of a first tile of another strip of tiles, so that, when combined with the address code stored by said line address store, yields the address of said first set of addressable storage locations of the first row of said first tile of said another strip of tiles, and wherein said fourth means includes means for controllably coupling a selected one of the first, second, third and fourth address code modifiers to said address code combiner to be combined with the contents of said line address store and coupled to said output port.
25. An apparatus according to claim 24, wherein said first means includes a first counter, the contents of which are successively changed from an initial prescribed value, so as to generate said sequence of first address code modifiers.
26. An apparatus according to claim 24, wherein said fourth means includes a second counter, the contents of which are successively changed from an initial predetermined value until said second counter has been changed J times corresponding to the number of J rows in a tile, whereupon said fourth means couples said third address code modifier to said address code combiner to be combined with the address code stored in said line address store.
27. An apparatus according to claim 25, wherein said fourth means includes a third counter, the contents of which are successively changed from an initial predetermined value until said third counter has been changed by a value corresponding to the number of tiles in a strip, whereupon said fourth means couples said fourth address code modifier to said address code combiner to be combined with the address code stored in said line address store.
28. An apparatus according to claim 27, further including a fourth counter the contents of which are successively changed from an initial value, representative of the number of strips in said block of tiles, until address codes have been generated for each of the strips of said block.
29. For use with video display apparatus having a matrix of M rows by N columns of pixels which are controllably energized by video control signals representative of image information stored in memory, said memory containing a plurality of addressable storage locations respectively associated with the pixels of said array, an apparatus for transferring a portion of an image displayed by the matrix of pixels of said video display apparatus from one portion of the matrix of pixels of said display to another portion of the display pixel . atrix, with a given orientation, said one portion of said matrix of pixels being subdivided into a first block of a plurality of pixel tiles, each pixel tile of which contains a sub-matrix of pixels, and said another portion of said matrix being subdivided into a second block of a plurality of pixel tiles, each pixel tile of which contains a sub-matrix of pixels, comprising: first means for successively reading out the contents of storage locations of said memory associated with the pixels of each of the tiles of said first block, on a tile-by-tile basis, until the contents of all storage locations of said memory associated with each of the tiles of said first block have been read out; second means for defining the orientation in which said portion of said image is to be displayed at said another portion of said display pixel matrix; and third means for writing imagery data representative of said portion of said image having the orientation defined by said second means into successive storage locations of said memory associated with the pixels of each of the tiles of said second block, on a tile-by-tile basis, until imagery data has been written into those storage locations of said memory associated with each of the tiles of said second block; whereby the generation of video control signals in accordance with the contents of the storage locε ns of said memory so as to energize the pixels or said display will produce an image said portion of which has been transferred from said one portion of said pixel matrix to said another portion of said pixel matrix with said defined orientation.
30. An apparatus according to claim 29, wherein the defined orientation of said portion of said image at said another portion of said display pixel matrix is different from the orientation of said portion of said image at said one portion of said display pixel matrix.
31. For use with an information storage device having a plurality of addressable storage locations that are identifiable in terms of a matrix of M rows by N columns of storage locations, an apparatus for transferring information from storage locations identifiable as being associated with one portion of said matrix to storage locations identifiable as being associated with another portion of said matrix, with a given orientation, said one portion of said matrix being subdivided into a first block of a plurality of tiles, each tile of which contains a sub-matrix of storage locations, and said another portion of said matrix being subdivided into a second block of a plurality of tiles, each tile of which contains a sub-matrix of storage locations, comprising; first means for successively reading out the contents of storage locations of said information storage device associated with the each of the tiles of said first block, on a tile- by-tile basis, until the contents of all storage locations of said information storage device associated with each of the tiles of said first block have been read out; second means for definin the orientation in which the read out contents of storage locations are to be written into said another portion of said information storage device; and third means for writing said read out contents, having an orientation defined by said second means, into successive storage locations of said information storage device associated with each of the tiles of said second block, on a tile- by-tile basis, until said read out contents have been written into those storage locations of said information storage device associated with each of the tiles of said second block.
32. An apparatus according to claim 31, wherein the defined orientation of the read out contents, as written into storage locations of said another portion of said information storage device, is different from its orientation in storage locations of said one portion of said information storage device.
33. For use with an information storage device containing a matrix of M rows by N columns of addressable storage locations, said matrix being subdividable into a plurality of tiles of addressable storage locations, each tile corresponding to a sub-matrix of J rows by K columns of addressable storage locations, the addressable storage locations of a respective row being addressable in successive worSs of storage addresses, an apparatus for generating address codes for accessing a selected portion of said matrix of addressable storage locations in terms of a block made up of one or more strips of said tiles, comprising: a line address store which stores an address code representative of a first word of addressable storage locations of a first row of one of the tiles of said block; means for providing a plurality of offset codes respectively representative of the geometries of said one or more strips, the tiles of a strip, the rows of a tile, and the words of a row; and means for controllably modifying the address code stored in said line address store with selected ones of said plurality of offset codes to produce a sequence of modified address codes associated with respectively different storage locations within said block.
34. An apparatus according to claim 33, wherein said offset code providing means includes means for providing a row offset code representative of the displacement from the first word of a row of a tile to the first word of the next row of that tile.
35. An apparatus according to claim 34, wherein said offset code providing means includes means for providing a tile offset code representative of the displacement from the first word of the last row of a tile of a respective strip to the first word of the first row of the next tile in said respective strip.
36. An apparatus according to claim 35, wherein said offset code providing means includes means for providing a strip offset code representative of the displacement from the first word of the last row of a tile of one strip to the first word of the first row of the first tile in another strip.
37. For use with an information storage device containing a matrix of addressable storage locations, said matrix being subdividable into a plurality of tiles of addressable storage locations, each tile corresponding to a sub-matrix of addressable storage locations, the addressable storage locations of a respective tile being addressable in successive words of storage addresses, a method for generating address codes for accessing a selected portion of said matrix of addressable storage locations in terms of a block made up of one or more tiles, comprising the steps of: (a) storing an address code representative of a first word of addressable storage locations of one of the tiles of said block;
(b) providing a plurality of offset codes respectively representative of different geometry boundaries within said block; and
(c) sequentially modifying the address code stored in step (a) with selected ones of the offset codes provided in step (b) , so as to produce a sequence of modified address codes associated with respectively different storage locations within said block.
38. A method according to claim 37, wherein step (b) includes the step of providing a row offset code representative of the displacement from a first word of one row of a tile to a first word of another row of that tile.
39. A method according to claim 38, wherein step (b) includes the step of providing a tile offset code representative of the displacement from a first word of the last row of a tile of a respective strip of tiles within said block to the first word of a first row of another tile in said respective strip.
40. A method according to claim 39, wherein step (b) includes the step of providing a strip offset code representative of the displacement from a first word of the last row of a tile of one strip to the first word of a first row of a first tile in another strip.
41. For use with an information storage device containing a matrix of addressable storage locations, said matrix being subdividable into a plurality of tiles of addressable storage locations, each tile corresponding to a sub-matrix of addressable storage locations, the addressable storage locations of a respective tile being addressable in successive words of storage addresses, an apparatus for generating address codes for accessing a selected portion of said matrix of addressable storage locations in terms of a block made up of one or more tiles, comprising:
(a) a line.address store which stores an address code representative of a first word of addressable storage locations of one of the tiles of said block;
(b) first means for providing a plurality of offset codes respectively representative of the different geometrical boundaries within said block; and
(c) second means for sequentially modifying the address code stored in said line address store with selected ones of the offset codes provided by said second means so as to produce a sequence of modified address codes associated with respectively different storage locations within said block.
42. An apparatus according to claim 41, wherein said second means includes means for providing a row offset code representative of the displacement from a first word of one row of a tile to a first word of another row of that tile.
43. An apparatus according to claim 42, wherein said second means includes means for providing a tile offset code representative of the displacement from a first word of the last row of a tile of a respective strip of tiles within said block to the first word of a first row of another tile in said respective strip.
44. An apparatus according to claim 39, wherein said second means includes means for providing a strip offset code representative of the displacement from a first word of the last row of a tile of one strip to the first word of a first row of a first tile in another strip.
PCT/US1991/005911 1990-08-20 1991-08-20 Offset-based dma mechanism WO1992003798A1 (en)

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