JPH01130188A - Waveform display device - Google Patents

Abstract

PURPOSE: To attain high speed operation by generating dots by a Y axis counter collectively from plural memory chips. CONSTITUTION: When the value of the Y axis counter 23 is a start point, an output from a register 24 is converted into an output for setting up the bit position of a start point to '1' by a decoder 31, and when a comparator 28 outputs an UP signal, an upper dot generation circuit 35 sets up all bits upper than a start point bit position to '1'. At the time of outputting a DOWN signal, the output from the decoder 31 sets up all bits lower than the start point bit position to '1'. When the value of the counter 23 is an end point, an output from a register 22 is converted into an output for setting up the bit position of the end point to '1' by a decoder 30 and dot generation is executed by reverse operation. Outputs from circuits 34, 35 are sent to a picture memory and a chip is selected to generate dots in a start point or end point cycle in the Y axis direction. Consequently high speed writing can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to means for generating dot signals to a display memory at high speed in a waveform display device such as a measuring instrument.

(Prior Art) Waveform measuring instruments such as digital oscilloscopes and FFT analyzers are required to display time-domain waveforms and frequency-domain waveforms at high speed. Conventionally used waveform display methods for this purpose include a method in which a waveform is drawn by specifying display points one after another using a vector scan type CRT as a 0 display CRT, and a raster scan type CRT. There are also methods for displaying images using image memory. The method described above requires a special circuit to generate the dots, and a. The method uses a general-purpose CRT controller to generate the dots, which generates the X and Y addresses by integrating the slopes. DDA Method (Problems to be Solved by the Invention) However, the method (a) has the disadvantage that the CRT itself becomes expensive. In addition, in method a, the speed of dot generation is slow, at about 500 ns/dot, and in method b, the slope needs to be calculated each time, so the speed of dot generation is slow, and this is realized by hardware. In this case, there is a problem that the hardware becomes complicated.

In addition, when trying to achieve high-speed writing in a circuit that generates dots in a dot generation circuit and writes them to an image memory compatible with a display screen such as a CRT, the bottleneck is the memory cycle time. . Of course, this would be possible by using a high-speed static RAM, but it would be extremely expensive. If this is implemented using an inexpensive dynamic RAM, the writing speed will be limited by the cycle time of the dynamic RAM. In particular, when the display waveform changes in a direction perpendicular to the readout direction, it is impossible to speed up the cycle time beyond that.

The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to inexpensively realize a waveform display device that can perform high-speed writing from a dot generation circuit to an image memory in a waveform display device such as a measuring instrument. purpose.

(Means for Solving the Problems) The present invention relates to a waveform display device that displays waveforms using an image memory, and its feature is that parallel bits at the same address of a plurality of memory chips are Input the image memory allocated so as to be arranged adjacently to form a memory cell, and the upper and lower Y-axis start point data, and simultaneously address the plurality of memory chips of the memory cell corresponding to the count value. and a chip selection circuit that selects each memory chip in accordance with the lower bits of the Y-axis start point data or the lower bits of the Y-axis end point data.

(Function) Since the Y16 counter collectively generates dots from a plurality of memory chips, high-speed operation is possible.

(Example) The present invention will be explained in detail below using the drawings.

FIG. 2 is a block diagram showing an embodiment of a waveform display device according to the present invention. 100 is a CPU that outputs commands to the dot generation circuit 200 for controlling the entire device and displaying waveforms; 200 is a dot that inputs the coordinate values of the start point and stop point from the CPU 100 and generates dots at high speed. A generation circuit 3.00 is a CRT controller that generates a read address for the image memory 500 for generating and displaying vertical and horizontal retrace signals for the CRT; 400 is a CR;
An arbiter 500 arbitrates read accesses from the T controller 300 and write accesses from the dot generation circuit 200, and an image memory 500 has a memory that corresponds one-to-one to the display dots of the CRT, and is read and accessed by the output of the arbiter 400. , 600 is a parallel/serial converter that converts the parallel output of the image memory 500 into a series to generate a video signal for the CRT.

FIG. 1 is a block diagram showing the configuration of dot generation circuit 200 in FIG. 2. In FIG. When displaying waveforms on measuring instruments, in the case of time-domain waveforms or frequency-domain waveforms, a Y-axis value is generally given for each monotonically increasing point on the X-axis. The dot generation circuit is configured to perform vertical interpolation at high speed when the dots are given one after another.

21.22 is a Y-axis end point register which inputs and stores the upper 8 bits and lower 2 bits of the Y-axis end point coordinate data from cptrtoo, respectively, and 23 inputs the upper 8 bits of Y-axis start point coordinate data from the CPU 100 to a comparator 28. Yllllup/down counter that counts the dot clock CLK in the direction (up or down) determined by the output of 29, Yfi[I start point register 24 that inputs the lower 2 bits of Y-axis start point coordinate data from the CPU 100, and 25 an X from the CPU 100. Input the axis start point coordinate data and use comparator 2.
26 is a command register that is set by a dot generation command from the CPU 100 and reset by a match output from the comparator 28, and 27 is the output of this command register 26. 28 is a comparator for the upper bits that compares the values of the Y-axis end point register 21 and the Y-axis up/down counter 23, and two are the Y-axis end point registers 22. This is a comparator for lower bits that compares the value of the Y-axis start point register 24 with the value of the Y-axis start point register 24 and outputs the result to the comparator 28. 70 is chip j2! In the selection circuit, 30.31 is a decoder that decodes the 2-bit output of the register 22.24 into a 4-bit output, and 32.33
is a two-manpower system that switches the output from the decoders 30 and 31 in response to the p/d o w n output from the comparator 28.
Output type selectors 34 and 35 are composed of a combination of OR circuits, etc., and input the selected outputs of the selectors 32 and 33 to set specific bits to "1". Lower and upper dot generation circuits; 36 are lower and upper dot generation circuits. Dot generation circuit 34.
4-bit output AND circuit corresponding to each of the 35 bits,
Reference numeral 37 is an XY address conversion circuit that obtains the values of the memory address and bit address of the corresponding dot from the values of the Y-axis counter 23 and the X-axis counter 25.

The operation of the dot generating circuit 200 configured as described above will now be described.

FIG. 3 shows the configuration of image memory 500. here 64
1024X1 using four kX4-bit memory chips
The configuration of the 0 image memory that makes up the 024 dot image memory is that the 4 x 4 bit memory cells 51 are 256 x 25.
It is arranged with a resolution of 6. As shown in FIG. 4, each memory cell 51 is constructed by arranging four parallel bits of the same address in four different memory chips adjacently in the Y direction of the image memory. In other words, 4 parallel to the X-axis direction
A memory unit cl consisting of three bits 0 to 3.

Memory unit cl consisting of bits 4-7, bits 8-11
A memory unit consisting of c2. Memory unit C3 consisting of bits 12-15 corresponds to memory chips 0, 1.2.3, respectively. Here, when generating dots in the Y direction,
When writing is performed one dot at a time, the writing speed is limited by the RAM access time. On the other hand, when writing four dots at a time, a high-speed counter and a comparator are required when the dots are simply generated by a counter and a comparator. Therefore, in this embodiment, dots are generated for each memory unit (4 bits) as shown below, and dots are generated only at the start and end cycles by a special method described later.

The coordinate data of the Y-axis end point Y1 is input from the CPU 190 to the Y-axis end point register 21.22, and the Y-axis UP/DO
w n counter 23 and Y-axis start point register 24
The coordinate data of the axis starting point yo is input, and the X-axis counter 23
The X-axis starting point coordinate data is input to command register 2.
When 6 is set by the dot generation command, the gate 27 is opened by the output of the command register 26 and the taro clock C is set.
A Y-axis up/down counter 23 counts the LK. The direction of up and down is controlled by the output of comparator 28, and the value of register 21 is
If the value is larger than the value, an up count is performed, and in the opposite case, a 60wn count is performed.The output of the counter 23 at this time indicates the memory cell to which the starting point belongs, and then the Y of the memory cell to which the dots generated up to the end point belong. When the counter 23, which indicates the address, reaches the end point value of the Y register 21,
Due to the coincidence output of the comparator 28, the X-axis counter 25 increases by 1 (counts up), the command register 26 is reset, and the counter 23 stops counting. The next Y-axis end point coordinate data corresponds to the new X-axis coordinate value by CPU100.
is applied to the registers 21 and 22, the counter 23
Using the value held in (previous Y-axis end point coordinate data) as new start point data, dots are generated up to the end point, and the same operation as last time is repeated. When the values of the 6 counters 23 written to the image memory 500 via the arbiter 400 in accordance with the memory address and bit address output from the XY address conversion circuit 37 are at the start point and the end point, the values of the registers 24 are respectively written as follows. Chip iH using a value of .22
Generates a selection signal. When the value of the counter 23 is initially at the starting point, the 2-bit output of the register 24 is converted by the decoder 31 into a 4-bit output with the bit position of the starting point being "1". When the comparator 28 is outputting the 1j p signal, the output of the decoder 31 is sent to the upper dot generation circuit 35 via the selector circuit 33, and all bits higher than the starting point bit position are set to "1". , the comparator 28 is d o
When the wn signal is being output, the output of the decoder 31 is sent to the lower dot generation circuit 34 via the selector circuit 32, and the counter 23 outputs a signal that sets all bits lower than the starting bit position to "1". When the value is at the end point, the 2-bit output of register 22 is sent to decoder 3.
It is converted into a 4-bit output with the end bit position set to "1" at o, and then the up/dow of the comparator 28
Corresponding to the n output, dot generation is performed in an operation opposite to that for the starting point. The output from the dot generation circuits 34 and 35 is sent to the image memory 500 via the arbiter 400 as a chip selection output via the gate circuit 36, and by selecting a chip, a dot at the start point or end point cycle is generated in the Y-axis direction. let In the cycle between the start point and the end point, all bits, that is, 4 bits at a time, are collectively set to "1", and the lower 2 bits of the X-axis counter 25 determine which column of 4.times.4 bits to write. FIG. 5 shows an example in which dots are generated in this way, starting from the starting point 61 in the starting point cycle 63, passing through the intermediate cycle 64, and ending in the ending point cycle 65.
The pattern in which dots are generated until reaching the end point 62 in is shown. Figure 6 shows the X-
This is an explanatory diagram showing a method of converting a Y address to a memory address. The upper 8 bits a1 of the Y-axis counter 23 and the upper 8 bits b1 of the X-axis counter 25 are used as an address to specify a memory cell, and the Y-axis The lower two bits a2 of register 22 or 24 are used for chip selection, and the lower two bits b2 of X-axis counter 25 are used for bit addressing in the X-axis direction. In this way, the counter can be used at 1/4 of the normal speed, and compared to the method of generating dots one by one and writing them all at once, the circuit that overwrites the dots and the circuit that detects the change point of the address are required. becomes unnecessary.

According to a waveform display device with such a configuration, adjacent bits are assigned to different chips, and dot generation is performed using multiple chips at once, so the generation circuit can be low-speed, and the memory chip can also be low-speed. Things can be used. That is, C
High-speed dot generation and writing are possible with a low-speed circuit such as MO3.

In addition, the X-axis counter is counted up each time the end point in the Y direction is reached, so after first loading the start points of the X and Y axes into each counter, you can simply specify the end points of the Y axis one after another. can interpolate the dots of Therefore, C.P.
The operation at U is very simple since there is no need to calculate the slope, and high-speed operation is possible with a dot generating circuit having a simple configuration.

In the above embodiment, the Y-axis counter is up, /
' Although a down counter is used, only an up counter or a down counter can also be used. In this case, the CPU should make an up or down judgment, and the starting point and ending point values should be swapped and set according to the judgment result.This will increase the CPU load somewhat, but it will reduce the hardware burden. Clothing becomes easier.

Furthermore, in the above embodiments, arbitrary values can be selected for the capacity of the image memory, the number of bits of the counter and register, etc.

(Effects of the Invention) As described above, according to the present invention, a waveform display device for a measuring instrument or the like that can perform high-speed writing from a dot generation circuit to an image memory can be realized at low cost.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing a dot generation circuit portion of an embodiment of the waveform display device according to the present invention, FIG. 2 is a configuration block diagram showing an embodiment of the waveform display device according to the present invention, and FIG. 3 5 is an explanatory diagram for explaining the operation of the apparatus shown in FIG. 1, and FIG. 6 is an explanatory diagram showing a method of specifying a memory address in the apparatus shown in FIG. 200... Dot generation circuit, 23... Y-axis counter, 25... X-axis counter, 28.29... Comparator,
500... Image memory, 51... Memory cell, 70
...Chip selection circuit, CLK...Clock, c1~
c4...Parallel bit. 3rd (¥1 5ii; S) To the slope 1st 4th figure 6th figure

Claims (1)

[Claims] In a waveform display device that displays waveforms using an image memory, the image memory is allocated so that parallel bits of the same address of multiple memory chips are arranged adjacently in the Y direction to constitute a memory cell, and the Y-axis starting point. a Y-axis counter that inputs upper bits of data and simultaneously addresses the plurality of memory chips of the corresponding memory cell;
A waveform display device comprising: a chip selection circuit that selects each of the memory chips in accordance with a lower bit of Y-axis start point data or a lower bit of Y-axis end point data.