SU1697074A1 - Information crt display unit - Google Patents

Abstract

The invention relates to automation and computing and can be used to display graphical information under the control of a microprocessor in a radio measuring technique, for example, in digital oscilloscopes. The purpose of the invention is to increase the speed of the device, which is achieved by introducing a counter, a data multiplexer and corresponding functional connections. The invention allows bit-by-bit recording of information in a regeneration memory block with an automatic increase of the write address, thereby reducing the time required to form or erase the signal under investigation on the ECT CRT. 2 Il.

Description

The invention relates to automation and computing and can be used to display graphical information under the control of a microprocessor in a radio measuring technique, for example, in digital oscilloscopes.

The purpose of the invention is to increase the speed of the device.

Figure 1 and 2 shows the structural diagram of the device.

The device contains a control unit 1, a synchronization unit 2, a video amplifier 3, a frame and line generator 4, a cathode-ray tube (CRT) 5, input register 6, output register 7, counter 8, address register 9, address multiplexer 10, memory , shift register 12, data multiplexer 13. Control unit 1 includes microprocessor 14, module 15

input and storage of information, block 16 of permanent memory and block 17 of firmware control, containing address selector 18, shaper 19 of signals, register 20, block 21 of permanent memory, buffer register 22, control register 23. The synchronization unit includes a generator of 24 clock pulses, a counter of 25 points, a counter of 26 lines, a Shaper of 27 frame and line sync pulses. Position 28 indicates a data bus connected to the input-output of this control unit 1. The device works as follows. The microprogram control unit 17 of the control unit 1, which is a signal distributor, continuously generates control signals defining the operation cycle of the memory block 11, which consists of two intervals: constantly occurring during the horizontal line and forward interval sweep

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reading the displayed information (there is no reading interval during the reverse run) and the time interval for the microprocessor to modify the information in block 11. In this 5 mode, the microprocessor loads the control word into the register 23, the control that determines the device operation mode, 3 The readout interval for the displayed information on the 5th: 2 synchronization generates (O the address of the next byte of information, which in the next cycle is about (reflected on the screen of the ELT5. Read from the block. T1 memory, enter information into the pei source 12 sd) It is converted into a video signal sequence in 15. By the time when the information in register 12 is sequentially converted into video signals by the synchronization unit 2, the next data byte from block 11 is prepared together with the control module 17, and the thus, a continuous sequence of video signals during the forward course of the sweeps. At the input of the re-25 non-scraper 4 frame and line scan, the synchronizing signals are received by horror and line current.

The time of the image byte of the information about the sequence of video signals 30 is much longer than the time required to prepare the next byte, and therefore the timing of the display cycle time was allotted to serve the microprocessor calls to Memory 11. In this 35, the following modes are possible:

- write data byte to memory block 11; - reading data byte from memory block 11;

- setting of any bit, located in block 11, which allows to display one 40 element on the screen of the SLT;

- setting the specified bit with an increase in the value of the X coordinate in the address of the memory block 11. .

- clearing any bit found in memory 45 in block 11 by erasing one display element;

- cleaning of the specified bit with increasing value of the X coordinate in the block address

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In addition to these operations, the microprocessor processes the information contained in the module 15 for entering and storing information according to the operation algorithms of the device, represented and designed as software, located in the fixed memory block 16. It is assumed that the presented device for display is used a. moduli system, for example, pscyl-.

In the field of graphics, where the microprocessor, along with the task of supporting the operation of the display device, performs the same actions with respect to other modules, coordinates their work, and if necessary, performs a certain sequence of actions during startup, collection, processing of information, i.e. the microprocessor is the central control element of the multi-module system, and the actions performed on the display device are only a Fragment in the overall system operation algorithm.

To write a byte of information into memory block 11, the microprocessor performs the following operations:

- writes the address of the byte in counter 8 (coordinates of the X byte and register 9 via the bus 28 data;

-signs bytes of data from the register 6 input through the bus 28 data;

- sets the byte write operation code to control register 23.

After receiving the code of the specified operation, the firmware control block 17 in the current or next display cycle generates control signals that record the data byte located in the input register 6, the contents of which are fed to the inputs of the memory blocks 11 through the multiplexer 13. The address of the cell to which the byte is written is determined by the contents of register 9 and the upper bits of the contents of counter 8. Data byte recording occurs simultaneously in all bits of the cell in memory block 11 and occurs in the time interval intended for servicing microprocessor calls. At the end of the indicated interval, the control register 23 is reset; The time it takes to write a data byte is, as before, equal to half the time of one display cycle.

To read the byte from memory block 11, the following actions are performed by software:

- write byte address to counter 8 and register 9 ;,

- the byte read code into register 23 is loaded;

The read byte is read from the output register 7 to the microprocessor via the data bus 23.

After receiving the byte read operation code, the firmware control block 17 in the current display cycle generates -. control signals which

provide read data byte from block 11 memory write it to the register 7 output. At the end of the operations, as in the case of other operations, the register 23 returns to the initial state. Byte read or write operations are used for online access to the data byte located in memory block 11, for example, when diagnosing memory block 11.

The following steps are taken to set a bit to a micro processor:

- write the address of the bit defined by the X and Y coordinates of the display element,

in the counter (X) 8 and register (Y) 9;

-installation in register 23 of the operation code of the bit installation.

After receiving the specified code, the firmware control block 17 in the current cycle generates control signals that write the data bits to the memory block 11. The bit number in a byte is determined by the lower bits of the X coordinate РХ2 ... РХО. In this case, the data inputs of the memory unit 11 are supplied with a single data state via the second input of the data multiplexer 13, and the microprogram control unit 17 opMnpyef receives the active write / read signal for only one bit, determined by the least significant bits of the X coordinate of the PHO .. .PX2. The cell address is determined by the contents of the register Y / 9 and the higher bits of the counter (X) 8. This operation is performed in the time interval intended for servicing the microprocessor calls, after which the initial state is set to 23.

For clearing a certain bit in a byte, the microprocessor performs similar operations as for setting a bit to one. The only difference is that control register 23 loads the clear operation code that determines the zero state of the data transmitted through the second input of the data multiplexer 13 to the inputs of the memory block 11.

To clear or set the indicated bit with an increase in the value of the coordinate X, it performs the following preparatory steps:

- loads the value of the Y-coordinate of the element in the register (Y) 9:

-signs the code of the operation of cleaning or setting the bit with the increase of the coordinate (X) in the register 23.

Before the specified actions are loaded into the counter

(X} is zero code. Thus, the value of the X coordinate is set to the initial zero state. Further, when writing the value of the Y-coordinate of the element in the register (Y) 9 (the X-coordinate value is already determined by the value of the sensor (X) 8) and specifying the opcode code, the bit is cleared or set, at the end of these operations, the counter value (X) 8 is increased by one. Having performed a certain number of ps3 the sequence of actions listed above, quickly form or erase the signal under study on the SLT screen. account possible and setting the bit to zero or a unit consisting of a display element with increasing values of the coordinates X, the microprocessor decreases the time to complete forming or erasing operations of the signal on the CRT screen.

Claims (1)

An apparatus for displaying information on a cathode-ray tube (CRT) screen comprising a control unit, an address register, an address multiplexer, a memory unit, a shift register, an input register, an output register, a synchronization unit, a video amplifier, a frame and line generator, the first and second outputs of which are connected to the deflection system of a CRT, whose modulator is connected to the output of the video amplifier, whose information input is connected to the output of the shift register, whose information input is connected to the output the memory unit connected to the information input of the output register, the output of which is connected to the input-output of the control unit, connected to the information inputs of the register and input and the address register, the output of which is connected to the first information input of the address multiplexer, the output of which is connected to the address input of the memory unit, the first and second control inputs and the control inputs of the group of which are connected respectively to the first and second outputs and outputs of the first group of the control unit, the third and fourth outputs of which first connected to the write and read control inputs of the output register, the fifth output of the control unit is connected to the control input of the shift register, the clock input of which is connected to the first output of the synchronization unit connected to the clock input of the control unit, the address inputs of which are connected to the second output of the block synchronization, the third output of which is connected to the second information input of the address multiplexer, the control input of which is connected to the sixth output of the control unit, the seventh and eighth in the strokes of which are connected respectively to the control inputs of the address register and the input register, the fourth output of the synchronization unit is connected to the generator input of the horizontal unscrambler, the information input of the control unit is an information input of the device, in order to improve speed contains a counter, a data multiplexer, the output of which is connected by the information input of the memory block, the output of the input register 0 connected to the first information input of the data multiplexer, the second information input of which is connected to the outputs of the second group of the control unit, the ninth output of which is connected to the control input of the data multiplexer, the output of the counter is connected to the first information input of the address multiplexer and the control input of the control unit, the tenth and eleventh outputs of which are connected respectively to the control and clock inputs of the counter, the information input of which is connected to the input-output of the control unit. Tire abres and control Bus data shch ... shd Data bus 2 / - PXU ... PX2 R w RCS ... RC7  AO ... A13 eleven CЈL №№Q ... D80 ... DV7 eight ZRS TI SKR.SSR mt tt s / g / at Them. 2