SU1571646A1 - Device for presentation of information - Google Patents

Abstract

The invention relates to automation and computing and can be used in measurement and control systems. The purpose of the invention is to expand the field of application by enabling simultaneous display of alphanumeric, graphical and histogram information. The goal is achieved by the introduction of an information processing unit 2, a second memory unit 4, registers 13, a driver 6, a distributor 12 pulses, and a counter 7 of a write address. The process of displaying information is performed independently of the process of converting the signal under study, which allows displaying fast processes and signals. 4 il.

Description

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The invention relates to automation and computing and can be used to display information in test and measurement systems.

The purpose of the invention is to expand the field of application of the device by providing simultaneous display of graphical, histogram, and alphanumeric information.

Fig, 1 shows a functional diagram of the proposed device; figure 2 - plot of the signals at the input and outputs of the pulse shaper.

The device contains an analog-to-digital converter (ADC) 1, information processing block 2 (DRC), synchronization block 3, second 4 and first 5 memory blocks (RAM), pulse generator 6, write address counter 7, controlled clock generator 8 , switch 9 codes, column address counter 10, read address counter 3, pulse distributor 12, register 13, matrix gas discharge indicator (IMG) 14,

The operation of the device is carried out in accordance with the program set by the FIGHT.

The operation of the device can be divided into two main processes occurring in parallel and independently from each other: the measurement process and the display process. The measurement process is implemented in accordance with the program in two modes of operation of the device: the conversion of the signal under investigation into digital form and the transfer of information about the signal to the BOI.

Signal conversion mode.

An analog signal is received i input ADC i, the control bus from the BOI 2 to the input of the synchronization unit 3 receives a pulse to start the operation of converting an analog signal into digital form. The conversion operation is performed in several clocks upon the arrival of the synchronization pulse synchronization unit 3 to the sikhrovkhod. The number of conversion cycles is equal to the number of samples of the analog signal and is set by the code on the control bus from BOI 2. During one clock cycle, the instantaneous value of the analog signal is converted into a digital code. The conversion is performed by the ADC upon receipt of its control pulse input. Start

ADC from the second output of block 3 synchronization. Then, synchronization unit 3 generates the RAM record and Address signals, respectively, coming from the first and third outputs of block 3 to the control and address inputs of the second RAM 5, which records the digital code from the ADC 1 output

in the appropriate memory cell.

At the end of the recording process, the next conversion cycle begins. After the end of the last conversion cycle, the synchronization unit 3

c generates a signal of the Conversion End, which arrives at the sync-input to the BOI 2, and sets the third output to zero address.

The mode of data transmission in the fights.

Q Data is transferred from the second RAM 5 to the BOI 2 after the synchronized input enters the BOI of the signal. Conversion end from the fourth output of the synchronization unit 3. BOI 2

5 sequentially reads codes from each memory location of RAM 5, starting with zero. After reading the information from any cell to the synchronization unit 3 via the control bus

a pulse is received from the BOI, increasing by one the address code at the third output of block 3. The output from RAM 5 receives the code from the next memory location, in which way the data from the cells of the second RAM 5 are successively transmitted to BOI 2,

BWIs process codes

carrying information about the form and parameters of the signal under study. In particular, FDT performs operations of amplitude and time scaling, averaging, comparison with maximum permissible values, etc. BOI generates reference images in the form of codes

Carry information about the studied g J signal, in accordance with the program

It has graphic, histogram and alphanumeric information on the IMG screen in a form that is convenient and easy to read. BOI allows ® to also get a moving image iT.e, animation.

3

The process of displaying information is also implemented in accordance with two modes of operation of the device and includes recording information in RAM 4 and indicating information recorded in RAM 4 on the screen of IMG 4.

51

Display mode.

The indication of the information recorded in the second RAM 4 is carried out in the absence of a pulse. The read inhibit at the third output of the driver 6 is prevented. The IMG 14 operates in the image scan mode by columns. The columns are switched sequentially by the address / column counter 10, the input of which receives pulses from the output of the generator 8.

Consider the processes that occur when selecting a single column. Suppose that at the output of counter 10 there is a code corresponding to the address of any column of the IMG. From the output of the generator 8 to the input of the counter 10 receives a pulse, increasing its output k to one. Then the information about the column from RAM 4 is entered into the register 13. Information is entered into the register in k cycles:

k -5- k n

where m is the number of elements in the column (number of rows) of the IMG; n is the number of digits of the RAM cell 4.

The register -13 consists of k n-bit registers, the information inputs of which are connected in parallel, and the control inputs are connected to the first k outputs of the distributor 12.

A sequence of pulses with a frequency much higher than the frequency of the sweep, in columns comes from the output of the generator 8 to the input of counter 11, from the output of which through the switch 9 the code of the address of the memory cell goes to the address input of RAM 4. The low bits from the output of counter 11. arrive at the input of the distributor 12, which is gated by the leading edge of the pulses from the output of the generator 8. When a strobe pulse arrives at one of the outputs of the distributor 12 corresponding to the code of the lower bits of the counter 11, a pulse is generated that arrives at the control th input of the corresponding register (see register 13). With this pulse, the code from the output of the RAM 4 is entered into the register. The leading edge of the pulse from the second output of the generator 8 triggers the counter 11, its output code is increased by one. Thus it is consistently carried out66

With k clocks entering information into register 13. At the end of the last clock cycle, at the (k + 1) output of distributor 12, a pulse is generated that arrives at the input of the controlled generator 8 and for the time the column lights up, prohibiting the generation of pulses at its second output. Exit code

Register 13 enters the horizontal tires IMG. The column flash time is significantly longer than the time required to enter information from RAM 4 into register 13 and is determined by the period

sweep by columns. After the end of the column flashing from the second output of the generator 8, a pulse arrives at the input of the counter 10 of the column address and its output code is increased by one. Indications

Information in the remaining columns of an IMG is made similarly.

After the last column is displayed, the counter 10 generates a pulse that collects

counter 11 of the read address to the zero state. Next, the process of reproducing a new frame begins.

The mode of recording information in RAM 4.

Information is recorded in RAM 4 as follows. A reset pulse is received from the first control output to the record address counter 7, which sets the counter 7 to the zero state. Data is written to RAM 4 in several cycles. Consider one beat. At the information output

installs binary data,. arriving at the input of the RAM 4, and accompanies them with a strobe pulse (Fig. 2-1), coming through the control bus to the input of the driver 6, which has three outputs. The signal plots at the input and output of the imaging unit 6 are shown in FIG. 2. At the third output of the imager, a pulse 4 is generated.

The input of the controlled generator is 8 pulses. In this case, the first and second outputs of the generator 8 are set to the zero state. The processes of reading data from RAM 4 and sweep by

columns in the IMG are interrupted. At the first output of the imager 6 a pulse is generated. Control of the switch arrives at the control input of the switch and switches it so that

The address input of the RAM 4 receives the code from the output of the counter 7 of the write address. The third output of the imaging unit 6 generates a pulse (Fig. 2-4) arriving at the control input of the RAM 4 and recording data into the corresponding cell of the RAM 4 from the information output of the BOI . On the trailing edge of the write pulse, the counter 7 of the write address is triggered and its output code is increased by one. At the end of the pulses, Switch Control and Read Ban, the switch 9 returns to its initial state. The reading of data from the RAM 4 and, consequently, the indications on the screen of the IMG 14 continues.

The proposed device allows simultaneous display of graphical histogram and character information. The device allows you to simultaneously display information about the form and parameters of the signal under study, as well as about the compliance of these parameters with the requirements of tolerances. At the same time, the specified information is located on the screen of the IMG in a consistent and convenient form. High accuracy of the representation of information about the parameters of the signal under study is achieved by displaying the values of the parameters in a digital (sign) form. The device has a high speed which is mainly determined by the speed of the ADC and the number of measurement operations, and, therefore, allows you to monitor fast processes and signals. This is a result of the fact that the measurement process is carried out independently of the display process, and, therefore, restrictions on the ratio of the periods of the signal under investigation and the indicator unwind are removed. Scaling by amplitude (rationing) and by time provides a wide dynamic range of measured signals.

invention formula

A device for displaying information, comprising an analog-to-digital converter, an information input, the input of which is an information input of the device, and an output connected to the information input of the first memory block, a control input for

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read-write is connected to the first output of the synchronization unit, a clock pulse generator, the first output of which is connected to the counting input of a column counter, the output of which is connected to the address input of the display unit, a switch, the first information input of which is connected to the output of the readout address counter, that, in order to expand the scope of application by providing simultaneous display of alphanumeric graphic and histogram information, a second memory block, registers, pulse puller, write address counter, pulse distributor, information processing unit, information input of which is connected to the address output of the information processing unit, and the control input is the device's synchronous input, the second output of the synchronization unit is connected to the analog-digital converter control output, and the third and fourth outputs, respectively, to the address input of the first memory block and to the synchronous input of the information processing unit; the first and second control outputs are connected respectively to the input pulse generator and the setup input of the write address counter, the clock input of which is connected to the first output of the pulse generator and to the control input of the second memory block, whose information input is connected to the information output of the information processing unit, and the address input to the switch output, control input which is connected to the second output of the pulse generator, the second information input is connected to the output of the write address counter, and the first information input is connected to the output of the read address counter and with the information input of the pulse distributor, the pulse input of the pulse distributor in is connected to the clock input of the read address counter and the second output of the clock generator, the first and second control inputs of which are connected respectively to the third output of the pulse generator and to the output of the pulse distributor, group outputs which are connected to the control inputs of the registers, the information inputs of which are connected to the output of the second memory block, the outputs of the registers are connected to the information

FIG. 2

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the input of the display unit, the control output of the column address counter is connected to the installation input of the address counter

readout.

Claims (1)

Claim A device for displaying information containing an analog-to-digital converter, the information input of which is the information input of the device, and the output is connected to the information input of the first memory block, the write-read control input of which is connected to the first output of the synchronization block, a clock generator, the first output which is connected to the counting input of the column counter, the output of which is connected to the address input of the display unit, a switch, the first information input of which is connected to the output read address counter, characterized in that, in order to expand the scope by providing simultaneous display of alphanumeric graphical and histogram information, a second memory block, registers, pulse shaper, write address counter, pulse distributor, information processing unit, information input are introduced into it which is connected to the address output of the information processing unit, and the control input is the device sync input, the second output of the synchronization unit is connected to the control analog-to-digital converter, and the third and fourth outputs, respectively, to the address input of the first memory block and to the sync input of the information processing unit. · information, the first and second control outputs are connected respectively to the input of the pulse shaper and the setting input of the recording address counter, clock input which is connected to the first output of the pulse shaper and to the control input of the second memory block, the information input of which is connected to the information output of the information processing unit, and the address input is the output of the switch, the control input of which is connected to the second output of the pulse shaper, the second information input is connected to the output of the counter of the write address, and the first information input is connected to the output of the counter of the read address and to the information input of the pulse distributor, · the gate input of the pulse distributor is connected to the clock input of the counter read addresses and with the second output of the clock generator, the first and second control inputs of which are connected respectively to the third output of the driver pulses and to the output of the pulse distributor, the group outputs of which are connected to the control inputs of the registers, the information inputs of which are connected to the output of the second memory block, the outputs of the registers are connected to the information input of the display unit, the control output of the column address counter is connected to the setup input of the read address counter . FIG. Z