JPH0693180B2 - Bitmap Display Device - Google Patents

Description

The present invention relates to an interlaced high-resolution bitmap suitable for use in a data processing system such as an image editing device that processes digital image data in pixel units. The present invention relates to an improvement in a display device, and particularly, to decrease the display quality of a screen by extending the period during which data can be continuously drawn in a large-capacity bitmap display memory that is required to process data in bit units. Without
The present invention relates to a bitmap display device capable of quickly processing even complicated drawing in a short time.

[Conventional technology]

2. Description of the Related Art Conventionally, in an image editing apparatus or the like that processes digital image data in units of pixels, a very high resolution bitmap display is used so that precise image editing can be performed.

However, in the case of a high-resolution bitmap display, for example, in order to display the A4 full size at a resolution of about 6 dots / mm, the screen dot size is 1,500 ×.
Since it is about 2,000 (dots), as a buffer memory for display, that is, display memory,
It requires a large amount of memory such as 300 to 400 Kbytes.

Therefore, in the conventional bitmap memory write control method, in the flashless mode, the rewritable period (drawing period) of the display memory is limited to the period excluding the display period on the CRT display and is continuous. The period that can be drawn is extremely short. Therefore, the time required to rewrite the data for one screen becomes extremely long, and the operation efficiency decreases.

On the other hand, if you use the flash mode method that pauses the display and draws, you can set the length of continuous drawing to any length. Due to the existence of the stop period, there is an inconvenience that the display quality deteriorates and the screen becomes very difficult to see.

[Problems to be Solved by the Invention]

The bitmap display device of the present invention solves such inconvenience in the conventional write control method of the bitmap memory and enables continuous drawing in the display memory without disturbing the display of the CRT display. The purpose of this is to realize a high-speed drawing function for the bitmap memory.

[Means for Solving the Problems]

According to the present invention, firstly, an interlaced CRT display, a bitmap display memory having a storage capacity for one screen of the display and divided into an odd line area and an even line area, and a display address. A first controller for controlling, a second controller for controlling a drawing address and a writing control to the display memory, and a multiplexer for selecting an address signal output from the first and second controllers. In a bitmap display device having a data processing system controlled by a central processing unit, the display memory divided into the odd line area and the even line area is provided with an address input for each area. , The multiplexer includes each of the display memories A first controller that controls the display address and a second controller that outputs a control signal that enables writing of data to the line area. The output period of the control signal that enables writing of data to each line area of the divided display memory output from the second controller is longer than the scanning period of one screen of the interlaced CRT display. The odd-numbered line area and the even-numbered line area are set by controlling the writing data to be continuously written to one area during that period and reading the display data from only the other area and displaying it on the CRT display. The writing operation to both areas is performed independently.

Secondly, an interlaced CRT display, a bitmap display memory having a storage capacity for one screen of the display and divided into an odd line area and an even line area, and controlling a display address. 1 controller, a second controller for controlling a drawing address and a writing control to the display memory, and a multiplexer for selecting an address signal output from the first and second controllers, In a bitmap display device connected to a data processing system controlled by a processing device, the display memory divided into the odd line area and the even line area includes an address input for each area, and the multiplexer is , Inputting each address of the display memory A second controller that outputs a control signal that enables writing of data to the line area and a first controller that controls the display address; The output period of the control signal that enables writing of data to each line area of the divided display memory output from the controller is arbitrarily set, during which drawing data is continuously written to one area. While controlling so that the display data is read from only the other area and displayed on the CRT display, and during the scanning period of the line of the one area, by stopping the display on the CRT display, Writing operations to both the odd line area and the even line area can be performed independently.

[Basic operation of interlaced display]

Here, with respect to the bitmap display device of the present invention, a configuration and a writing operation relating to display control of the interlaced display will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of a bitmap display device of the present invention. In the drawing, 1 is a CRT display, 2 is a P / S (parallel / serial) converter, 3 is a display memory, 3A is a memory area for odd lines, 3B is a memory area for even lines, and 4A.
Is the first multiplexer, 4B is the second multiplexer,
Reference numeral 5 is a display address controller, 6 is a drawing controller, and ▲ ▼ and ▲ ▼ are write control signals.

The function of each part is as follows.

The CRT display 1 is an interlaced (so-called interlaced scanning) type bitmap display.

The P / S converter 2 converts the data output in parallel from the display memory 3 into serial data, and the CRT
Send to display 1.

The display memory 3 has a storage capacity for one screen of the CRT display 1 and is an odd line (ODD line).
Memory area 3A and an even-numbered line (EVEN line) memory area 3B. Each of these areas 3A, 3B is
Each has independent address input 1 and address input 2, and the outputs of the first multiplexer 4A and the second multiplexer 4B are connected to each other. Further, the data input is commonly given to both line areas from a data processing system (not shown).

In the display memory 3, in the memory area 3A for odd-numbered lines, when the address input 1 is active and the write control signal ▲ ▼ is inactive, the data at the given address is transferred from the data output 1 to the P / S converter. Input to 2.

In addition, the address input 1 is active and the write control signal ▲
When ▼ is also active, the data from the data input is written to the given address. Address input 1
When is inactive, the read / write operation of this memory area 3A cannot be performed.

The same operation is performed in the memory area 3B for even lines by the address input 2 and the write control signal ▲ ▼.

With this configuration, the display memory 3
The two memory areas 3A and 3B can independently perform the above operation. Therefore, the data output 1 and the data output 2 are simultaneously output to the respective memory areas 3A and 3B.
It is possible that the data from will be output.

Therefore, in the bitmap display device of the present invention, the later-described drawing controller 6 causes the first and second multiplexers 4A and 4B and the write control signals ▲ ▼ and ▲.
By controlling ▼, two memory areas 3
The data from A and 3B are not output at the same time.

The first multiplexer 4A and the second multiplexer 4B select either one of the drawing address signal output from the drawing controller 6 and the display address signal output from the display address controller 5 to display it. Input to address input 1 and address input 2 of memory 3.

The display address controller 5 is the display memory 3
The display address signal of is output.

The drawing controller 6 outputs the drawing address signal of the display memory 3 and also the first multiplexer.
The timings of the outputs of the 4A and the second multiplexer 4B are controlled so that they are not generated at the same time, and the write control signals ▲ ▼ and ▲ ▼ are similarly generated so that both control signals are not generated at the same time. To control.

Next, the drawing operation of the bitmap display device of the present invention shown in FIG. 1 will be described.

First, in a basic operation, in synchronization with a period that is a non-scanning line of the interlaced CRT display 1, that is, a non-display period, the drawing controller 6 causes the memory 3 to operate.
By outputting the control signals ▲ ▼ and ▲ ▼ that enable the writing of data to the memory areas 3A and 3B of 1 to the one area, the drawing data is controlled to be continuously written to the one area. The display data is read from the other area and displayed on the CRT display 1.

FIG. 2 is a time chart for explaining the operation at the time of drawing the data to be displayed on the interlaced CRT display 1 in the bitmap display device of FIG.

In the case of FIG. 2, from the drawing controller 6, in synchronization with the non-scan line of the CRT display 1,
Since the data write control signals ▲ ▼ and ▲ ▼ for the memory areas 3A and 3B of the memory 3 are output to one area, the horizontal / vertical synchronization signals of the CRT display 1 are used to control the output timing. can do.

On the CRT display 1, data periodically read from the display memory 3 is displayed. This read cycle is a constant value determined by the scanning speed of the CRT display 1.

Since the CRT display 1 is of the interlace system, for example, as shown in FIG. 2, if scanning scanning is started from the odd line 2, the memory area 3A for the odd line of the display memory 3 is continuously and The data of all lines is read out and sent to the CRT display 1, and then from the memory area 3B for even lines, continuously,
The data of all lines are read and sent to the CRT display 1. By such display reading, one display cycle is completed.

Then, when the screen is not rewritten and the access to the display memory 3 is only reading for displaying on the CRT display 1, such one cycle is sequentially repeated.

As described above, data reading from the display memory 3 for displaying on the CRT display 1 is continuously performed from the odd line memory area 3A or the even line memory area 3B.

Therefore, for example, while the data for reading is being read from the memory area 3A for odd lines, the drawing controller 6 can write drawing data to the memory area 3B for other even lines.

That is, as shown in FIG. 2, the display address signal output from the display access controller 5 passes through the first multiplexer 4A and the odd line memory area 3A.
Address input 1 of. At the same time, by deactivating the write control signal ▲ ▼, the data in the memory area 3A for odd lines is output to the data output 1,
Displayed on CRT display 1.

During this period, the drawing controller 6 outputs a drawing address signal, supplies it to the address input 2 of the memory area 3B for even lines through the second multiplexer 4B, and activates the write control signal ▲ ▼. , Drawing data given to data input, memory area for even lines
It can be written to 3B (even line drawing possible period).

Similarly, while the data for display is being read from the memory area 3B for even lines, the drawing controller 6 can write the drawing data to the memory area 3A for odd lines (the odd lines). Drawable period).

As described above, in the interlaced CRT display device, since it is possible to continuously draw in the display memory during the scanning period of one screen, it is possible to perform a high-precision drawing operation without disturbing the display of the CRT display. It can be executed in a short time.

The above is the basic display control configuration and operation of the interlace type CRT display device on which the bitmap display device of the present invention is based.

[Action]

In the first embodiment (the invention of claim 1), in such an interlaced CRT display device, the output period of the control signal that enables writing of the data output from the drawing controller is set to 1 It is set to be longer than the scanning period of the screen, and during that period, the drawing data is controlled to be continuously written in one area, and the display data is read from the other area and displayed on the CRT display.

In addition, in the second embodiment (the invention of claim 2), the output period of the control signal that enables writing of the data output from the drawing controller is arbitrarily set, and one region The drawing data is controlled to be continuously written to, and the display data is read from only the other area and displayed on the CRT display, and displayed on the CRT display during the scanning period of the line in one area. I'm trying to stop.

[Embodiment 1] Next, an embodiment of the bitmap display device of the present invention will be described in detail with reference to the drawings.

In the first embodiment, in the case of a high resolution bitmap display device, the correlation between adjacent scan lines of an image to be displayed, that is, odd lines and even lines is generally very strong, so that the interlaced method is used. When displaying by, for example, display data of odd lines,
Focusing on the fact that even if the data of adjacent even lines is used as a substitute, the display image is not greatly disturbed, the drawing data is written continuously.

Therefore, in this embodiment, the output period of the data write control signals ▲ ▼ and ▲ ▼ output from the drawing controller 6 to the memory areas 3A and 3B of the memory 3 is set longer than the scanning period of one screen, In the meantime, the drawing data is controlled to be continuously written in one area, and the display data is read from the other area and displayed on the CRT display 1.

FIG. 3 is a time chart for explaining the drawing operation of the first embodiment in the bitmap display device shown in FIG.

Also in the first embodiment, when the access to the display memory 3 is only the reading for displaying on the CRT display 1, the operation is the same as that shown in FIG.

Therefore, in order to rewrite the screen, the display memory 3
The case of writing drawing data to will be described.

First, when writing drawing data to the odd line memory area 3A, the drawing controller 6 outputs a drawing address signal and supplies the address input 1 of the odd line memory area 3A through the first multiplexer 4A. At the same time, by activating the write control signal ▲ ▼, it becomes possible to write drawing data in the memory area 3A for odd lines. That is, below the display data output of FIG. 3, during the period shown as the drawable period of the odd line area, the data output is given only from the other even line area.

During this period, the display address controller 5 outputs the display address signal in accordance with the scanning cycle of the CRT display 1. This display address signal is sent to the second multiplexer.
It is always input to the address input 2 of the memory area 3B for even lines via 4B.

As described above, in the first embodiment, in the scan in the case where the drawing data is not written, even during the period for displaying the data in the odd-numbered line memory area 3A, the writing operation to that memory area is performed. Controls the reading of data from the other even-line memory area 3B and continuous display.

By this operation, when drawing in the odd-numbered line memory area 3A is completed, next, even-numbered line memory area 3B is drawn.
To draw.

Contrary to the previous case, during this period, display data is read out only from the memory area 3A for even lines, is output to the CRT display 1, and is continuously displayed.

When drawing in the memory area 3B for even lines is completed, rewriting of one screen is completed at that point.

As described above, according to the first embodiment, it is possible to set the continuous drawing period in the display memory to an arbitrary length without causing a large disturbance in the display image on the CRT display. Therefore, a highly accurate drawing operation can be executed in a short time.

[Embodiment 2] Also in this second embodiment, the basic point of view is the first
However, in the case of displaying by the interlace method on the high resolution bitmap display device, even if the line is in the non-display state during the display period of the line in which the drawing data is being written. , Paying attention to the fact that the display image is not greatly disturbed when the brightness is slightly reduced on the screen, and during the scanning period of that line,
The display on the CRT display is stopped.
In addition, during the non-display period which is the drawing period, if the brightness of the CRT display is controlled to be increased, the display image quality is hardly affected.

In the second embodiment, write control signals ▲ ▼ and ▲ for the data output from the drawing controller 6 are output.
The output period of ▼ is set arbitrarily, and during that period, the drawing data is controlled to be continuously written in one area, and the display data is read from only the other area and displayed on the CRT display. The third embodiment is similar to the first embodiment except that the display on the CRT display is stopped during the scanning period of the line in one area.

FIG. 4 is a time chart for explaining the drawing operation in the bitmap display device of FIG. 1 according to the second embodiment.

Next, regarding the second embodiment, in order to rewrite the screen,
A case of writing drawing data in the display memory 3 will be described.

First, when writing drawing data to the odd line memory area 3A, the drawing controller 6 outputs a drawing address signal and supplies the address input 1 of the odd line memory area 3A through the first multiplexer 4A. At the same time, by activating the write control signal ▲ ▼, it becomes possible to write drawing data in the memory area 3A for odd lines.

That is, below the display data output in FIG. 4, during the period shown as the drawable period of the odd-numbered line area, the opening to the odd-numbered line memory area 3A is continuously performed.

During this period, the display address controller 5 outputs the display address signal only in the scanning period of even lines according to the scanning cycle of the CRT display 1. This display address signal is input to the address input 2 of the memory area 3B for even lines via the second multiplexer 4B.

However, during the scanning period of the odd line, the display address signal is deactivated, the reading of the display data from the display memory 3 is stopped, and the CRT display 1 is set in the non-display state.

By this operation, when drawing in the odd-numbered line memory area 3A is completed, next, even-numbered line memory area 3B is drawn.
To draw.

In the meantime, contrary to the previous case, the display data is read out and output to the CRT display 1 only during the scanning period of the odd lines.

When drawing in the memory area 3B for even lines is completed, rewriting of one screen is completed at that point.

As described above, also in the case of the second embodiment, it is possible to set the continuous drawing period in the display memory to an arbitrary length without causing a large disturbance in the display image on the CRT display. Therefore, a highly accurate drawing operation can be executed in a short time.

〔The invention's effect〕

According to the invention of claim 1 (first embodiment), the output period of the control signal that enables writing of the data output from the drawing controller is set longer than the scanning period of one screen, and during that period. The drawing data is controlled to be continuously written in one area, and the display data is read from the other area and displayed on the CRT display.

As a result, it is possible to set the duration of continuous drawing to the display memory to an arbitrary length without causing a large disturbance in the display image on the CRT display,
An excellent effect that a highly accurate drawing operation can be executed in a short time is obtained.

In the invention of the second item (second embodiment), the output period of the control signal that enables writing of the data output from the drawing controller is arbitrarily set, and during that period, the drawing data is written to one area. It controls to write continuously, reads the display data from only the other area and displays it on the CRT display, and stops the display on the CRT display during the scanning period of the line of one area. I have to.

Therefore, it is possible to set the duration of continuous drawing in the display memory to an arbitrary length without causing a large disturbance in the display image of the CRT display,
An excellent effect that a highly accurate drawing operation can be executed in a short time is obtained.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an embodiment of the bitmap display device of the present invention, and FIG. 2 is a diagram showing the data displayed on the interlaced CRT display 1 in the bitmap display device of FIG. FIG. 3 is a time chart for explaining the drawing operation, FIG. 3 is a time chart for explaining the drawing operation according to the first embodiment in the bitmap display device shown in FIG. FIG. 8 is a time chart for explaining the drawing operation in the bitmap display device of FIG. 1 according to the second embodiment. In the drawing, 1 is a CRT display, 2 is a P / S converter,
3 is a display memory, 3A is an odd line memory area, 3B is an even line memory area, 4A is a first multiplexer, 4B is a second multiplexer, 5 is a display address controller, and 6 is a drawing controller.

Claims (2)

[Claims] 1. An interlaced CRT display, a bitmap display memory having a storage capacity for one screen of the display, divided into an odd line area and an even line area, and controlling a display address. A first controller; a second controller for controlling a drawing address and a writing control to the display memory; and a multiplexer for selecting an address signal output from the first and second controllers, In a bitmap display device connected to a data processing system controlled by a central processing unit, the display memory divided into the odd line area and the even line area has an address input for each area, and the multiplexer Enter each address of the display memory And a first controller that controls the display address and the second controller that outputs a control signal that enables writing of data to the line area, respectively. The output period of the control signal that enables the writing of data to each line area of the divided display memory output from the controller 2 is set longer than the scanning period of one screen of the interlaced CRT display. During that time, while controlling to continuously write data to one area, and reading the display data from only the other area and displaying it on the CRT display, both the odd line area and the even line area can be displayed. A bitmap display device characterized in that writing operation to an area can be independently performed. 2. An interlaced CRT display, a bitmap display memory having a storage capacity for one screen of the display and divided into an odd line area and an even line area, and controlling a display address. A first controller; a second controller for controlling a drawing address and a writing control to the display memory; and a multiplexer for selecting an address signal output from the first and second controllers, In a bitmap display device connected to a data processing system controlled by a central processing unit, the display memory divided into the odd line area and the even line area has an address input for each area, and the multiplexer Enter each address of the display memory And a first controller that controls the display address and the second controller that outputs a control signal that enables writing of data to the line area, respectively. The output period of the control signal that enables the writing of data to each line area of the divided display memory output from the controller No. 2 is arbitrarily set, and the drawing data is continuously supplied to one area during that period. The display data is read from only the other area and displayed on the CRT display, and the display on the CRT display is stopped during the scanning period of the line of the one area. Thus, the write operation to both the odd line area and the even line area can be performed independently. Display devices.