JPH06118918A - Display signal output circuit - Google Patents

Abstract

PURPOSE:To output a video signal to plural CRTs having different scanning periods. CONSTITUTION:The display signal output circuit has a dual-port display RAM 3 which stores the video signal, plural buffer memories 20 which hold the output of the dual-port display RAM 3, and a control part 10 which controls their operations; and data read out of the dual-port display RAM 3 are held on the buffer memories 20 and read out of the buffer memories 20 independently of one another, thereby outputting video signals having different transfer periods in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display signal output circuit.

[0002]

2. Description of the Related Art When an image is generated by a workstation (hereinafter abbreviated as WS) used for computer graphics (hereinafter abbreviated as CG) or the like, not only is the output result displayed on a display owned by the WS, In order to use it for a presentation or the like, there are cases in which there is a demand for displaying on a normal TV or recording on a VTR.

In this case, in addition to the WS display signal, it is necessary to output a TV display signal whose timing is different from that of the WS display signal, such as an NTSC signal. Figure 7
FIG. 6 is a configuration diagram of a conventional display signal output circuit. In the figure, reference numeral 1 is a control unit for controlling the display signal output device. An input unit 2 is for inputting a video signal to the dual port display RAM 3. For example, it may be a signal processor.

Reference numeral 3 denotes a dual port display RAM, which is a large-scale integrated circuit composed of a RAM 4 and a serial access memory (hereinafter abbreviated as SAM) 5. 4 is RAM
And, it is a memory for accumulating video signals.

Reference numeral 5 is a SAM, which is a shift register for copying a part of the RAM 4 and outputting it serially. Reference numeral 6 is a display unit, which is an SA of the RAM3 for dual port display.
It displays the output from M5. A RAM port 7 is a terminal used for transmitting / receiving data for writing / reading to / from the RAM 4.

Reference numeral 8 is a SAM port, which is a terminal used for transmitting / receiving data for writing / reading to / from SAM5. AD0
Is an address signal line for designating the address of the RAM4. CT0 to control signal lines control the operation of a dual port display RAM (hereinafter abbreviated as VRAM) 3. CL is a clock line and is a clock for the shift operation of the dual port display RAM3.

In the normal usage of VRAM3, RAM is used
Write video signal from port 7 and read video signal from SAM port 8. To read a video signal from RAM4, the data is first transferred from RAM4 to SAM5, and then the contents of SAM5 are read from SAM port 8.

To transfer from the RAM4 to the SAM5, a block address is given to the VRAM3 as an address signal AD0-, and a transfer instruction is given to the VRAM3 as a control signal CT0-. The time required for transfer is one read cycle (about 200 nanoseconds) of 1 kilobit of data, and the data is completed.

The operation of the figure will be described. First, a video signal is written from the input unit 2 to the RAM 4 via the RAM port 7. RAM4 has a capacity of 1 megabit and can store one screen.

When the video signal for one screen is written, the control unit 1 transfers the video signal for one scanning line from the RAM4 to the SAM5. Therefore, it does not affect the write cycle to the RAM4.

The video signal for one scanning line transferred to the SAM 5 is sequentially sent from the SAM port 8 to the display unit 6 according to the clock (CL) supplied from the control unit 1, and the display unit 6
Displays the sent video signal.

Thus, the dual port display RAM 3
Has a RAM port 7 for writing and a SAM port 8 for outputting. Conventionally, the CR is directly output from the output of the SAM port 8 of the VRAM3 holding the image signal in the WS as described above.
Was producing a T output signal.

However, the output result is not only displayed on the display owned by WS, but also displayed on a normal TV or VTR for use in a presentation or the like.
There may be a request such as wanting to record on.

In this case, in addition to the WS display signal, it is necessary to output a TV display signal whose timing is different from that of the WS display signal, such as an NTSC signal. In this case, the VRAM3 of the conventional display signal output device is read out from different addresses at different cycles to obtain a plurality of CRTs.
It is necessary to send out the output signal.

[0015]

However, VRAM3
However, since the SAM5 can store only one scanning line image signal (corresponding to a block address) at a time, there has been a problem that the image signal cannot be simultaneously output to a plurality of CRTs having different scanning periods. .

In view of the above points, the present invention aims to output CRT signals having different timings at the same time.

[0017]

The above-mentioned problems can be solved by a display signal output circuit configured as follows. FIG. 1 is a principle diagram of the present invention.

A display signal output circuit having a dual port display RAM 3 for storing video signals, a plurality of buffer memories 20 for holding the outputs of the dual port display RAM 3, and a control section 10 for controlling the operations thereof. The data read from the dual port display RAM 3 is held in a plurality of the buffer memories 20, and the data is read from several buffer memories 20 independently of each other, so that different transfer cycles can be achieved. It is configured to output the held video signals in parallel.

[0019]

According to the control of the control unit 10, the video signals corresponding to one scanning line read from the dual port display RAM 3 in which the video signals are stored are stored in the plurality of buffer memories.
The video signals are stored in the buffer memory 20 and read from the buffer memory 20 independently of each other at a speed necessary for display.

Therefore, it is not necessary to competely read the data of the SAM port of the dual port display RAM3.

[0021]

FIG. 2 is a block diagram of an embodiment of the present invention. In this configuration, a dual buffer configuration in which the buffer memory is duplicated is adopted for the purpose of high speed operation.

In the figure, reference numerals 21, 22, 23 and 24 denote buffer memories for holding a video signal for one scanning line. Switching circuits 11 and 12 switch the output of the duplicated buffer memory for each scanning cycle, thereby speeding up the writing of the buffer memory being displayed and the writing for the next scanning line by dividing the functions. .

A high resolution control unit 51 controls the display of the high resolution display unit 61. Reference numeral 61 is a high-resolution display unit, which has high resolution and has 1280 × 1024 pixels.
S is a display device.

A low resolution control unit 52 controls the display of the low resolution display unit 62. Reference numeral 62 denotes a low resolution display unit, which is an apparatus for displaying an NTSC signal (low resolution signal) having 640 × 480 pixels.

The transfer request signal HRQ is a signal which the high resolution control section 51 requests the control section 10 to transfer the video signal, and the transfer request signal LRQ is the low resolution control section 52 which requests the control section 10 to transfer the video signal. Signal to do. In addition, the same reference numerals as those in FIG. 7 are the same.

FIG. 3 is a time chart of control signals. The high resolution control section 51 and the low resolution control section 52 to the control section.
10 shows the timing of the control signal output to 10. HSYNC (H) and HSYNC (L) represent horizontal synchronization signals in the high resolution control unit 51 and low resolution control unit 52, respectively, and VBLANK (H) and VBLANK (L) are high resolution control unit 51, respectively.
And the vertical blanking interval signal in the low resolution control unit 52.

HSYNC (H) occurs every 13.945 microseconds and HSYNC (L) occurs every 63.5 microseconds. VBLA
Displayed when NK is low level. Further, it is assumed that this VBLANK input to the control unit 10 becomes low level by one horizontal scanning period before the timing when the image is actually displayed. This is for reading the video signal in advance.

FIG. 4 is a display signal read cycle time chart (No. 1). This is the operation at the time of FIG. 3, and is the case where only the high resolution control section 51 and the high resolution display section 61 operate.

The following operation is performed by the control unit 10.
HSYNC (H) ((a) in the figure) is high level and VBLANK (H) ((in the figure)
The timing when (b)) becomes the low level and the high resolution control unit 51 issues the transfer request signal HRQ ((c) in the figure) is captured. In FIG. 3, this corresponds to the timing of.

Next, a block address corresponding to a scanning line required by the high resolution control section 51 is given to the VRAM3,
A transfer cycle ((d) in the figure) is performed, and the video data of a predetermined display row is transferred from RAM4 to SAM5.

Then, the data read from the SAM port is transferred to the buffer memory 21 ((e) in the figure). When the transfer is completed, the transfer request signal HRQ is reset by the completion notification signal from the control unit 10.

The transfer time is 1 Mbit VRAM,
Transferring 256 data with 30 nanosecond clock 7.
Since it is 68 microseconds, the time for one horizontal scanning period is sufficient. At the timing of, the predetermined line is displayed by sending the video signal of the buffer memory 21 to the high resolution display section 61 ((f) in the figure).

At the same time, the video data of the next display line is transferred from the SAM port to the buffer memory 22. Then, similarly, it is displayed on the high resolution display section 61. Buffer memory like this
Images are displayed on the high-resolution display unit 61 by performing transfer by alternately using 21, 22.

At the timing of, the low resolution display section 62
Since HSYNC (L) becomes high level and VBLANK (L) becomes low level, the low resolution control unit 52 also needs to transfer the video signal. Here, the low resolution side divides the transfer of the video signal into two to perform split transfer for shortening the waiting time on the high resolution side.

FIG. 5 is a display signal read cycle time chart (No. 2). The operation at this time will be described with reference to the drawing. First, at a timing, the transfer request signal HRQ ((c) in the figure) of the high resolution control section 51 is generated before the transfer request signal LRQ ((i) in the figure) of the low resolution control section 52, and the buffer is transmitted from the SAM port. Transfer to the memory 22 ((d) in the figure) is performed.

When the transfer of the high resolution control section 51 is completed, the transfer request signal LRQ of the low resolution control section 52 is generated at the timing t1. That is, the VRAM3 is made to perform the first half cycle of the split transfer, first, the data of the display row is sent from the RAM4 to the SAM5, and the data of the SAM port is transferred to the buffer memory 23 only in the first half (timing S
2).

The transfer time from the SAM port to the buffer memory 23 in this case is 3.84 microseconds, which is half the transfer time on the high resolution side, since split transfer is used. Since the timing in the middle of the transfer on the low resolution side is entered, it is necessary to perform the transfer on the high resolution side, but the transfer on the high resolution side is waited until the transfer on the low resolution side is completed (timing S3).

As described above, since the cycle of one horizontal scanning period on the high resolution side is short, split transfer is performed on the low resolution side. After the transfer of the first half of the low resolution side is completed, the transfer of the high resolution side shown in FIG. 5 occurs, and when that ends, the transfer request of the remaining second half of the low resolution side occurs.
(Timing S3).

When a transfer request for the remaining second half on the low resolution side is generated at timing S3, the same block address and control signal as those in the first half are sent from the control unit 10 to the VRAM3 as before.
VRAM3 sends the data of the display row from RAM4 to SAM5 and transfers the latter half data to the buffer memory 23 from the SAM port.

The video signal of the buffer memory 23 is sent to the low resolution display section 62 at the timing of S4. FIG. 6 is a display signal read cycle time chart (No. 3).

At the timing S8 in FIG. 3, the transfer request signal LRQ on the low resolution side ((i) in FIG. 6) is being transferred during the transfer on the high resolution side.
However, this transfer request is made to wait until the end of transfer on the high resolution side (timing S5 in FIG. 6).

When the transfer on the high resolution side is completed, the transfer on the first half on the low resolution side is performed. After the transfer in the first half, there is no transfer request from the high resolution side, so the transfer in the latter half of the low resolution side continues (timing S6).

Since the timing S9 is entered during the latter half of the transfer, the transfer request signal HRQ on the high resolution side ((i) in FIG. 6) comes, but this request is the SAM of the latter half image data on the low resolution side.
End of transfer from port to buffer memory 23 (Timing S
7) It will be accepted later.

Thus, until the transfer request signal HRQ is accepted, the signal is extended by the time t2 shown in the figure. In this way, by controlling the transfer of the high resolution side and the low resolution side by the control circuit, the high resolution display section having different resolutions is obtained.
The video signal of 61 and the video signal of the low resolution display unit 62 can be simultaneously generated.

In this embodiment, the case where the signals of the two high resolution display sections and the low resolution display sections are generated at the same time has been described. However, if a plurality of buffer memories are provided, a plurality of video signals can be generated at the same time. It is possible.

[0046]

As described above, according to the present invention, a plurality of CRT signals having different resolutions can be simultaneously output, so that a multi-CRT system used for presentations can be easily constructed. it can.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a time chart of control signals

FIG. 4 is a display signal read cycle time chart (part 1).

FIG. 5 is a display signal read cycle time chart (part 2).

FIG. 6 is a display signal read cycle time chart (part 3).

FIG. 7 is a configuration diagram of a conventional display signal output circuit.

[Explanation of symbols]

1 control unit 2 input unit 3 VRAM 4 RAM 5 SAM 6 display unit 7 RAM port 8 SAM port 10 control unit 11, 12 switching circuit 20, 21, 22, 23, 24 buffer memory 51 high resolution control unit 52 low resolution control unit 61 high resolution display 62 low resolution display

Claims (1)

[Claims] 1. A dual port display RAM (3) for storing a video signal, and the dual port display RAM (3)
Is a display signal output circuit having a plurality of buffer memories (20) for holding the outputs of the above, and a control unit (10) for controlling the operations thereof, wherein the data read from the dual port display RAM (3) Are stored in a plurality of the buffer memories (20), and data are read from several buffer memories (20) independently of each other, thereby outputting video signals having different transfer cycles in parallel. Display signal output circuit characterized by.