JPH05197359A - Lookup table circuit for display - Google Patents

Abstract

PURPOSE:To reload data in a lookup table memory without generating irregularities on a screen even in the display of short display blanking period. CONSTITUTION:The input of multiplexers 203, 206 are selected to the address bus 102-2 side and the input register 205 side in an ordinary operation. Therefore, reload data from a display control circuit 101 is written on buffer memory 201 for reload as necessary irrespective of a display timing. Also, display data from frame memory 104 is sent to each lookup table memory 202 via the input register 205, and is converted to color data at the memory, and is sent to the display via an output register 207. When the display blank period is started after write on the buffer memory 201 for reload is finished, a controller 208 switches both input of the multiplexers 203, 206 to the address counter 204 side. Thereby, the reload data can be transferred from the buffer memory 201 for reload to each lookup table memory 202 comprehensively in a short period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display look-up table circuit used in information equipment such as computers, measuring equipment and word processors.

[0002]

2. Description of the Related Art When displaying on a screen of a display such as a color CTR or a color LCD, image information stored in a frame memory is read by R (red), G for each pixel
(Green) and B (blue) color signals are converted and output to the screen.

The look-up table circuit makes this change, and a look-up table memory (RAM) having a capacity corresponding to the number of pixels of the display is provided inside. In this look-up table memory, R, G,
If each color of B is represented by, for example, 3 bits and 8 gradations, color data of 256 colors is stored.

By the way, the color data stored in such a look-up table memory may be rewritten, but in the conventional information equipment, this rewriting is performed during a display blank period such as a vertical blank period. ..

[0005]

However, although flat display devices have been widely adopted recently, in the case of such a flat type screen, the vertical blanking period becomes short.

Therefore, this rewriting cannot be completed during the vertical blanking period, and the rewriting must be performed even during the display period. In such a case, problems such as noise being generated on the screen during the display operation and the color of the screen changing from the middle occur.

The present invention has been made in view of the above circumstances, and even if the display blank period of the display is short, the data stored in the look-up table memory is not disturbed on the screen. It is an object of the present invention to provide a display look-up table circuit capable of rewriting.

[0008]

As a means for solving the above problems, the present invention reads display data accumulated in a frame memory on the basis of control signals from a display control circuit and a display timing control circuit, In a display look-up table circuit that outputs the display data to a display device by giving a color or a brightness to each pixel, the color data or the brightness data corresponding to the color information or the brightness information attached to the display data is stored. A plurality of look-up table memories and a rewriting buffer memory for storing rewriting data regarding the color data or the luminance data sent from the display control circuit at any time regardless of display timing. The rewrite data stored in the buffer memory is displayed. The plurality of lookup table memories are displayed during the blank period. By transferring, it is characterized in that to perform said color data or collectively rewriting of luminance data.

[0009]

In the above structure, the display control circuit and the display timing control circuit are arranged such that, during the display period, the display data read from the frame memory is provided with color data or luminance data by a plurality of lookup table memories. And output it to the display.

On the other hand, the rewriting data from the display control circuit is written in the rewriting buffer memory at any time regardless of whether it is the display period or the display blank period.

As described above, after the rewriting data is written in the rewriting buffer memory and then the display blank period starts, the rewriting data is transferred from the rewriting buffer memory to the plurality of look-up tables, and the look-up table memory. Rewriting of the color data or the luminance data in the above is performed collectively. The time required for this rewriting is sufficiently shorter than the display blank period. Therefore, the screen is not disturbed by this rewriting.

[0012]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 2 is a block diagram of an apparatus for controlling the look-up table circuit according to this embodiment.

In FIG. 2, a main memory 103, a frame memory 104, and a display timing control circuit 105 are connected to a display control circuit 101 provided in the CPU via a system bus 102.

The main memory 103 stores programs, data, etc. of the display control circuit 101. The frame memory 104 stores an image to be displayed on the screen, and stores index information such as color or gradation in 1 byte, for example, corresponding to 1 pixel of the screen.

The display timing control circuit 105 is for generating a display timing signal and the like, and sequentially reads display data from the frame memory 104 in accordance with the display timing of the screen and uses it for the lookup table circuit 106.
Is output to the display device 107 via.

The look-up table circuit 106 converts the screen color or gradation index read from the frame memory 104 into actual R, G, B color data or monochrome luminance data, and outputs this to the display 107. To do. The display 107 may be, for example, a flat display device such as LCD (liquid crystal), EL (electroluminescence), plasma or CRT.

FIG. 1 is a block diagram showing the structure of the lookup table 106 shown in FIG. In this figure, the lookup table circuit 106 is provided with one rewriting buffer memory (RAM) 201 and a plurality of lookup table memories (RAM) 202.

The rewriting buffer memory 201 has the same capacity as one lookup table memory 202, and temporarily buffers the data to be written in the lookup table memory 202. The display control circuit 101 can perform read / write access to the rewriting buffer memory 201 via the data bus 102-1, the address bus 102-2, the multiplexer 203, and the reading output buffer 209. It should be noted that the plurality of look-up table memories 202 can simultaneously display the display unit 10.
It has the same number of memory units as the number of pixels to be output to 7.

The multiplexer 203 is a display control circuit 1
The CPU address signal sent from 01 via the address bus 102-2 and the transfer address signal from the counter 204 are switched and one of the address signals is output to the rewriting buffer memory 201. is there. Further, the counter 204 is the rewriting buffer memory 2
The address signal is a read address of 01 and a write address of the lookup table memory 202.

The controller 208 controls the entire look-up table circuit 106, and inputs a control signal 210 such as a vertical blank timing signal or a transfer start command signal from the display timing control circuit 105 or the display control circuit 101. ..

The input register 205 is the frame memory 1
The display data is received from 04 and held. The plurality of input registers 205 are provided with register units having the same number of bits as the number of bits of an index representing one pixel, the number of pixels which the display unit 107 requires at the same time.

The multiplexer 206 has a counter 204.
Output of the input register 205 and the output of the input register 205 are switched, and any one of them is output as the address of the lookup table memory 202. Further, the output register 207 is the lookup table memory 20.
Hold the data output from 2 and display it on the display 1
It is output to 07.

Next, the operation of the embodiment of the present invention configured as described above will be described with reference to the time chart of FIG.

First, in the normal case, the multiplexer 203
Selects the input from the address bus 102-2 side, and the multiplexer 206 selects the input from the input register 205 side. Therefore, the rewriting buffer memory 20
1 can store the rewriting data from the display control circuit 101 in both the display period and the display blank period. On the other hand, in the lookup table 202, the frame memory 104 sent from the input register 205
The index information of is converted into color data or luminance data, and this is output to the output register 207.

Here, the frame pulse (F
P) 301 is a signal output from the display timing control circuit 105, which is output once for each display of one screen. That is, the vertical synchronizing signal VSYNC on the CRT
Is equivalent to. Similarly, line pulse (LP)
302 is output once for each display of one line, and corresponds to the horizontal synchronizing signal HSYNC in the CRT.

The data 303 output to the display unit 107 is one line (one row) per line pulse 302. In the example of FIG. 3, the display 107
One screen of is formed by 480 lines.
After the output of the data for the lines, the dummy row timing for the four lines is generated. A clock pulse 309 is used to control the entire apparatus.

Now, when the data writing to the rewriting buffer memory 201 is completed, the display control circuit 101
The display timing control circuit causes the vertical sync interrupt signal 306 (L
It will wait for the output of (signal). The vertical sync interrupt signal 306 is output at the start of displaying one screen.

When the vertical sync interrupt signal 306 is output,
The display control circuit 101 includes a display timing control circuit 105.
The transfer start signal 305, which is a command signal, is set to the look-up table circuit 106 via the, or directly to the look-up table circuit 106. By this setting, the vertical synchronization interrupt signal 306 is reset from the L level to the H level.

When the transfer start signal 305 is set, the controller 2 of the lookup table circuit 106
08 waits until the vertical blank period comes. Then, the vertical blank signal 3 from the display timing control circuit 105
The controller 208 sets the transfer enable signal 307 when it knows the start of the vertical blanking period by 04 (active only for the period of the dummy line of 4 lines).

While the transfer enable signal 307 is active, the multiplexers 203 and 206 are
Both select the input from the address counter 204 side.
As a result, the read address of the rewrite buffer memory 201 and the write address of each look-up table 202 become the same, and rewrite data is transferred from the rewrite buffer memory 201 to each look-up table memory 202. Reference numeral 308 in FIG. 3 denotes an address signal for the look-up table memory 202, and the address counter 204 generates an address from start to end during rewriting data transfer.

When the transfer of the rewriting data is completed, the transfer enable signal 307 and the transfer start signal 305 are reset. As is clear from the time chart in Fig. 3,
The period during which the transfer enable signal 307 is active is sufficiently shorter than the vertical blank period.
Therefore, rewriting data is not performed during the display period, and even in the case of a flat screen display device having a short vertical blank period, the screen is not disturbed.

[0032]

As described above, according to the present invention, the rewriting buffer memory is provided so that the rewriting data can be accumulated at any time, and the rewriting data is looked up from the rewriting buffer memory during the display blank period. Since it is configured to rewrite by collectively transferring to the table memory, even if the display has a short display blank period, the data in the lookup table memory can be rewritten without disturbing the screen. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a look-up table circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of an information device using the look-up table circuit of FIG.

FIG. 3 is a time chart for explaining the operation of FIGS. 1 and 2.

[Explanation of symbols]

 101 Display Control Circuit 104 Frame Memory 105 Display Timing Control Circuit 106 Lookup Table Circuit 107 Display 201 Rewriting Buffer Memory 202 Lookup Table Memory

Claims (1)

[Claims] 1. A display device in which display data accumulated in a frame memory is read based on control signals from a display control circuit and a display timing control circuit, and the display data is given a color or a brightness for each pixel. A display look-up table circuit for outputting to a plurality of look-up table memories for storing color data or brightness data corresponding to the color information or brightness information attached to the display data, and sent from the display control circuit. And a rewrite buffer memory that stores rewrite data for the color data or the brightness data at any time regardless of display timing. The rewrite data stored in the rewrite buffer memory is stored in the rewrite buffer memory during the display blank period. Rewriting of the color data or luminance data by transferring to the lookup table memory of Display look-up table circuit and performing collectively.