JPH02230190A - Image signal processor - Google Patents

Abstract

PURPOSE:To eliminate the need for an A/D converter and its control circuit, to miniaturize a system and to reduce the cost of a processor by outputting display data converted with a pallet not only for a CRT but also for flat display. CONSTITUTION:A pixel clock 116 and a pixel address 117 are supplied to an interface I/F part 101 with a display controller in an image signal processor 100. The pallet 102 constituted of a RAM is converted to digital color data of R, G, and B by setting supplied display data as address signals and reading the stored data. The color display of the converted data is performed on the CRT display through decoders 103 - 105 and D/A converters 106 - 108. G signals 113 indicating digital color data most naturally are used to display data on a monochrome liquid crystal through a liquid crystal or a plasma display I/F 115.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applicable to personal computers and engineering workstations with expanded graphic functions, which are controlled by a display controller or microprocessor, This invention relates to an image signal processing device that generates an image signal for displaying a display, etc., and particularly relates to an image signal processing device that has a palette (also called a lookup table) that converts display data into display data. [Prior Art] FIG. 8 shows a conventional system for displaying a CRT display, a liquid crystal display, or a plasma display, which is equipped with a palette for converting pixel-by-pixel display data into display display data (for example, digital RGB data). Give an example. According to the conventional example shown in FIG. 8, the palette 82 is composed of a RAM (hereinafter referred to as palette RAM), and a display controller 81 generates a clock 92 (pixel clock) corresponding to l pixels and a display for each picture. Data 99 (pixel address) is supplied.
The palette 82 uses this display data as an address to
Conversion to display display data 93 is performed by performing an AM read operation. Palette conversion data is written to the palette RAM by the microprocessor 80 via data path 96. The display display data 93 converted by the palette is converted into a signal 88 (for example, an analog RGB signal) for CRT display display by a digital-to-analog converter C (hereinafter referred to as a D/A converter) of 83, and is supplied to the CRT display 87. be done. Also, the synchronization signal 91 to the CRT display
is supplied from the display controller 81. On the other hand, in order to display a liquid crystal or plasma display, the analog signal for the CRT display, which is the output of the D/A converter 83, is converted into an A/D converter using an analog-to-digital converter 84 (hereinafter referred to as an A/D converter). After D conversion,
Liquid crystal/plasma display interface device 85
The display data 90 is supplied to the display data 90. The interface device 85 is also supplied with a pixel clock 92 corresponding to one pixel from the display controller 81, and takes in data for each pixel. liquid crystal,
A synchronizing signal 91 for plasma display display is also transmitted to the display. The data is supplied to the interface device 85 from the controller 8l. Thereafter, the interface device 85 outputs a digital display signal 89 to display on a liquid crystal or plasma display 86. In FIG. 8, 94 is a control signal for the pallet 82 outputted from the microprocessor 80, and 95 is a read/write signal similarly outputted from the processor for putting the pallet 82 into a writing or reading state. When the palette 82 is set to the write state by 95, it writes the display conversion data supplied from the bus 96, and when it is set to the read state by 95, it reads the display conversion data from the bus 96. Further, 97 is a control signal by which the processor 80 controls the display controller 8l, and 98 is a bidirectional data path between the two. [Problems to be Solved by the Invention] In the prior art described above, when displaying on a flat display, the palette output is converted into an analog RGB signal for displaying on a CRT display. After D/A conversion to an analog signal, it must be converted to a digital signal again using an A/D converter to create a signal for displaying on a liquid crystal or plasma display, which increases the number of devices and requires a display system. This had the problem of making it larger and more expensive. In addition, as in the conventional example shown in FIG. 7, a normal palette is composed of a semiconductor memory such as RAM or ROM, and the conversion operation is performed by reading the memory. There is a delay time after the display data (pixel address) is supplied to the palette until it is converted to the 93 display data or the 88 analog signal and output. In addition, this delay time is due to the read time of ROM or RAM, and the read time of semiconductor memory is unstable and has a considerable variation due to manufacturing etc., so this delay time is unstable. It becomes something. Therefore, the phase relationship between the pixel clock 92 or synchronization signal 91 output from the display controller in synchronization with the pixel address 99 and the display display data that includes a time delay becomes unstable, causing a timing shift. Put it away. In the conventional example shown in FIG. 7, since the pixel clock 92 and the synchronization signal 9l are supplied from the display controller to the interface device 85, the timing of data capture on the interface device side is controlled and the A/ Not only was it extremely difficult to control the timing of the D converter, but it also had the problem of not necessarily capturing accurate data and causing problems such as jitter on the display. Furthermore, due to the above-mentioned phase relationship, it was extremely difficult to speed up the system. The same applies when displaying on a CRT display, and the synchronization signal 9 is supplied to the CRT display.
1 and the signal 88 for display display have an unstable phase relationship, which has the problem of causing problems such as ZIC. Therefore, the present invention aims to solve these problems.
Its purpose is to provide image processing that is suitable for systems that display flat displays such as liquid crystal displays or plasma displays, that is small, low cost, capable of high-speed processing, and that can generate high-quality images. The objective is to supply equipment. [Means for Solving the Problems] The image signal processing device of the present invention is controlled by a display controller or a microprocessor, receives pixel-by-pixel display data as input, and is a storage device that converts the data into display display data. In the image signal processing device which outputs an image signal for display on a display, the image signal processing device has a terminal for outputting the display display data converted by the palette as an image signal for display on a CRT display. , and a terminal for outputting an image signal for display on a flat display. Second, the image signal processing device has a terminal for outputting a clock signal corresponding to one screen unit, and outputs an image signal for displaying the flat display in synchronization with the clock signal. Features: Third, in the image signal processing device, (a) a horizontal synchronization signal circuit including a horizontal synchronization signal input terminal, a horizontal synchronization signal delay circuit, and a horizontal synchronization signal output terminal; (b) a vertical synchronization signal input terminal and a vertical synchronization signal circuit; (c) a blanking signal circuit consisting of a blanking signal input terminal, a blanking signal delay circuit, and a blanking signal output terminal; at least one circuit of the following; The present invention is characterized in that it has the same delay time as the time required to convert the display data input into image data for display on a display.

Fourthly, in the image signal processing device, the first, second, and third means are integrated on the same semiconductor substrate. [Example 1] The present invention will be explained below based on an example. 1st
Figures (a) and (b) are diagrams showing a first embodiment of the present invention, and 100 is an image signal processing device according to the present invention. 101
is an interface I/F unit with the display controller, and from the display controller, the pixel clock 116
and the pixel address 117 is supplied. A pixel clock is a clock that has a pixel frequency. Furthermore, pixel addresses are digital display data for each pixel that is synchronized with the pixel clock. Reference numeral 102 denotes a palette, which is composed of a RAM, uses 8-bit display data (pixel address) supplied from the display controller as an address signal, and reads out the data stored at the specified address to display R (Red). )6bit. G
(Green) 6bit. B (Blue) 6-bit digital color data (112 to 114)
It is converted to . 103 to 105 are each R. Decoders 106 to 108 decode the G and B palette output data for D/A conversion, and each R. G. This is the D/A converter of B. 115 is a liquid crystal or plasma display.
It is an interface device, which is supplied with data converted by a palette from 100 image signal processing devices,
Display on liquid crystal or plasma display. way, 10
9 to 111 are analog RGB signal outputs, and 106
By outputting the analog RGB signals D/A converted by the D/A converters 108 to 108, a color display is made on the CRT display according to the combination of degrees of each RGB analog value. In Figure 1(a), digital RGB data (18 bits) converted by the palette
Since then, G6bit is input to a liquid crystal or plasma display interface device, but with this configuration, along with a CRT display, 2'
It can be applied to systems that display monochrome liquid crystal or plasma displays capable of displaying = 64 gradations. The reason why G6 bit of digital RGB data is output for liquid crystal or plasma display is as follows. RGB primary color signal as luminance signal (Y)
When converting to , the following conversion formula is used. Y=0.3R+0.59G+0.1 1B As can be seen from the above equation, among the R component, G component, and B component, the G component has the largest weight on the luminance signal (Y). therefore,
When trying to display a black and white (monochrome) display, R. G. If an attempt is made to display using any one of the B signals, the most natural display will be to use the G signal. For this reason, 6 bits of G data is output as display data for liquid crystal or plasma displays. In FIG. 1(b), R. G. B, each of ``2nd place 2
A total of 6 bits are input to the interface device, and with this configuration, C
It can be applied to color liquid crystal displays that can display 64 colors as well as RT displays. In addition to the above two examples, the output to the liquid crystal or plasma display interface device may be determined depending on the display capacity of the display. Further, in the embodiment shown in FIG. 1, a circuit for writing data into the palette RAM is omitted. Further, the image signal processing device 100 is realized as a one-chip semiconductor integrated circuit configured on the same semiconductor substrate. FIG. 2 shows an image signal processing apparatus using an image signal processing apparatus according to a second embodiment of the present invention. Indicates the display method using liquid crystal or plasma display. 140 is
1 is an image signal processing device that is an embodiment of the present invention.

A display controller 120 supplies pixel data 125, which is digital display data for each pixel, and a pixel clock 126 having a pixel frequency to the image signal processing device 140. 131 is a palette, which is made up of RAM. l21 is a microprocessor (hereinafter referred to as MPU) that controls the entire system.
124 is a data path for transferring data between the image signal processing device 140, 123 is a read signal, and 12
2 is a write signal. In response to signals l24, 123, and 122, the MPU writes and reads conversion data to and from the palette RAM. Reference numeral 132 denotes an MPU interface circuit, which controls and interfaces the image processing apparatus 140 when a request for writing or reading from the palette RAM is received from the MPU. 133 is a data bus for transferring data to and from the palette RAM. The visual output 126 sent from the display controller 120 is input to the timing generator circuit 127. The timing generator generates a clock 128 to the pixel address register 130 and a clock 136 to the display data register 135 from the input pixel clock. The pixel address input from 125 is 1
30 is input to the pixel address register, is taken into the register by the clock 128, and is input to the pallet R.
Provides address 129 to AM. Palette RAM stores data 13 at the location specified by 129.
4 to the display display data register of 135. Each location in the palette RAM stores RGB color data or green color data. A display data register 135 takes in data 134 output from the palette RAM using a clock 136. The data taken into the register is output from the data bus 137. A clock 136 to the display register 135 is also output from the image signal processing device 140. A clock 136 and a display disk 137 output from the image signal processing device are input to a liquid crystal or plasma display interface device 138 to drive a display 139. With this configuration, display data 137 synchronized with the output clock 136 is supplied to the interface device. In other words, the display data 137 is determined when the data is taken into the display display data register 137 by the clock 136, and this clock 136 is output as is, so the display data 137 and the clock 136 are always synchronized and there is no phase shift. It doesn't happen. Note that the image signal processing device 140 is realized as a semiconductor integrated circuit of a chip. FIG. 3 shows a method of displaying a display device using an image signal processing device according to a third embodiment of the present invention. 161 is an image signal processing device that is an embodiment of the present invention. l41 is the display controller, 161
A pixel address 143 serving as display data, a pixel clock 142 having a pixel frequency synchronized with the pixel address, a horizontal synchronization signal 144 synchronized with the pixel clock, and a vertical synchronization signal 14 are provided in the image signal processing device of
Supply 5. 151 is a pallet. , consists of RAM. A clock buffer circuit 146 supplies a clock 148 from the inputted pixel clock 142 to a pixel address register 147, a display data register 155, and synchronization signal registers 150 and 156. The pixel address register 147 takes in the pixel address supplied from 143 using the clock 148, and supplies address 149 to the palette RAM 151. Palette RA
M converts the pixel address into display display data stored at the address specified by this address, and outputs it to the display display data register 155 through the data bus 154. The display data register 155 receives data output from the palette RAM using the clock 148. The data taken into the display display register is output from the data path 157 and supplies image data to the display device 160. On the other hand, the horizontal synchronization signal 144 and the vertical synchronization signal 145 are input to the image signal processing device 161 and then input to the synchronization signal register A 150.
A synchronization signal register A 150 takes in data in response to a clock 148, and outputs a horizontal synchronization data 152 and vertical synchronization data 153 to a synchronization signal register B 156. Similarly, the synchronization signal register B of 156 is connected to the clock 14.
8 takes in data, and outputs each synchronizing signal to the outside through the horizontal synchronizing signal output 158 and the vertical synchronizing signal output 159. Horizontal, output from the image signal processing device
The vertical synchronization signal is provided to 160 display devices. With this configuration, the horizontal and vertical synchronizing signals supplied from 144 and 145 are delayed by a shift register made up of two registers 150 and 156, and then output from 158 and 159. It turns out. Then, a pixel address is supplied from l43,
The delay time from being taken into the pixel address register of 147 until it is converted to display display data and output to the data path of 157, and the horizontal and vertical synchronization signals supplied from 144 and 145 are input to the register of 150. The delay time from capture to output from 158 and l59 is the same. This is Regisk 1
47 and register 150 are controlled by the same clock, and register 155 and register 156 are controlled by the same clock. Further, in the embodiment shown in FIG. 3, a circuit for writing data from the MPU to the palette RAM is omitted. Note that the image signal processing device 161 is realized as a single-chip semiconductor integrated circuit. Next, FIG. 4 shows an example in which the functions shown in the first to third embodiments described above are implemented as one image signal processing device. This image signal processing device 15 is constructed on the same semiconductor substrate, and inputs a pixel address (8 bits), which is digital display data for each pixel, into an R. G. B, 6 bits each
The RGB data is converted into digital and analog signals, and is output as an analog RGB signal for display on a CRT display. At the same time, 6 bits of G data is output as digital data. 16 is a pixel clock input terminal,
17 is a horizontal synchronizing signal input terminal, l8 is a vertical synchronizing signal input terminal, and 19 is a pixel address input terminal, and the above signals are supplied from the display controller and roller. 2
0 is a data bus, 21 is a control signal input terminal, 2
2 is a read/write control signal input terminal,
The above signals are supplied from the MPU that controls the system, and are used when the MPU writes and reads conversion data to and from the palette RAM. The pixel clock is input to the timing generator 1, and the timing generator generates the clock 24 and the clock 25 whose phase change is delayed from the clock 24. The clock 24 is supplied to the synchronization signal register A (2) and the pixel address register (3). The clock 25 is supplied to the synchronization signal register B of 7, the R register of 8, the G register of 9, the B register of 10, and the GDATA register of 1l. The pixel address register No. 3 takes in the pixel address data inputted from the input terminal 19 by the clock 24, and the pixel address register No. 3 receives the pixel address data inputted from the input terminal 19 by the clock 24.
bit RAM) with address 32. Palette R
AM performs a read operation of data stored in the area specified by address 32, and reads R6bit, G6bit
．． Outputs 86-bit data in parallel to 35, 36, and 37 data paths. The registers 8, 9, and 10 take in the data output from the palette RAM using the clock 25, and output the data to the D/A converters 12, 13, and 14. Each D/A converter of 12, 13, and 14 is
The data of R6bit tt G6bit tt 86bit t are each D/A converted, and the R output terminal of 44, 45
G output terminal of 46, B output terminal of 46, more analog RGB
Output as a signal. Also, among the RGB data output from the palette RAM, 36 6-bit G data are also supplied to 11 G data registers, and the 1l G data register takes in the data with the clock 25.
It is output as 6-bit data from the 47 digital G data output terminal. The synchronization signal register of 2 is 17, 1
The horizontal synchronization signal and vertical synchronization signal input from the terminal 8 are taken in by the clock 24. The synchronization signal taken into the register 2 is input to the delay circuit 5.
This delay circuit is designed to prevent the shift registers 26 and 27 from malfunctioning due to clock skew by synchronizing signal registers A and B at the same time that register A takes in synchronizing signals l7 and l8.
This delays the synchronization signal output as . Without this delay circuit, the synchronization signal held in register A by clock 24 would be immediately held in register B by clock 25, and there is a risk that the synchronization signal would be output one pixel clock earlier. The synchronization signals 28 and 29 output from the delay circuit No. 5 are input to the synchronization signal register B No. 7. A synchronization signal register 7 receives a synchronization signal using a clock 25, and outputs it from a horizontal synchronization signal output terminal 42 and a vertical synchronization signal output terminal 43. Further, the clock 25 is output from the pixel clock output terminal of 4l. Reference numeral 4 denotes an MPU interface circuit, which controls the writing and reading of conversion data to and from the palette RAM in accordance with the control signal from the control signal input terminal 2l and the read/write signal from the read/write signal input terminal 22. conduct. The interface circuit 4 outputs an 8-bit write address 30 and a control signal 31 to the palette RAM 6 to the pixel address register 3, outputs a read/write signal 33 to the palette RAM 6, and exchanges conversion data 34 with the palette RAM. Read and write. data path 20
The address data and conversion data are supplied from the display controller. A control signal from 21 switches whether the data input from 20 is an address or conversion data. If the read/write signal from 22 indicates a write and the control signal indicates an address, then 2
The address from the 0 data path is output to address register 3 via bus 30. At this time, the control signal 31 changes the data taken in by the register 3 from 19 to 3.
Switch to 0 1I+. Next, when the control signal of 2l indicates conversion data, the conversion data from 20 is supplied to the palette RAM via 34, and since the read/write signal 33 indicates writing, it is input from 20 and taken into the register 3. The converted data input from 20 will be written into the area specified by the address. When the read/write signal from 22 indicates reading, the converted data is read from the palette RAM to 35, 36, and 37 according to the pixel address input from 19, or the data to the bus 20 is read from the palette RAM. It will be done. FIG. 5 is a timing chart showing the operation of the image signal processing device shown in FIG. 4. (a) is the manually operated pixel clock as shown in FIG.
4, (c) is the clock of FIG. 4, 25.
The phase difference between (b) and (c) is the time required to convert the display data in the palette RAM. (d) is shown in Figure 41.
7, and (e) is the pixel address input from FIG. 4, 19. (f) is the signal in FIG. 4 26, and (b
) is the horizontal synchronization signal captured by the clock.
(g) is the signal shown in FIG. 4, which is the pixel address taken into the pixel address register 3 by the clock shown in (b), which becomes the address 32 of the palette RAM. (h
) are the signals 35, 36, and 37 in Fig. 4, and the pallet RAM
This is the output data of (i) is a horizontal synchronizing signal outputted from FIG. 42, which is taken in by the clock shown in (c) and outputted by the resistor shown in FIG. 47. (j) is the digital G data output from Fig. 4 47 or 38
, 39 and 40, respectively, and are output by the clock shown in FIG.
, 10 registers and output. (k) is analog RGB output from Fig. 4 44, 45, 46
8, 9, and 9 in FIG. 4 by the clock in (c).
The data is taken into each register of IO, and output after D/A conversion. Next, FIG. 6 shows a block diagram of a system for displaying a CRT display and a liquid crystal display using the image signal processing apparatus according to the embodiment of the present invention shown in FIG.
52 is an image signal processing device according to the present invention realized as a chip semiconductor integrated circuit. Reference numeral 50 denotes an MPU that controls the entire system, and specifies conversion data using a palette RAM for the image signal processing device 52. 51 is a display controller, which is an MPU
, and supplies a pixel clock 61, a horizontal synchronization signal 62, a vertical synchronization signal 63, and a pixel address 64 to the 52 image signal processing devices. The image signal processing device 52 supplies the CRT display 54 with an analog RGB signal 69 and a delayed horizontal synchronization signal 68 and vertical synchronization signal 67 within the image signal processing device. Also,
The image signal processing device outputs 66 pixel clocks to 53 liquid crystal displays or plasma display interface devices, and synchronizes with this output clock.
It supplies digital G data 65, horizontal synchronization signal 68, and vertical synchronization signal 67. and the liquid crystal display or plasma display interface device shall be 55
drives a liquid crystal or plasma display. In the same figure, 56, 57, 58, 59, 60 are 98 in FIG.
This is a code corresponding to 97, 94.95, and 96. According to FIGS. 4 and 6, the liquid crystal display or plasma display performs gradation display in which each pixel displays shading according to the value of the 6-bit G color data, but the present invention is not limited to this.
As shown in Figure (b), the upper few bits of RGB color data may be outputted one by one. In this case, the liquid crystal display displays color at each pixel. Note that the number of bits of color data output from the image signal processing device is not limited to the embodiment, and the larger the number, the more gradation or multicolor display becomes possible. Incidentally, the specific configuration of the timing generator shown in FIG. 2 127 and FIG. 4 1 is shown in FIG. 7. 170 is an inverter, which inputs the pixel clock from the outside of 171. This 171 is the clock shown in FIG. 5(a). 172 is the clock of FIG. 2 128 and FIG. 4 24, and is shown in FIG. 5(b). 173 is the clock of FIG. 2 136 and FIG. 4 25, and is shown in FIG. 5(c).
As shown in FIG. 7, the input pixel clock is delayed in phase by an inverter and outputted to 102, further delayed in phase, and outputted to 103. In the embodiment of the present invention, a synchronizing signal is output from the device, but in order to apply it to a CRT display device that requires a blanking signal, a blanking signal can also be output using the same configuration as the synchronizing signal. It may also be output to a CRT display with a delay. Further, in the embodiment of the present invention, the image signal processing device includes a CRT.
Although a diagram is shown in which both a display and a liquid crystal display or a plasma display are connected, in actual use, either a CRT display, a liquid crystal display, or a plasma display is connected and used as a display device. Furthermore, liquid crystal or plasma displays are electronically luminescent (E-luminescent).
L) It may be a display. [Effect of the Invention J As described above, according to the present invention, display display data converted by a palette is not only output as a signal for display on a CRT display such as an analog RGB signal, but also output as a signal for display on a CRT display, such as an analog RGB signal. By supplying display data to the device, A/
Since the D converter and its control circuit are not required,
This has the effect that a system that displays both a CRT display and a liquid crystal display or a plasma display can be constructed in a smaller size and at a lower cost than conventional systems. In addition, a clock signal corresponding to one pixel unit (pixel clock) and display display data are output in synchronization with the clock signal, and since they are output through a circuit formed on the same semiconductor substrate, temperature changes may occur. The amount of delay applied to the output is the same, and the phase difference between the two is stable and a constant phase relationship can be maintained at all times, so data can be captured accurately and easily on the liquid crystal or plasma interface device 1 side. is possible. Furthermore, conventionally, when displaying on a liquid crystal or plasma display. D/
The output of the A converter was A/D converted, but in the present invention, the output of the A converter is A/D converted.
Since it does not require a /D converter, it has the effect of enabling high-speed processing of display data displayed on a liquid crystal or plasma display. In addition, the same delay time as the delay time until the pixel address supplied by the display controller is converted into display display data and output is applied to display control signals such as horizontal and vertical synchronization signals supplied by the same display controller. Since the display data is output after the data is stored, the relationship between the display control signal and the display display data is always stable, and it has the advantage of being able to supply stable, high-quality images free from disturbances such as jitter. Furthermore, if an image signal processing device such as the present invention is used to convert a CRT display system to a system that can also be displayed on a liquid crystal or plasma display, the display interface side will need to be This has the advantage that there is no need to consider timing issues, and the system can be easily constructed.
Figure. FIG. 2 is a block diagram showing a display system using an image signal processing device according to a second embodiment of the present invention. FIG. 3 is a block diagram showing a display system using an image signal processing device according to a third embodiment of the present invention. FIG. 4 is a block diagram showing a fourth embodiment of the present invention. FIG. 5 is a timing chart showing the operation of the image signal processing device of FIG. 4. FIG. 6 is a block diagram of a system for displaying a CRT display or a liquid crystal display using an image signal processing device according to an embodiment of the present invention. Figure 7 is a specific configuration diagram of the timing generator.
FIG. 8 is a block diagram showing a display system using a conventional image signal processing device. Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Kisaburo Suzuki (and 1 other person) Akira 1 Figure

Claims (4)

[Claims] (1) It is controlled by a display controller or a microprocessor, and has a palette that is a storage device that receives display data in units of pixels and converts the display data into display display data, and that outputs image signals for displaying the display. The output image signal processing device has a terminal for outputting the display display data converted by the palette as an image signal for displaying on a CRT display, and a terminal for outputting as an image signal for displaying on a flat display. An image signal processing device characterized by: (2) The device according to claim 1, further comprising a terminal for outputting a clock signal corresponding to one pixel, and outputting an image signal for displaying the flat display in synchronization with the clock signal. Image signal processing device. (3) (a) Horizontal synchronization signal circuit consisting of horizontal synchronization signal input terminal, horizontal synchronization signal delay circuit, and horizontal synchronization signal output terminal, (b) Vertical synchronization signal input terminal, vertical synchronization signal delay circuit, and vertical synchronization signal output (c) a blanking signal circuit consisting of a blanking signal input terminal, a blanking signal delay circuit, and a blanking signal output terminal; 2. The image signal processing device according to claim 1, having a delay time equal to the time required to convert an input into image data for display on a display. (4) The image signal processing device according to claim 1, 2 or 3, wherein the image signal processing device is integrated on the same semiconductor substrate.