JP2013156323A - Display control device and electronic apparatus using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display control device that can control a display device such that the display device performs predetermined display and prevent abnormality of a display screen even when image data and clock signals fail to be supplied from an outside.SOLUTION: A display control device includes: an image processing circuit for applying image processing to image data on the basis of a first clock signal when at least the image data and the first clock signal are supplied from an outside; an image pattern generating circuit for generating the image data representing a predetermined image pattern on the basis of a second clock signal when the second clock signal is supplied; and a selecting circuit that selects and outputs one of the image data output from the image processing circuit and the image data output from the image pattern generating circuit in accordance with a mode selection signal.

Description

  The present invention controls display devices including display panels such as LCD (Liquid Crystal Display) panels and organic EL (Electro-Luminescence) panels in electronic devices such as in-vehicle display devices and mobile phones. The present invention relates to a display control device. Furthermore, the present invention relates to an electronic device using such a display control device.

  For example, a display control device used in an in-vehicle display device is supplied with image data or a clock signal from a host CPU or the like, and controls the display device to perform various displays. However, when the operation of the host CPU is stopped, there is a possibility that image data and a clock signal are not supplied from the outside. In such a case, if nothing is displayed on the display device or the display screen becomes abnormal, the user is shaken.

  As a related technique, Patent Document 1 discloses an LCD controller that can maintain display contents up to that even if a microcomputer serving as a display data supply source fails. The LCD controller includes a data memory for temporarily storing display data supplied from the outside, a counter for counting pulse signals supplied from the outside, a conversion circuit for converting the count value of the counter into display data, and a data memory. A multiplexer for selecting one of the display data stored in the display data and the display data output from the conversion circuit, a driver for driving the LCD with the display data selected by the multiplexer, and an external supply And a switching circuit for switching the multiplexer according to the signal.

  According to Patent Document 1, when display data is normally supplied from the outside, the display data is displayed on the LCD, and when display data is not normally supplied from the outside, the display data is based on the count value of the counter. Thus, since the correct display data up to the previous time is displayed on the LCD, the inconvenience of displaying random data as in the conventional case can be solved.

  However, in order to display the correct display data up to immediately before on the LCD, a data memory for temporarily storing the display data supplied from the outside is required, which increases the cost. In addition, the correct display data up to immediately before may be inconsistent with the current situation.

Japanese Laid-Open Patent Publication No. 8-24061 (paragraphs 0006-0007, 0016, 0019)

  According to some aspects of the present invention, even when image data or a clock signal is not supplied from the outside, the display device can be controlled so as to perform a predetermined display, and display screen abnormality can be prevented. A control device can be provided, and an electronic device using such a display control device can be provided.

  In order to solve the above problems, a display control device according to one aspect of the present invention provides image data based on a first clock signal when at least the image data and the first clock signal are supplied from the outside. An image processing circuit that performs image processing on the image pattern generation circuit that generates image data representing a predetermined image pattern based on the second clock signal when the second clock signal is supplied; And a selection circuit that selects and outputs one of the image data output from the image processing circuit and the image data output from the image pattern generation circuit in accordance with the mode selection signal.

  Here, the display control device further includes a timing generation circuit that generates a vertical synchronization signal and a horizontal synchronization signal based on the second clock signal when the second clock signal is supplied, and the image processing circuit includes When the vertical synchronization signal and the horizontal synchronization signal are supplied from the outside together with the image data and the first clock signal, the image data subjected to the image processing is output together with the vertical synchronization signal and the horizontal synchronization signal, and the selection circuit includes: According to the mode selection signal, one of image data, vertical synchronization signal and horizontal synchronization signal output from the image processing circuit and image data, vertical synchronization signal and horizontal synchronization signal output from the timing generation circuit is selected and output. You may make it do.

  In that case, the display control device detects whether one of the first clock signal, the vertical synchronization signal, and the horizontal synchronization signal is supplied from the outside, and detects the first clock signal, the vertical synchronization signal, and When the one of the horizontal synchronization signals is supplied from the outside, a mode selection signal representing a first mode in which image data output from the image processing circuit is selected is generated, and the first clock signal and A clock signal for generating a mode selection signal representing a second mode in which image data output from the image pattern generation circuit is selected when one of the vertical synchronization signal and the horizontal synchronization signal is not supplied from the outside. A detection circuit may be further provided.

  Alternatively, the display control device detects the access from the host CPU, and when there is an access from the host CPU within a certain period, the display control device represents a first mode in which the image data output from the image processing circuit is selected. An access detection circuit that generates a selection signal and generates a mode selection signal representing a second mode in which image data output from the image pattern generation circuit is selected when there is no access beyond a certain period from the host CPU. Furthermore, you may make it comprise.

The display control device further includes a clock signal generation circuit that generates the second clock signal when the mode selection signal indicates the second mode and stops the operation when the mode selection signal indicates the first mode. You may make it comprise.
Furthermore, an electronic apparatus according to an aspect of the present invention includes any one of the display control devices described above.

  According to one aspect of the present invention, an image pattern generation circuit that generates image data representing a predetermined image pattern based on a second clock signal, a selection circuit that selects and outputs image data according to a mode selection signal, By providing the display device, it is possible to control the display device so as to perform a predetermined display even when image data or a clock signal is not supplied from the outside, thereby preventing an abnormality in the display screen.

1 is a block diagram of an electronic apparatus that uses a display control apparatus according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a timing generation circuit and an image pattern generation circuit shown in FIG. 1. The figure of the color bar produced | generated by the image pattern production | generation circuit shown in FIG. The block diagram of the electronic device using the display control apparatus which concerns on the 2nd Embodiment of this invention. FIG. 5 is a circuit diagram showing a configuration example of a clock signal detection circuit shown in FIG. The block diagram of the electronic device using the display control apparatus which concerns on the 3rd Embodiment of this invention. FIG. 7 is a circuit diagram showing a configuration example of an access detection circuit shown in FIG. 6.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
FIG. 1 is a block diagram showing a circuit configuration of an electronic apparatus using the display control apparatus according to the first embodiment of the present invention. This electronic device is an electronic device such as an in-vehicle display device or a mobile phone. In FIG. 1, only a portion related to image display is shown.

  As shown in FIG. 1, the electronic device includes a host CPU (central processing unit) 10, a clock signal generation circuit 20, a display control device 30, and a display device 40. The clock signal generation circuit 20 may be incorporated in the display control device 30.

  The host CPU 10 controls the operation of each unit in the electronic device. The display control device 30 is supplied with at least image data Vdata, a first clock signal (pixel clock signal) Pclk, and a mode selection signal Msel from the host CPU 10 or another external device, and controls and / or performs image display. Perform image processing. In the following description, it is assumed that the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync are also supplied from the host CPU 10 or another external device.

  Here, the timing at which the image data Vdata of each pixel is supplied is synchronized with the pulse included in the first clock signal Pclk. The image data Vdata may include three color components (for example, 8 bits for each component) of R (red), G (green), and B (blue) for each pixel.

  In preparation for a situation where the operation of the host CPU 10 or the like stops, the clock signal generation circuit 20 generates a second clock signal (sub clock signal) Sclk. Thereby, the display control device 30 receives the image data Vdata representing the predetermined image pattern, the vertical synchronization signal Vsync, and the horizontal synchronization signal Hsync based on the second clock signal Sclk supplied from the clock signal generation circuit 20. Can be generated.

  The display device 40 includes a display driver and a display panel such as an LCD panel or an organic EL panel, and is based on image data Vdata, a vertical synchronization signal Vsync, and a horizontal synchronization signal Hsync output from the display control device 30. To display the image.

  The display control device 30 includes a host interface (I / F) 31, a register block 32, an image processing circuit 33, multiplexers 34 and 37 as selection circuits, a timing generation circuit 35, and an image pattern generation circuit 36. Is included.

  The host interface 31 is used for connecting the host CPU 10. The host CPU 10 sets various parameters and threshold values used in image processing by the image processing circuit 33 in accordance with the operation of the operator. The host interface 31 communicates with the host CPU 10, receives various parameters and threshold values, and stores them in the register block 32.

  When the image data Vdata, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the first clock signal Pclk are supplied, the image processing circuit 33 applies the image data Vdata to the image data Vdata based on the first clock signal Pclk. To perform image processing.

  For example, the image processing circuit 33 calculates luminance data by adding the values of the three color components of the image data Vdata at a predetermined ratio, and generates a histogram (frequency distribution) of the luminance data in one or a plurality of frames. The image data Vdata is subjected to processing for changing the luminance in the next frame according to the result of the histogram.

  Alternatively, the image processing circuit 33 may perform noise reduction processing on the image data Vdata using the image data Vdata over a plurality of frames. When the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync are not supplied from an external device, the image processing circuit 33 may generate the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync.

  The mode selection signal Msel represents, for example, a first mode in which image data output from the image processing circuit 33 is selected when it is at a low level, and when it is at a high level, the image pattern generation circuit 36. 2 represents a second mode in which image data output from is selected.

  The multiplexer 34 selects one of the first clock signal Pclk and the second clock signal Sclk according to the mode selection signal Msel, and outputs the selected clock signal CLK. For example, the multiplexer 34 selects the first clock signal Pclk in the first mode in which the mode selection signal Msel is low level, and the second clock signal in the second mode in which the mode selection signal Msel is high level. Select Sclk.

  The timing generation circuit 35 generates a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync based on the clock signal CLK selected by the multiplexer 34, and outputs them together with the clock signal CLK.

  The image pattern generation circuit 36 generates image data representing a predetermined image pattern based on the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the clock signal CLK output from the timing generation circuit 35. Note that the timing generation circuit 35 and the image pattern generation circuit 36 are reset when the reset signal RST is activated.

  Here, the predetermined image pattern may be a simple pattern such as a color bar or a checkered pattern. In that case, since the image data can be generated without using a memory, the cost can be reduced. Alternatively, the predetermined image pattern may be a pattern including characters such as a logo representing a company name and a predetermined message. In that case, appropriate information can be provided to the user.

  The multiplexer 37, in accordance with the mode selection signal Msel, image data Vdata, vertical synchronization signal Vsync and horizontal synchronization signal Hsync output from the image processing circuit 33, and image data Vdata and vertical synchronization signal output from the image pattern generation circuit 36. One of Vsync and horizontal synchronization signal Hsync is selected and output to the display device 40. The clock signal CLK selected by the multiplexer 34 is also output to the display device 40.

  As described above, the clock signal CLK selected by the multiplexer 34 is also supplied to the timing generation circuit 35 and the image pattern generation circuit 36. Thereby, the timing generation circuit 35 and the image pattern generation circuit 36 operate based on the first clock signal Pclk in the first mode in which the mode selection signal Msel is at a low level, and the mode selection signal Msel is at a high level. In the second mode, the operation is performed based on the second clock signal Sclk.

  Therefore, even when the image data Vdata and the first clock signal Pclk are supplied from the host CPU 10 or another external device, if the mode selection signal Msel is set to the high level, the image data Vdata and the first clock signal Pclk are synchronized with the first clock signal Pclk. The predetermined image pattern generated in this manner can be displayed on the display device 40. Thereby, for example, the color bar can be displayed on the display device 40 and the image quality evaluation can be performed.

  Alternatively, the mode selection signal Msel is set to a low level when the first clock signal Pclk is supplied from an external device, and the mode selection signal Msel is set to a high level when the first clock signal Pclk is not supplied from the external device. Anyway.

  Accordingly, when the first clock signal Pclk is supplied from the external device, an image based on the image data output from the image processing circuit 33 is displayed on the display device 40. On the other hand, when the first clock signal Pclk is not supplied from the external device, an image based on the image data output from the image pattern generation circuit 36 is displayed on the display device 40. Since the clock signal CLK selected by the multiplexer 34 is also supplied to the host interface 31, the host interface 31 can operate even when the first clock signal Pclk is not supplied from an external device. is there.

  Instead, the mode selection signal Msel may be set to a low level when there is an access from the host CPU 10 within a certain period, and the mode selection signal Msel may be set to a high level when there is no access from the host CPU 10 beyond a certain period.

  As a result, when there is an access from the host CPU 10 within a certain period, an image based on the image data output from the image processing circuit 33 is displayed on the display device 40. On the other hand, when there is no access beyond a certain period from the host CPU 10, an image based on the image data output from the image pattern generation circuit 36 is displayed on the display device 40.

  FIG. 2 is a circuit diagram showing a configuration example of the timing generation circuit and the image pattern generation circuit shown in FIG. The timing generation circuit 35 includes counters 51 and 54, a horizontal synchronization signal generation circuit 52, inverting input NOR circuits 53 and 56, and a vertical synchronization signal generation circuit 55.

  The counter 51 is a counter for measuring the horizontal synchronization period. The counter 51 is synchronized with the pulse included in the clock signal CLK selected by the multiplexer 34 shown in FIG. 1 and has a 10-bit count value Ch [9: 0] is incremented. The horizontal synchronization signal generation circuit 52 compares the count value Ch [9: 0] output from the counter 51 with a predetermined value, thereby generating a horizontal synchronization signal Hsync that is activated to a low level when they match. Generate. Further, the horizontal synchronization signal generation circuit 52 generates a data enable signal DE that is activated to a high level during a period in which data is valid within one horizontal synchronization period.

  The inverting input NOR circuit 53 resets the counter 51 when the horizontal synchronization signal Hsync is activated to a low level or the reset signal RST is activated to a low level. At that time, the count value Ch [9: 0] becomes zero.

  The counter 54 is a counter for measuring the vertical synchronization period, and is a 10-bit count value in synchronization with the falling edge of the pulse included in the horizontal synchronization signal Hsync output from the horizontal synchronization signal generation circuit 52. Increment Cv [9: 0]. The vertical synchronization signal generation circuit 55 compares the count value Cv [9: 0] output from the counter 54 with a predetermined value, thereby generating a vertical synchronization signal Vsync that is activated to a low level when they match. Generate.

  The inverting input NOR circuit 56 resets the counter 54 when the vertical synchronization signal Vsync is activated to a low level or the reset signal RST is activated to a low level. At that time, the count value Cv [9: 0] becomes zero.

  The image pattern generation circuit 36 includes a counter 61, an inverting input NOR circuit 62, an image data storage unit 63, and a multiplexer 64. Here, a case where the image pattern generation circuit 36 generates an image pattern of a color bar will be described.

  The counter 61 is a counter for measuring a period (64 pixels) in which one bar included in the color bar lasts, and is included in the clock signal CLK selected by the multiplexer 34 shown in FIG. The 9-bit count value Cr [8: 0] is incremented in synchronization with the existing pulse. The inverting input NOR circuit 62 resets the counter 61 when the data enable signal DE is deactivated to a low level or the reset signal RST is activated to a low level. At that time, the count value Cr [8: 0] becomes zero.

  The storage unit 63 stores eight types of image data Color0 to Color7 that respectively represent the colors of the eight bars included in the color bar. The multiplexer 64 selects one of the eight types of image data Color0 to Color7 stored in the storage unit 63 in accordance with the upper 3 bits Cr [8: 6] of the count value Cr [8: 0]. For example, when Cr [8: 6] is “000”, the image data Color0 is selected, and when Cr [8: 6] is “001”, the image data Color1 is selected. The selected 24-bit image data Vdata [23: 0] is output to the multiplexer 37 shown in FIG.

  FIG. 3 is a diagram showing an image pattern of color bars generated by the image pattern generation circuit shown in FIG. This color bar includes eight bars each having a width corresponding to 64 pixels, and the colors of these bars correspond to eight types of image data Color0 to Color7 from the left to red, blue, green, Yellow, magenta, cyan, white and black.

  FIG. 4 is a block diagram showing a circuit configuration of an electronic apparatus using the display control apparatus according to the second embodiment of the present invention. In the display control device 30a according to the second embodiment shown in FIG. 4, a clock signal detection circuit 38 is added to the display control device 30 according to the first embodiment shown in FIG. 20 is built-in. The other points are the same as in the first embodiment.

  The clock signal detection circuit 38 detects whether or not the first clock signal Pclk is supplied from the external device to the display control device 30a, and when the first clock signal Pclk is supplied, the image processing circuit A mode selection signal Msel representing a first mode in which the image data output from 33 is selected is generated. On the other hand, the clock signal detection circuit 38 generates a mode selection signal Msel representing a second mode in which the image data output from the image pattern generation circuit 36 is selected when the first clock signal Pclk is not supplied. To do.

  When the first clock signal Pclk is not supplied from the external device, there is a high possibility that the image data Vdata is not supplied from the external device. Even if the image data Vdata is supplied from the external device, the image processing circuit 33 cannot receive the image data Vdata. Therefore, an appropriate mode can be selected by detecting whether or not the first clock signal Pclk is supplied.

  The mode selection signal Msel generated by the clock signal detection circuit 38 is also output to the clock signal generation circuit 20. The clock signal generation circuit 20 generates the second clock signal Sclk when the mode selection signal Msel indicates the second mode, and stops operation when the mode selection signal Msel indicates the first mode. Thereby, useless power consumption in the clock signal generation circuit 20 can be reduced.

  FIG. 5 is a circuit diagram showing a configuration example of the clock signal detection circuit shown in FIG. The clock signal detection circuit 38 includes a CR oscillation circuit 80 including a capacitor C1, a resistor R1, and inverters 81 and 82. The CR oscillation circuit 80 performs an oscillation operation and generates an oscillation signal OS1. The oscillation period of the CR oscillation circuit 80 is set to be sufficiently longer than the period of the first clock signal Pclk. Further, the clock signal detection circuit 38 includes an inverter 83, D flip-flops 84 to 86 and 89, an EXOR circuit 87, and an OR circuit 88.

  First, the host CPU 10 or the display control device 30a shown in FIG. 4 activates the reset signal RST to a low level for a certain period, and then deactivates the reset signal RST to a high level. As a result, the clock signal detection circuit 38 is reset, and the mode selection signal Msel output from the D flip-flop 89 becomes a low level representing the first mode.

  The inverter 83 and the D flip-flop 84 constitute a frequency dividing circuit, and when the reset signal RST is deactivated, the oscillation signal OS1 is frequency-divided and the frequency-divided signal DIV is output. The D flip-flops 85 and 86 sequentially latch the divided signal DIV in synchronization with the pulse included in the first clock signal Pclk.

  The EXOR circuit 87 obtains an exclusive OR of the frequency-divided signal DIV input to the D flip-flop 85 and the signal latched by the D flip-flop 86, and sets the output signal to a high level when they do not match. The output signal of the EXOR circuit 87 is supplied to the D flip-flop 89 via the OR circuit 88. The D flip-flop 89 outputs the mode selection signal Msel by latching the output signal of the EXOR circuit 87 in synchronization with the rising edge of the pulse included in the oscillation signal OS1.

  Here, when the first clock signal Pclk is supplied from an external device, the level of the frequency-divided signal DIV input to the D flip-flop 85 at the rising edge of the pulse included in the oscillation signal OS1 Since the level of the signal latched by the D flip-flop 86 is equal, the mode selection signal Msel is at a low level representing the first mode.

  On the other hand, when the first clock signal Pclk is not supplied, the level of the divided signal DIV input to the D flip-flop 85 and the D flip-flop 86 at the rising edge of the pulse included in the oscillation signal OS1. Therefore, the mode selection signal Msel is at a high level indicating the second mode.

  Since the mode selection signal Msel output from the D flip-flop 89 is also supplied to one input terminal of the OR circuit 88, once the mode selection signal Msel goes high, the output signal of the OR circuit 88 also goes high. Maintained. Therefore, the D flip-flop 89 maintains the mode selection signal Msel at a high level.

  As a modification of the second embodiment, instead of detecting whether or not the first clock signal Pclk is supplied, it is detected whether or not the vertical synchronization signal Vsync or the horizontal synchronization signal Hsync is supplied. good. In that case, instead of the clock signal detection circuit 38, a synchronization signal detection circuit for detecting whether the vertical synchronization signal Vsync or the horizontal synchronization signal Hsync is supplied from the external device to the display control device 30a is provided. However, the oscillation period of the CR oscillation circuit 80 is set to be sufficiently longer than the period of the vertical synchronization signal Vsync or the horizontal synchronization signal Hsync.

  When the vertical synchronization signal Vsync or the horizontal synchronization signal Hsync is not supplied from the external device, there is a high possibility that the image data Vdata is not supplied from the external device, so the supply of the vertical synchronization signal Vsync or the horizontal synchronization signal Hsync is not possible. By detecting the presence or absence, an appropriate mode can be selected.

  The synchronization signal detection circuit generates a mode selection signal Msel representing a first mode in which image data output from the image processing circuit 33 is selected when the vertical synchronization signal Vsync or the horizontal synchronization signal Hsync is supplied. . On the other hand, the synchronization signal detection circuit is a mode selection signal Msel representing a second mode in which image data output from the image pattern generation circuit 36 is selected when the vertical synchronization signal Vsync or the horizontal synchronization signal Hsync is not supplied. Is generated.

  FIG. 6 is a block diagram showing a circuit configuration of an electronic apparatus using the display control apparatus according to the third embodiment of the present invention. In the display control device 30b according to the third embodiment shown in FIG. 6, the clock signal detection circuit 38 is changed to the access detection circuit 39 compared to the display control device 30a according to the second embodiment shown in FIG. ing. The other points are the same as in the second embodiment.

  The access detection circuit 39 detects the access from the host CPU 10 and represents a first mode in which the image data output from the image processing circuit 33 is selected when there is an access from the host CPU 10 within a certain period. A selection signal Msel is generated. On the other hand, the access detection circuit 39 generates a mode selection signal Msel representing the second mode in which the image data output from the image pattern generation circuit 36 is selected when there is no access from the host CPU 10 for a certain period of time. .

  When there is no access from the host CPU 10, there is a high possibility that the image data Vdata is not supplied from the host CPU 10, so that an appropriate mode can be selected by detecting the presence or absence of access from the host CPU 10.

  The mode selection signal Msel generated by the access detection circuit 39 is also output to the clock signal generation circuit 20. The clock signal generation circuit 20 generates the second clock signal Sclk when the mode selection signal Msel indicates the second mode, and stops operation when the mode selection signal Msel indicates the first mode. Thereby, useless power consumption in the clock signal generation circuit 20 can be reduced.

  FIG. 7 is a circuit diagram showing a configuration example of the access detection circuit shown in FIG. The access detection circuit 39 includes a CR oscillation circuit 90 including a capacitor C2, a resistor R2, and inverters 91 and 92. The CR oscillation circuit 90 performs an oscillation operation and generates an oscillation signal OS2. The oscillation period of the CR oscillation circuit 90 is set to be longer than 1/103 of the access period from the host CPU 10. Further, the access detection circuit 39 includes an NOR circuit 93 with an inverting input, a counter 94, a WDT (watchdog timer) assert circuit 95, an OR circuit 96, and a D flip-flop 97.

  Normally, the host CPU 10 periodically accesses the host interface 31, and the host interface 31 activates an access signal to a low level in response to an access from the host CPU 10. In that case, the reset signal RST may be generated by the display control device 30b shown in FIG. Alternatively, the host CPU 10 may access the display control device 30b by periodically activating the reset signal RST to a low level.

  First, the reset signal RST is activated to a low level for a certain period, and then the reset signal RST is deactivated to a high level. As a result, the access detection circuit 39 is reset, and the mode selection signal Msel output from the D flip-flop 97 becomes a low level representing the first mode.

  When the reset signal RST is deactivated, the counter 94 increments the 10-bit count value C [9: 0] in synchronization with the rising edge of the pulse included in the oscillation signal OS2. Normally, since the host CPU 10 accesses before the count value C reaches the maximum value “1023”, the count value C returns to zero. However, if there is no access from the host CPU 10, the count value C is the maximum. The value is “1023”.

  The WDT assert circuit 95 compares the count value C output from the counter 94 with the maximum value “1023”, and maintains the output signal at the low level when the count value C is smaller than the maximum value “1023”. To do. On the other hand, when the count value C output from the counter 94 reaches the maximum value “1023”, the WDT assert circuit 95 activates the output signal to a high level.

  The output signal of the WDT assert circuit 95 is input to the D flip-flop 97 via the OR circuit 96. The D flip-flop 97 outputs the mode selection signal Msel by latching the output signal of the WDT assert circuit 95 in synchronization with the rising edge of the pulse included in the oscillation signal OS2.

  Since the mode selection signal Msel output from the D flip-flop 97 is also supplied to one input terminal of the OR circuit 96, once the mode selection signal Msel goes high, the output signal of the OR circuit 96 also goes high. Maintained. Therefore, the D flip-flop 97 maintains the mode selection signal Msel at a high level.

  DESCRIPTION OF SYMBOLS 10 ... Host CPU, 20 ... Clock signal generation circuit, 30, 30a, 30b ... Display control device, 31 ... Host interface, 32 ... Register block, 33 ... Image processing circuit, 34, 37 ... Multiplexer, 35 ... Timing generation circuit , 36 ... Image pattern generation circuit, 38 ... Clock signal detection circuit, 39 ... Access detection circuit, 40 ... Display device, 51, 54 ... Counter, 52 ... Horizontal synchronization signal generation circuit, 53, 56 ... NOR circuit, 55 ... Vertical Synchronous signal generation circuit, 61 ... counter, 62 ... NOR circuit, 63 ... image data storage unit, 64 ... multiplexer, 80 ... CR oscillation circuit, 81, 82 ... inverter, 83 ... inverter, 84-86, 89 ... D flip-flop 87, EXOR circuit, 88 ... OR circuit, 90 ... CR oscillation circuit, 91, 2 ... Inverter, 93 ... NOR circuit, 94 ... counter, 95 ... WDT asserted circuit, 96 ... OR circuit, 97 ... D flip-flop, C1, C2 ... capacitors, R1, R2 ... resistance

Claims (6)

An image processing circuit that performs image processing on image data based on the first clock signal when at least the image data and the first clock signal are supplied from the outside;
An image pattern generation circuit for generating image data representing a predetermined image pattern based on the second clock signal when the second clock signal is supplied;
A selection circuit for selecting and outputting one of the image data output from the image processing circuit and the image data output from the image pattern generation circuit in accordance with a mode selection signal;
A display control apparatus comprising: A timing generation circuit for generating a vertical synchronization signal and a horizontal synchronization signal based on the second clock signal when the second clock signal is supplied;
The image processing circuit outputs the image data subjected to the image processing together with the vertical synchronization signal and the horizontal synchronization signal when the vertical synchronization signal and the horizontal synchronization signal are supplied from the outside together with the image data and the first clock signal. ,
In accordance with the mode selection signal, the selection circuit includes the image data, the vertical synchronization signal and the horizontal synchronization signal output from the image processing circuit, and the image data, the vertical synchronization signal and the horizontal synchronization signal output from the timing generation circuit. Select one of the output
The display control apparatus according to claim 1.   It is detected whether one of the first clock signal, the vertical synchronization signal, and the horizontal synchronization signal is supplied from the outside, and the one of the first clock signal, the vertical synchronization signal, and the horizontal synchronization signal is detected. When externally supplied, a mode selection signal representing a first mode in which image data output from the image processing circuit is selected is generated, and the first clock signal, the vertical synchronization signal, and the horizontal synchronization signal A clock signal detection circuit for generating a mode selection signal representing a second mode in which the image data output from the image pattern generation circuit is selected when the one of them is not supplied from the outside; The display control apparatus according to claim 1 or 2.   A mode selection signal representing a first mode in which image data output from the image processing circuit is selected when access from the host CPU is detected and there is an access from the host CPU within a certain period of time is generated. And an access detection circuit for generating a mode selection signal representing a second mode in which image data output from the image pattern generation circuit is selected when there is no access from the host CPU for a certain period of time. The display control device according to claim 1 or 2.   The clock signal generation circuit further generates a second clock signal when the mode selection signal indicates the second mode and stops operation when the mode selection signal indicates the first mode. 4. The display control device according to 4.   The electronic device which comprises the display control apparatus of any one of Claims 1-5.