KR20170079338A - Gate draiver and display device having the same - Google Patents

Abstract

In the present invention, a shift register for generating a scan signal and an inverter for generating an emission signal share a plurality of clock signals, thereby reducing the clock signal wiring of the gate drive circuit. Therefore, the present invention has an effect of simplifying the wiring structure of the gate drive circuit and realizing a narrow bezel.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate driver circuit and a display device including the gate driver circuit.

The present invention relates to a gate driving circuit and a display device including the same.

2. Description of the Related Art [0002] With the development of information electronic devices for realizing high-resolution and high-quality images such as portable telephones (portable phones), notebooks, computers, and HDTVs, flat panel displays Devices are increasingly in demand. As such flat panel display devices, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED) and an organic light emitting diode (OLED) have been actively studied.

Among the flat panel display devices, the organic light emitting display device has advantages of high response speed, high luminous efficiency, high luminance and wide viewing angle by using a self-luminous element.

A general organic light emitting display includes a display panel including an organic light emitting element in each pixel, a data driving circuit for supplying data to the data line of the display panel, a gate driving circuit for supplying gate pulses to the gate line of the display panel, And a timing controller for controlling the data driving circuit and the gate driving circuit. The gate driving circuit sequentially supplies a scan signal and an emission signal to the gate lines in response to a gate control signal input from the timing controller. In the display panel, the transistor of the horizontal line is turned on by the scan signal, and the emission time of each pixel is determined through the emission signal.

A general gate driving circuit includes a shift register for generating a scan signal and an inverter for generating an emission signal, and may be configured as a GIP (Gate In Panel) at the edge of the display panel.

However, a general gate driving circuit includes the shift register and the inverter including four or more clock signals provided to the shift resist including a plurality of control signals, for example, a gate start pulse, and four or more clock signals provided to the inverter, There has been a problem that the area is increased due to the number of wirings by the signals. A general gate driver circuit has a problem that a bezel region of a display device is widened.

An object of the present invention is to provide a gate driving circuit and a display device including the same that can simplify the wiring structure of a gate driving circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gate driving circuit capable of realizing a narrow bezel by simplifying a wiring structure of a gate driving circuit and a display device including the same.

According to an aspect of the present invention, there is provided a gate driving circuit including a shift register for generating a scan signal and an inverter for generating an emission signal, . That is, the clock signal wiring of the gate drive circuit of the present invention can be reduced.

The embodiment has the effect of simplifying the wiring structure of the gate driving circuit and implementing a narrow bezel.

The display device according to the present invention can reduce the clock signal wiring of the gate driving circuit by sharing the clock signals by the shift register and the inverter.

Embodiments can simplify the clock signal wiring structure by a gate driver circuit having a shift register and an inverter sharing a clock signal. The embodiment can reduce at least eight clock wirings of a general gate drive circuit to five.

The embodiment has the effect of simplifying the wiring structure of the gate driving circuit and implementing a narrow bezel.

1 is a block diagram schematically showing a configuration of a display apparatus according to an embodiment of the present invention.
2 is a diagram showing a gate drive circuit of the embodiment.
3 is a diagram showing the configuration of the first stage of the gate drive circuit of the embodiment.
4 is a diagram showing the gate drive circuit input signal and output signal of the embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. To fully disclose the scope of the invention to a person skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

In the case where the word 'includes', 'having', 'done', etc. are used in this specification, other parts can be added unless '~ only' is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if a temporal posterior relationship is described by 'after', 'after', 'after', 'before', etc., 'May not be contiguous unless it is used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

FIG. 1 is a block diagram schematically showing a configuration of a display device according to an embodiment of the present invention, FIG. 2 is a view showing a gate drive circuit of the embodiment, and FIG. 3 is a cross- Fig.

As shown in FIGS. 1 to 3, the display device of the embodiment may be an organic light emitting diode (OLED), but is not limited thereto. For example, the display device may be a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), or an electrophoretic display (EPD).

The display device may include a display panel 2, a timing controller 8, a gate driving circuit 4, and a data driving circuit 6.

The display panel 2 may be divided into a display area and a non-display area. The display panel 2 includes a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm and a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm, And may include a pixel P arranged at every pixel. Here, the pixel P may include an organic light emitting device that emits light and a driving device that drives the organic light emitting device.

When the display panel 2 is a liquid crystal display panel including a liquid crystal layer, the liquid crystal display panel may include first and second transparent substrates facing each other and a liquid crystal layer between the first and second transparent substrates have. The liquid crystal display panel may include a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm and the plurality of gate lines G1 to Gn and the plurality of data lines D1 to Dm, A pixel electrode, and a storage capacitor, which are connected to the transistors, respectively.

The timing controller 8 arranges the RGB data (RGB) input from the outside in accordance with the size and resolution of the display panel 2, and supplies the aligned digital image data to the data driving circuit 6. The timing controller 8 controls the timing controller 8 using externally input synchronizing signals such as a dot clock DCLK, a data enable signal DE, a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, Generates the control signal GCS and the data control signal DCS and supplies them to the gate driving circuit 4 and the data driving circuit 6, respectively.

The data driving circuit 6 may be mounted in the display panel 2 by a COG (Chip on Glass) method. The data driving circuit 6 uses the source start pulse SSP and the source shift clock SSC in the data control signal to output digital image data input from the timing controller 8 To an analog data voltage. Then, in response to a source output enable (SOE) signal, a data voltage is supplied to each data line (D1 to Dm).

The gate driving circuit 4 may supply a scan signal and an emission signal to the gate lines G1 to Gn using the gate control signal GCS. The gate control signal is input to gate start pulses (GSP) and shift registers 41a, 41b, 41c, and 41d that indicate a start gate line from which a scan starts in one vertical period in which one screen is displayed, A gate shift clock (GSC) generated by a pulse width corresponding to the ON period of the transistor in the pixel P as a timing control signal for successively shifting the start pulse GSP, And a gate output enable (GOE) signal that indicates the output of the gate driver 4.

The gate drive circuit 4 of the embodiment can be mounted in the non-display area of the display panel 2 in a GIP (Gate In Panel) manner.

The gate drive circuit 4 of the embodiment may include a plurality of shift registers 41a, 41b, 41c and 41d and a plurality of inverters 43a, 43b, 43c and 43d. The plurality of inverters 43a, 43b, 43c, and 43d generate the scan signal SCAN1 using the gate control signal, and the plurality of inverters 43a, 43b, 43c, The scan signal EM1 can be generated. The plurality of shift registers 41a, 41b, 41c and 41d and the plurality of inverters 43a, 43b, 43c and 43d may share the first to fifth clock signals CLK1 to CLK5. In the embodiment, the plurality of shift registers 41a, 41b, 41c and 41d and the plurality of inverters 43a, 43b, 43c and 43d share the first to fifth clock signals CLK1 to CLK5, Can be reduced to five. The first to fifth clock signals CLK1 to CLK5 may have five phases. The plurality of shift registers 41a, 41b, 41c and 41d and the plurality of inverters 43a, 43b, 43c and 43d of the embodiment can share the first to fifth clock signals CLK1 to CLK5 of five phases . The gate driving circuit 4 may further include a gate start pulse input terminal VST and a gate start pulse input wiring to which a gate start pulse GSP provided to the first shift register 41a is inputted.

The embodiment includes a plurality of shift registers 41a, 41b, 41c and 41d sharing clock signals except for the gate start pulse GSP and a gate driving circuit 4 including a plurality of inverters 43a, 43b, 43c and 43d ) Structure, the wiring structure of the gate drive circuit (4) can be simplified by reducing the number of clock wirings from 8 to 5 than a general gate drive circuit.

The embodiment has the effect of simplifying the wiring structure of the gate drive circuit 4 and realizing a narrow bezel.

For example, the first shift register 41a is provided with a first clock signal CLK1, a third clock signal CLK3 and a fifth clock signal CLK5 at its clock terminal And the first inverter 43a can be provided with the second clock signal CLK2 at the clock terminal.

The first shift resists 41a may include first to ninth transistors T1 to T9 and a first driving capacitor CB1.

The first transistor T1 has a gate start pulse VST and a gate electrode connected to each other, a high potential voltage VDD and a drain electrode connected to each other, and a source electrode connected to a drain electrode of the second transistor T2.

A gate electrode of the second transistor T2 is connected to a clock terminal to which a fifth clock signal CLK5 is input. A drain electrode of the second transistor T2 is connected to a source electrode of the first transistor T1. And the source electrode is connected.

The third transistor T3 has a gate electrode connected to the QB1 node QB1, a drain electrode connected to the source electrode of the fourth transistor T4, and a source electrode connected to the low potential voltage VSS.

The fourth transistor T4 has a gate electrode connected to the high-potential voltage VDD, a source electrode connected to the drain electrode of the third transistor T3, a source electrode connected to the drain electrode of the second transistor T2, .

The fifth transistor T5 is connected to the gate electrode of the fifth transistor T5 through which the third clock signal CLK3 is supplied, the drain electrode of the fifth transistor T5 is connected to the high potential voltage VDD, and the source electrode of the fifth transistor T5 is connected to the QB1 node QB1 .

The sixth transistor T6 has a gate electrode connected to the gate start pulse VST, a drain electrode connected to the source electrode of the fifth transistor T5, and a source electrode connected to the low-potential voltage VSS.

The seventh transistor T7 has a gate electrode connected to the source electrode of the fourth transistor T4, a drain electrode connected to the QB1 node QB1, and a source electrode connected to the low potential VSS.

A gate electrode of the eighth transistor T8 is connected to the Q1 node Q1. A drain electrode of the eighth transistor T8 is connected to a terminal to which the first clock signal CLK1 is supplied. A scan signal SCAN1, And the output node Vout1 is connected to the source electrode. A first driving capacitor CB1 is disposed between the gate electrode and the source electrode.

In the ninth transistor T9, a gate electrode is connected to the QB1 node QB1, a drain electrode is connected to the source electrode of the eighth transistor T8, and a source electrode is connected to the low potential voltage VSS.

The first inverter 43a may include a 10th to 15th transistors T10 to T15 and a second driving capacitor CB2.

In the tenth transistor T10, a gate electrode is connected to a terminal to which the second clock signal CLK2 is supplied, a drain electrode is connected to the high-potential voltage VDD, and a source electrode is connected to the Q2 node Q2 .

In the eleventh transistor T11, a gate electrode is connected to the QB2 node QB2, a drain electrode is connected to the Q2 node Q2, and a source electrode is connected to the low potential voltage VSS.

The twelfth transistor T12 has a gate electrode connected to the emission signal EM1 output line, a drain electrode connected to the high potential voltage VDD, a source electrode of the fourteenth transistor T14, T15) is connected to the drain electrode of the transistor T15.

In the thirteenth transistor T13, a gate electrode is connected to the Q2 node Q2, a drain electrode is connected to the high potential voltage VDD, and a source electrode is connected to the emission signal EM1 output line Vout2 . A second driving capacitor CB2 is disposed between the gate electrode and the source electrode of the thirteenth transistor T13.

The 14th transistor T14 has a gate electrode connected to the QB2 node QB2, a drain electrode connected to the emission signal EM1 output line, and a source electrode connected to the source electrode of the 12th transistor T12 .

In the fifteenth transistor T15, a gate electrode is connected to the QB2 node QB2, a drain electrode is connected to the source electrode of the fourteenth transistor T14, and a source electrode is connected to the low potential voltage VSS.

4 is a diagram showing the gate drive circuit input signal and output signal of the embodiment.

2 to 4, in the gate driving circuit of the embodiment, the gate start pulse VST and the fifth clock signal CLK5 are synchronized with the first shift register 41a in the first stage STG1, The first and second transistors T1 and T2 are turned on and become high in the Q1 node Q1. Also, the QB1 node QB1 is in a low state.

In the next second period a2, when the first clock signal CLK1 is inputted, a high level is outputted to the output node Vout, and the Q1 node Q1 is bootstrapped by the first driving capacitor CB1. (Bootstrapping). The first inverter 43a is turned on to the output node Vout to turn on the fourteenth transistor T14 so that the emission signal EM1 is in a low state. At this time, the eleventh transistor T11 is turned on and the thirteenth transistor T13 is turned off.

In the next third period a3, when the second clock signal CLK2 is input, the thirteenth transistor T13 is turned on and the emission signal EM1 becomes high. Thereafter, the first clock signal CLK1 is input and the emission signal EM1 becomes low.

In the next fourth period a4, when the third clock signal CLK3 is input to the first shift register 41a, the third transistor T3 and the fifth transistor T5 are turned on and the QB1 node QB1 is turned on. Becomes High, and the Q1 node Q1 becomes Low. Thereafter, the second clock signal CLK2 is input and the emission signal EM1 becomes a high state.

Since the third clock signal CLK3 is input in the fifth period a5 and the QB1 node QB1 is in the high state, the emission signal EM1 is maintained in the high state.

In the embodiment, the plurality of shift registers 41a, 41b, 41c and 41d and the plurality of inverters 43a, 43b, 43c and 43d share the first to fifth clock signals CLK1 to CLK5, Can be reduced to five. The embodiment has a gate drive circuit structure including a plurality of shift registers 41a, 41b, 41c, and 41d and a plurality of inverters 43a, 43b, 43c, and 43d sharing clock signals except gate start pulses. The wiring structure of the gate drive circuit (4) can be simplified by reducing the number of clock wirings from 8 to 5 than the drive circuit.

The embodiment has the effect of simplifying the wiring structure of the gate drive circuit 4 and realizing a narrow bezel.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments can be combined and modified by other persons having ordinary skill in the art to which the embodiments belong. Accordingly, the contents of such combinations and modifications should be construed as being included in the scope of the embodiments.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. It can be seen that the modification and application of branches are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

4: Gate drive circuit
41a, 41b, 41c and 41d: a plurality of shift registers
43a, 43b, 43c, 43d:

Claims (6)

A plurality of clock signal lines;
A shift register for receiving a plurality of clock signals from the plurality of clock signal lines and generating a scan signal; And
And an inverter for receiving the plurality of clock signals and generating an emission signal,
Wherein the shift register and the inverter share a plurality of clock signals.
The method according to claim 1,
Further comprising a gate start pulse input terminal for providing a start timing signal of said shift register and an input wiring.
The method according to claim 1,
Wherein the plurality of clock signals have five phases.
A timing controller for generating a plurality of clock signals and a gate control signal;
A display panel having a plurality of pixels; And
A shift register for receiving a plurality of clock signal lines at an edge of the display panel and a plurality of clock signals from the plurality of clock signal lines and generating a scan signal, and an inverter for receiving the plurality of clock signals and generating an emission signal, A gate driving circuit including the gate driving circuit;
And the gate driver circuit shares the plurality of clock signals with the shift register and the inverter.
5. The method of claim 4,
And a gate start pulse input terminal for providing a start timing signal of the shift register and an input wiring.
5. The method of claim 4,
Wherein the plurality of clock signals have five phases.

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