KR20190057641A - Clock signals and Gate drive circuit using the same - Google Patents

Abstract

The present invention relates to a clock signal which makes each pulse output unit share a clock signal when one stage has two pulse output units, and to a gate driving circuit using the same. In order to prevent activation periods from overlapping, the clock signal, during each deactivation period of clock signals for a first pulse output unit on n (n is a natural number) adds clock signals for a second pulse output unit on n. For the gate driving circuit using the same has a plurality of stages, and each stage has first and second pulse output units, clock signals on n (n is a natural number) are shared by the first and second output units of each stage, and n numbers of stages are grouped as one such that clock signals applied to the first and second output units of each stage are changed. Since first and second pulse output units of each stage can share clock signals, the number of clock signals is reduced and thus, clock signal lines are reduced.

Description

[0001] The present invention relates to a clock signal and a gate drive circuit using the same,

The present invention relates to a gate driving circuit in which one stage includes two pulse output sections, and the two pulse outputs of each stage are configured to configure clock signals so that they can share a clock signal, To a gate driving circuit for driving a clock signal supplied thereto in a switched manner.

As an information-oriented society develops and various portable electronic devices such as a mobile communication terminal and a notebook computer develop, a demand for a flat panel display device that can be applied to the portable electronic device is gradually increasing.

As such a flat panel display device, a liquid crystal display (LCD) using liquid crystal and an OLED display using an organic light emitting diode (OLED) are used.

Such flat panel display devices include a display panel having a plurality of gate lines and a plurality of data lines for displaying an image, and a driving circuit for driving the display panel.

A display panel of the liquid crystal display device among the display devices includes a thin film transistor array substrate on which a thin film transistor array is formed on a glass substrate, a color filter array substrate on which a color filter array is formed, And a liquid crystal layer filled between the array substrate and the color filter array substrate.

The thin film transistor array substrate includes a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction perpendicular to the first direction, And one sub pixel region (Pixel P) is defined by each data line. One thin film transistor and a pixel electrode are formed in one sub pixel region (P).

In the display panel of such a liquid crystal display device, a voltage is applied to an electric field generating electrode (pixel electrode and common electrode) to generate an electric field in the liquid crystal layer, and the arrangement state of the liquid crystal molecules in the liquid crystal layer is adjusted by the electric field, The image is displayed by controlling the polarization.

In the display panel of the OLED display device among the above-described display devices, a plurality of gate lines and a plurality of data lines intersect to define sub-pixels, and each sub-pixel includes an anode and a cathode, And a pixel circuit for independently driving the OLED.

The pixel circuit may be variously configured, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges the capacitor with a data voltage in response to a scan pulse. The driving TFT controls the amount of current supplied to the OLED according to the data voltage charged in the capacitor to control the amount of light emitted from the OLED.

The display panel for a display device is defined as a non-active area (NA) that is a peripheral area of the display area AA and a display area (AA) that provides an image to the user.

The driving circuit for driving the display panel may further include: a gate driving circuit for sequentially supplying gate pulses (or scan pulses) to the plurality of gate lines of the display panel; And a timing controller for supplying video data and various control signals to the gate driving circuit and the data driving circuit, and the like.

The gate driving circuit may be constituted by at least one gate drive IC, but it is preferable that in the process of forming the sub-pixel and the plurality of signal lines (gate lines and data lines) of the display panel, Region can be formed simultaneously.

In other words, a gate-in-panel (hereinafter referred to as " GIP ") method of directly driving the gate driving circuit to the display panel is applied.

The gate driving circuit includes a plurality of stages which are equal to or greater than the number of gate lines in order to sequentially supply scan pulses to the respective gate lines (scan lines), and the plurality of stages are connected to each other in a dependent manner.

In other words, a gate-in-panel (hereinafter referred to as " GIP ") method of directly driving the gate driver to the display panel is applied. In addition, the plurality of gate lines correspond to GIP at a ratio of 1: 1.

However, as the flat panel display device becomes a high-resolution, narrow bezel, it is required that one stage output two or more pulses.

That is, each stage includes two outputs for receiving a clock signal, a gate start signal, a gate high voltage, and a gate low voltage applied from the timing controller and generating one sense pulse and one scan pulse.

FIG. 2 is a diagram illustrating a clock pulse applied to each stage. FIG. 3 is a circuit diagram of a first and a second gate driving circuit, Lt; / RTI > is a waveform diagram of the second clock pulses.

As shown in Fig. 1, the nth stage ST (n) of the conventional gate driving circuit includes a carry pulse SE (n-3) output from the previous stage and a carry pulse SE a Q node controller 12 for controlling the first node Q by means of an inverter 13 (n + 3), and an inverter 13 for inverting the voltage of the first node Q and applying the inverted voltage to the second node Qb And a clock signal SCCLK (n) of the plurality of first pulse output clock signals SCCLK1 to SCCLK2 to generate a first clock signal SCCLK (n) according to the voltages of the first node Q and the second node Qb, A first pulse output section 15 for outputting a first clock signal SCLK (n) and a second pulse output section 15 for outputting a second clock signal SCLK (n) A second pulse output section 16 for outputting a second pulse SE (n) according to the voltage of the node Q and the second node Qb; Ripple of the two pulse output sections 15 and 16, Ground is formed by a first node, a reset unit 11 for resetting the first node (Q) by a stabilizing portion 14, a start signal (VST).

As described above, each stage of the conventional gate driving circuit constructed as described above includes the first and second pulse output sections 15 and 16, and the first pulse output section 15 of each stage is supplied with the first pulse The output clock signals SCCLK1 to SCLK8 are applied and the second pulse output clock signals SECLK1 to SECK8 are applied to the second pulse output portion 16 of each stage.

2 and 3, one of the 8-phase first pulse output clock signals SCCLK1 to 8 and the second pulse output clock signal SECLK1 (Line 1, Line 2, To 8 are applied. Therefore, a gate drive circuit having two pulse outputs of eight phases required 16 pulse signals.

Therefore, in the conventional flat panel display device, the number of clock signals increases as the number of clock signals increases toward a high resolution and a large model. Therefore, the bezel size, the PCP area, the number of pins of the connector and the level shifter The number of pins is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a gate driving circuit having first and second pulse output sections in which the first and second pulse output sections share a clock signal, It is possible to reduce the bezel size of the display panel, the PCP area, the number of pins of the connector, and the number of pins of the level shifter, and a gate driving circuit using the flap signal can be provided It has its purpose.

According to another aspect of the present invention, there is provided a clock signal generator comprising: a plurality of stages each having a first and a second pulse output section, and the clock signals for the second pulse output section of the n-phase are added so that the activation periods do not overlap with each other in the inactivation period of each of the clock signals for the first pulse output section on the n-th (n is a natural number).

That is, when the clock signals are four-phase, the first clock signal includes a first clock signal for the first pulse output section and a third clock signal for the second pulse output section, and the second clock signal includes a second clock signal for the second pulse output section Wherein the third clock signal includes a third clock signal for the first pulse output section and a first clock signal for the second pulse output section and the fourth clock signal comprises a third clock signal for the first pulse output section and a fourth clock signal for the second pulse output section, And a fourth clock signal for one pulse output section and a second clock signal for the second pulse output section.

The first clock signal includes a first clock signal for the first pulse output section and a fourth clock signal for the second pulse output section and the second clock signal includes a second clock signal for the first pulse output section And a fifth clock signal for the second pulse output section, wherein the third clock signal comprises a third clock signal for the first pulse output section and a sixth clock signal for the second pulse output section, the fourth clock signal comprises a first pulse A fourth clock signal for the output section and a first clock signal for the second pulse output section, the fifth clock signal includes a fifth clock signal for the first pulse output section and a second clock signal for the second pulse output section, The clock signal includes a sixth clock signal for the first pulse output section and a third clock signal for the second pulse output section.

The first clock signal includes a first clock signal for the first pulse output section and a fifth clock signal for the second pulse output section and the second clock signal includes a second clock signal for the first pulse output section, And a sixth clock signal for the second pulse output section, the third clock signal comprises a third clock signal for the first pulse output section and a seventh clock signal for the second pulse output section, the fourth clock signal comprises a first pulse A fifth clock signal for the first pulse output section and a first clock signal for the second pulse output section, and the sixth clock signal for the sixth pulse output section includes the fifth clock signal for the first pulse output section and the fourth clock signal for the second pulse output section, The clock signal includes a sixth clock signal for the first pulse output section and a second clock signal for the second pulse output section and the seventh clock signal includes a seventh clock signal for the first pulse output section and a third clock signal for the second pulse output section And the eighth clock signal includes And the eighth clock signal for one pulse output section and the fourth clock signal for the second pulse output section.

The first clock signal includes a first clock signal for the first pulse output section and a seventh clock signal for the second pulse output section and the second clock signal includes a second clock signal for the first pulse output section And the eighth clock signal for the second pulse output section, the third clock signal includes a third clock signal for the first pulse output section and a ninth clock signal for the second pulse output section, and the fourth clock signal includes a first pulse A fifth clock signal for the first pulse output section and an eleventh clock signal for the second pulse output section, and a sixth clock signal for the sixth pulse output section, The clock signal includes a sixth clock signal for the first pulse output section and a twelfth clock signal for the second pulse output section and the seventh clock signal includes a seventh clock signal for the first pulse output section and a first clock signal for the second pulse output section And the eighth clock signal includes The eighth clock signal for the first pulse output section and the second clock signal for the second pulse output section, the ninth clock signal includes a ninth clock signal for the first pulse output section and a third clock signal for the second pulse output section , The tenth clock signal includes a tenth clock signal for the first pulse output section and a fourth clock signal for the second pulse output section and the eleventh clock signal includes the eleventh clock signal for the first pulse output section and the eleventh clock signal for the second pulse output section 5 clock signal, and the twelfth clock signal includes a twelfth clock signal for the first pulse output section and a sixth clock signal for the second pulse output section.

According to another aspect of the present invention, there is provided a gate driving circuit comprising a plurality of stages, each stage including first and second pulse output sections, wherein n (n is a natural number) The clock signals on the first and second stages are shared by the first and second output sections of the stage and the n stages are grouped so that the clock signal applied to the first and second output sections of each stage is changed .

That is, when four-phase clock signals are shared by the first and second output sections of each stage, the first pulse output section and the second pulse output section of the (4n-3) The second clock signal and the fourth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (4n-2) -th stage, and the first clock signal and the fourth clock signal of the (4n-1) A third clock signal and a first clock signal are respectively applied to the pulse output unit and the second pulse output unit, and a fourth clock signal and a second clock signal are respectively applied to the first pulse output unit and the second pulse output unit of the (4n) A clock signal is applied.

6 are shared by the first and second output sections of each stage, the first pulse output section and the second pulse output section of the (6n-5) -th stage are respectively supplied with a first clock signal and a fourth clock signal The second clock signal and the fifth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (6n-4) th stage, and the first pulse output of the (6n-3) A third clock signal and a sixth clock signal are applied to the first and second pulse output sections, respectively, and a fourth clock signal and a first clock signal are respectively applied to the first pulse output section and the second pulse output section of the (6n-2) A fifth clock signal and a second clock signal are respectively applied to the first pulse output section and the second pulse output section of the (6n-1) -th stage, and the first pulse output of the (6n) And a sixth clock signal and a third clock signal are respectively supplied to the negative and second pulse output sections .

If the 8-phase clock signals are shared by the first and second output portions of each stage, the first pulse output portion and the second pulse output portion of the (8n-7) th stage are respectively supplied with the first clock signal and the fifth clock signal The second clock signal and the sixth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (8n-6) th stage, and the first pulse output of the (8n-5) A third clock signal and a seventh clock signal are respectively applied to the first and second pulse output sections, and a fourth clock signal and a seventh clock signal are respectively applied to the first pulse output section and the second pulse output section of the (8n-4) And a fifth clock signal and a first clock signal are respectively applied to the first pulse output section and the second pulse output section of the (8n-3) th stage, and the first clock signal and the first clock signal of the (8n-2) The pulse output unit and the second pulse output unit are respectively supplied with a sixth clock signal and a second clock signal The seventh clock signal and the third clock signal are respectively applied to the first pulse output section and the second pulse output section of the (8n-1) -th stage, and the first pulse output section of the (8n) And the eighth clock signal and the fourth clock signal are respectively applied to the two pulse output sections.

Th stage is shared by the first and second output portions of each stage, the first pulse output portion and the second pulse output portion of the (12n-11) th stage are respectively supplied with the first clock signal and the seventh clock signal The second clock signal and the eighth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (12n-10) th stage, and the first pulse output of the (12n-9) The third clock signal and the ninth clock signal are respectively applied to the first and second pulse output sections and the first pulse output section and the second pulse output section of the (12n-8) Th clock signal is applied to the first pulse output section and the second pulse output section of the (12n-7) th stage, and the fifth clock signal and the eleventh clock signal are applied to the (12n-6) The first pulse signal and the second pulse signal have a sixth clock signal and a twelfth And a seventh clock signal and a first clock signal are respectively applied to the first pulse output section and the second pulse output section of the (12n-5) th stage, and the first clock signal and the first clock signal of the (12n-4) The eighth clock signal and the second clock signal are respectively applied to the pulse output unit and the second pulse output unit, and the ninth clock signal and the ninth clock signal are respectively applied to the first pulse output unit and the second pulse output unit of the (12n-3) A third clock signal is applied, a tenth clock signal and a fourth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (12n-2) th stage, The 12th clock signal and the 5th clock signal are respectively applied to the first pulse output unit and the second pulse output unit, and the 12th clock signal and the 12th clock signal are respectively applied to the 1st pulse output unit and the 2nd pulse output unit of the (12n) The sixth clock signal is applied.

The clock signals according to the present invention having the above-described characteristics and the gate driving circuit using the clock signals have the following effects.

That is, since the first and second pulse outputs of each stage can share the clock signal, the number of clock signals decreases and the clock signal line decreases.

Therefore, the present invention can implement a narrow bezel, reduce the PCP area, the number of pins of the connector, the number of pins of the level shifter, and the like.

1 is a block diagram of an n-th stage ST (n) of a conventional gate driving circuit
FIG. 2 is a diagram illustrating the first and second clock signals applied to each stage of the related art.
3 is a waveform diagram of first and second clock signals applied to each stage of the related art.
4 is a view schematically showing a flat display device according to the present invention.
5 is a stage configuration diagram of a gate driving circuit according to the present invention
6 is an equivalent circuit diagram of a sub-pixel of a display panel according to an embodiment of the present invention.
7 is an explanatory diagram of clock signals applied to each stage according to an embodiment of the present invention.
8 is an explanatory diagram of a clock signal applied to the first stage according to the embodiment of the present invention
FIG. 9 is an explanatory diagram of a clock signal applied to the fifth stage according to the embodiment of the present invention
10 is a waveform diagram of pulse signals shared by the first and second pulse output sections of each stage according to the first embodiment of the present invention
11 is a timing chart of the first clock signal line CLK1 among the clock signal lines according to the embodiment of the present invention.
12 shows waveforms of pulse signals applied to the scan lines and the sensing lines when normally driving sub-pixels as shown in FIG. 6 using the clock signals CLK1 to CLK8 shown in FIG.
13 is a graph showing waveforms of pulse signals shared by the first and second pulse output sections of each stage according to the second embodiment of the present invention and the characteristics of the driving TFTs of the sub- The waveforms of the pulse signals to be applied to the respective scan lines and the sensing lines at the time of sensing
FIG. 14 is a waveform diagram of four-phase clock signals CLK1-CLK4 shared by the first and second pulse output sections of each stage according to the third embodiment of the present invention.
15 is a waveform diagram of six-phase clock signals CLK1-CLK6 shared by the first and second pulse output sections of each stage according to the fourth embodiment of the present invention.
16 is a waveform diagram of 12-phase clock signals CLK1-CLK12 shared by the first and second pulse output sections of each stage according to the fifth embodiment of the present invention.

A clock signal and a gate driving circuit using the same according to the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 4 is a configuration diagram briefly showing a flat panel display device according to the present invention, and FIG. 5 is a stage configuration diagram of a gate drive circuit according to the present invention.

A flat panel display device according to the present invention includes a display panel 1, a gate driving circuit 2, a data driving circuit 3, and a timing controller 4 as shown in Fig.

The display panel 1 is provided with a plurality of gate lines GL and a plurality of data lines DL and a plurality of gate lines GL and a plurality of data lines DL in a crossing region of the plurality of gate lines GL and the plurality of data lines DL. A plurality of sub-pixels P are arranged in a matrix form. The plurality of subpixels P are arranged to receive an image corresponding to a video signal (data voltage) supplied from the plurality of data lines DL in response to a scan pulse G supplied from the gate lines GL Display.

 The gate driving circuit 2 is a GIP (gate in panel) type gate driver and is disposed in a non-display region of the display panel 2 and has a plurality of stages as described with reference to FIG.

Each stage is provided with a first pulse output section 15 and a second pulse output section 16, as described with reference to Fig.

The gate driving circuit 2 sequentially supplies a scan pulse (gate driving signal, Vgout) to each gate line GL in accordance with a plurality of gate control signals GCS provided from the timing controller 4. [

The plurality of gate control signals GCS includes a plurality of clock signals CLK1-8 having different phases, a gate start signal VST indicating the start of driving of the gate driving circuit 2, a gate high voltage VGH) and a gate low voltage (VGL).

The data driving circuit 3 converts the digital image data RGB input from the timing controller 4 into an analog data voltage using a reference gamma voltage and outputs the converted analog data voltage to the plurality of data lines DL. The data driving circuit 3 is controlled in accordance with a plurality of data control signals DCS provided from the timing controller 4. [

The timing controller 4 arranges image data RGB input from the outside in accordance with the size and resolution of the display panel 1 and supplies the image data RGB to the data driving circuit 3. The timing controller 4 receives the synchronization signals SYNC input from the outside such as a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, A plurality of gate control signals GCS and a plurality of data control signals DCS are generated and supplied to the gate driving circuit 2 and the data driving circuit 3, respectively.

6 is an equivalent circuit diagram of a sub-pixel when the display panel 1 is an OLED display panel according to an embodiment of the present invention.

Each sub-pixel of the OLED display panel according to the present invention includes an organic light emitting diode (OLED) and a pixel circuit for driving the organic light emitting diode, as shown in FIG.

The pixel circuit includes first and second switching TFTs T1 and T2, a storage capacitor Cst, and a driving TFT DT.

The first switching TFT Tl charges the storage capacitor Cst with a data voltage in response to a scan pulse Scan. The driving TFT DT controls the amount of current supplied to the OLED according to the data voltage charged in the storage capacitor Cst to control the amount of light emitted from the OLED. The second switching TFT T2 senses the threshold voltage and the mobility of the driving TFT DT in response to the sensing pulse Sense.

The organic light emitting diode OLED may include a first electrode (e.g., an anode electrode or a cathode electrode), an organic light emitting layer, and a second electrode (e.g., a cathode electrode or an anode electrode).

 The storage capacitor Cst is electrically connected between a gate electrode of the driving TFT DT and a source electrode so that a data voltage corresponding to a video signal voltage or a voltage corresponding thereto is applied for one frame time I can keep it.

As shown in FIG. 6, each sub-pixel is driven by a scan pulse (Scan) and a sensing pulse (Sense).

1, the first pulse output section 15 of each stage outputs a scan pulse (Scan), and the second pulse output section (16) outputs a scan pulse (Scan), and when the gate drive circuit (2) And outputs a sensing pulse Sense.

FIG. 7 is an explanatory diagram of clock signals applied to each stage according to an embodiment of the present invention, FIG. 8 is an explanatory diagram of a clock signal applied to a first stage according to an embodiment of the present invention, 5 is an explanatory diagram of a clock signal applied to the fifth stage according to the embodiment.

As described above, each stage of the gate drive circuit 2 according to the present invention includes a first pulse output section 15 for outputting a scan pulse (Scan), a second pulse output section 16 for outputting a sense pulse Sense As shown in Fig. 7, the first and second pulse output sections 15 and 16 of each stage share a plurality of clock signals CLK1-8 having different phases. In FIGS. 7 to 9, the eight-phase clock signal CLK1-8 will be described as an example.

7, the first pulse signal CLK1 is applied to the first pulse output section 15 of the first stage and the second pulse output section 16 of the first stage is supplied with the fifth clock signal CLK1. The signal CLK5 is applied.

The second clock signal CLK2 is applied to the first pulse output section 15 of the second stage and the sixth clock signal CLK6 is applied to the second pulse output section 16 of the second stage.

The third clock signal CLK3 is applied to the first pulse output section 15 of the third stage and the seventh clock signal CLK7 is applied to the second pulse output section 16 of the third stage.

The fourth clock signal CLK4 is applied to the first pulse output section 15 of the fourth stage and the eighth clock signal CLK8 is applied to the second pulse output section 16 of the fourth stage.

Conversely, the fifth clock signal CLK5 is applied to the first pulse output section 15 of the fifth stage and the first clock signal CLK1 is applied to the second pulse output section 16 of the fifth stage.

The sixth clock signal CLK6 is applied to the first pulse output section 15 of the sixth stage and the second clock signal CLK2 is applied to the second pulse output section 16 of the sixth stage.

The seventh clock signal CLK7 is applied to the first pulse output section 15 of the seventh stage and the third clock signal CLK3 is applied to the second pulse output section 16 of the seventh stage.

The eighth clock signal CLK8 is applied to the first pulse output section 15 of the eighth stage and the fourth clock signal CLK4 is applied to the second pulse output section 16 of the eighth stage.

In this manner, clock signals are applied in the same manner as the first to fourth stages of the ninth to twelfth stages, and clock signals are applied to the thirteenth to sixteenth stages in the same manner as the fifth to eighth stages .

FIG. 8 illustrates a clock signal applied to the first pulse output section 15 and the second pulse output section 16 of the first stage, FIG. 9 illustrates the first pulse output section 15 and the second pulse output section 16 of the fifth stage, The clock signal applied to the second pulse output section 16 is described.

8 and 9, a first clock signal CLK1 is applied to the first pulse output section 15 of the first stage and a fifth clock signal CLK1 is applied to the second pulse output section 16 of the first stage. A fifth clock signal CLK5 is applied to the first pulse output section 15 of the fifth stage and a first clock signal CLK5 is applied to the second pulse output section 16 of the fifth stage, CLK1 is applied.

That is, when the 8-phase clock signal CLK1-8 is shared by the first and second output sections 15 and 16 of each stage, the eight stages are grouped into the first and second output sections 15 , 16 are changed.

That is, the first clock signal CLK1 and the fifth clock signal CLK5 are applied to the first pulse output section 15 and the second pulse output section 16 of the (8n-7) The second clock signal CLK2 and the sixth clock signal CLK6 are applied to the first pulse output section 15 and the second pulse output section 16 of the The third pulse signal CLK3 and the seventh clock signal CLK7 are respectively applied to the first pulse output section 15 and the second pulse output section 16 of the stage and the first The fourth pulse signal CLK4 and the eighth clock signal CLK8 are applied to the pulse output section 15 and the second pulse output section 16, respectively.

A fifth clock signal CLK5 and a first clock signal CLK1 are applied to the first pulse output section 15 and the second pulse output section 16 of the (8n-3) The sixth clock signal CLK6 and the second clock signal CLK2 are applied to the first pulse output section 15 and the second pulse output section 16 of the The seventh clock signal CLK7 and the third clock signal CLK3 are respectively applied to the first pulse output section 15 and the second pulse output section 16 of the stage and the first pulse output The eighth clock signal CLK8 and the fourth clock signal CLK4 are applied to the first pulse output unit 15 and the second pulse output unit 16, respectively.

Here, n is a natural number.

10 is a waveform diagram of pulse signals shared by the first and second pulse output units of each stage according to the first embodiment of the present invention.

The first through eighth clock signals CLK1, CLK2, CLK3, CLK4, CLK5 and CLK6, which are eight-phase clock signals CLK1-8 shared by the first and second pulse output sections 15, 16 of each stage, , CLK7, and CLK8 will now be described.

In FIG. 10, the first to eighth clock signals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7 and CLK8 correspond to the first and second pulse output sections 15, 16 and the clock signals SECLK1 to SECLK8 are the second pulse output clock signals to be applied to the second pulse output portion 16 of the conventional stage.

The first to eighth clock signals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7 and CLK8 are input to the first pulse output section 15 of the conventional stage, (Low level period) of the first pulse output clock signals SCCLK1 to SCCLK8 are applied to the second pulse output section 16 of the conventional stage so that the activation periods do not overlap with each other And the second pulse output clock signals SECLK1 to SECLK2 are added.

That is, the conventional second pulse output fifth clock signal SECLK5 is added to the inactivation period (low level period) of the conventional first pulse output first clock signal SCCLK1 to generate the first clock signal CLK1 ).

The second clock signal (SECLK6) for the second pulse output is added to the inactivation period (low level period) of the conventional first pulse output second clock signal SCCLK2 to generate the second clock signal CLK2 according to the present invention will be.

The third clock signal CLK3 according to the present invention is generated by adding the second pulse output seventh clock signal SECLK7 to the inactive period (low level period) of the conventional first pulse output third clock signal SCCLK3 will be.

The eighth clock signal SECLK8 for the second pulse output is added to the inactivation period (low level period) of the conventional first pulse output fourth clock signal SCCLK4 to generate the fourth clock signal CLK4 according to the present invention will be.

The second pulse output first clock signal SECLK1 is added to the inactive period (low level period) of the conventional first pulse output fifth clock signal SCCLK5 to generate the fifth clock signal CLK5 according to the present invention will be.

The second pulse output second clock signal SECLK2 is added to the inactive period (low level period) of the conventional first pulse output sixth clock signal SCCLK6 to generate the sixth clock signal CLK6 according to the present invention will be.

The seventh clock signal (CLK7) according to the present invention is generated by adding the second pulse output third clock signal (SECLK3) to the inactivation period (low level period) of the seventh conventional clock signal SCCLK7 will be.

The eighth clock signal CLK8 according to the present invention is generated by adding the second pulse output fourth clock signal SECLK4 to the inactive period (low level period) of the conventional first pulse output eighth clock signal SCCLK8 will be.

Accordingly, the first clock signal CLK1 according to the present invention includes the first clock signal SCCLK1 for the first pulse output and the fifth clock signal SECLK5 for the second pulse output, and the second clock signal CLK2 includes a first pulse output second clock signal SCCLK2 and a second pulse output sixth clock signal SECLK6 and a third clock signal CLK3 according to the present invention includes a first pulse output third clock signal (SCCLK3) and a seventh clock signal (SECLK7) for the second pulse output. The fourth clock signal (CLK4) according to the present invention includes the first pulse output fourth clock signal (SCCLK4) and the second pulse output eighth clock And the fifth clock signal CLK5 according to the present invention includes the first pulse signal SCCLK5 for the first pulse output and the first clock signal SECLK1 for the second pulse output, The sixth clock signal CLK6 corresponding to the first pulse output SCCLK6 and the second pulse output second clock < RTI ID = 0.0 > And the seventh clock signal CLK7 according to the present invention includes the seventh clock signal SCCLK7 for the first pulse output and the third clock signal SECLK3 for the second pulse output, The eighth clock signal CLK8 includes the first pulse output eighth clock signal SCCLK8 and the second pulse output fourth clock signal SECLK4.

In FIG. 10, the clock signal indicated by red is the clock signal for the second pulse output unit 16, and the clock signal indicated by black is the clock signal for the first pulse output unit 15. [

In FIG. 10, the clock signals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8 adjacent to each other are superimposed on each other, but the present invention is not limited thereto and may not overlap.

11 is a timing diagram of a first clock signal line CLK1 among clock signal lines according to an embodiment of the present invention.

11, a clock for the first pulse output section 15 of the first stage (first gate line), a second pulse output section 16 of the fifth stage are connected to the first clock signal line CLK1, The clock for the first pulse output section 15 of the ninth stage, the clock signal for the second pulse output section 16 of the thirteenth stage, and so on.

Although not shown in the drawing, the second clock signal line CLK2 is supplied with the clock for the first pulse output section 15 of the second stage, the clock for the second pulse output section 16 of the sixth stage, The clock for one pulse output section 15, the clock signal for the second pulse output section 16 of the 14th stage,...

FIG. 12 is a waveform diagram of pulse signals applied to the scan lines and the sensing lines when normally driving sub-pixels as shown in FIG. 6 using the clock signals CLK1 to CLK8 shown in FIG.

Here, the normal driving means driving in a state in which the characteristics (threshold voltage and mobility) of the driving TFT DT shown in Fig. 6 are not sensed.

10 and 11, each of the clock signals CLK1 to CLK8 includes a clock signal for the first pulse output section 15 and a clock signal for the second pulse output section 16, 7 to 9, when the 8-phase clock signal CLK1-8 is shared by the first and second output sections 15 and 16 of each stage, the eight stages are grouped into a first group The clock signal for the first pulse output section 15 and the clock signal for the second pulse output section 16 are supplied to the first output section 15 and the second output section 16 in the actual operation, Is applied to the output unit (15) and the second pulse output unit (16), the sub-pixel can be driven accurately.

13 is a graph showing waveforms of pulse signals shared by the first and second pulse output sections of each stage according to the second embodiment of the present invention and the characteristics of the driving TFTs of the sub- Fig. 8 is a waveform diagram of a pulse signal applied to each scan line and a sensing line when sensing the signal line.

The first to eighth clock signals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7 and CLK8 are input to the first and second pulse output sections 15, 16 of each stage according to the second embodiment of the present invention, Are shared clock signals.

The first pulse output clock signals applied to the first pulse output section 15 of each stage are shown in black and the second pulse output clock signals applied to the second pulse output section 16 of each stage are shown in blue Respectively.

As described with reference to FIG. 10, based on the first pulse output clock signals applied to the first pulse output section 15 of each stage, the first pulse output section 15 of each stage The second pulse output clock signals applied to the second pulse output section 16 are added to the inactive periods (low level periods) of the output clock signals so that the activation periods do not overlap with each other, (CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8) shared by the first and second pulse output sections 15,

That is, the fifth clock signal (SECLK5) for the second pulse output is added to the inactive period (low level period) of the first pulse output first clock signal to generate the first clock signal CLK1 according to the second embodiment of the present invention .

The second clock signal CLK2 according to the second embodiment of the present invention is generated by adding the second pulse outputting sixth clock signal to the inactivation period (low level period) of the first pulse output second clock signal.

The third clock signal CLK3 according to the second embodiment of the present invention is generated by adding the seventh clock signal for the second pulse output to the inactivation period (low level period) of the third pulse signal for the first pulse output.

The eighth clock signal for the second pulse output is added to the inactive period (low level period) of the fourth pulse signal for the first pulse output to generate the fourth clock signal CLK4 according to the second embodiment of the present invention.

The fifth pulse signal CLK5 according to the present invention is generated by adding the second pulse output first clock signal to the inactivation period (low level period) of the fifth pulse signal for the first pulse output.

The second pulse output second clock signal is added to the inactive period (low level period) of the sixth pulse signal for the first pulse output to generate the sixth clock signal CLK6 according to the second embodiment of the present invention.

The third clock signal for the second pulse output is added to the inactive period (low level period) of the seventh clock signal for the first pulse output to generate the seventh clock signal CLK7 according to the second embodiment of the present invention.

And the eighth clock signal (CLK8) according to the second embodiment of the present invention is generated by adding a fourth clock signal for the second pulse output in the inactivation period (low level period) of the eighth clock signal for the first pulse output.

The clock signals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8 according to the second embodiment of the present invention also include a first pulse output clock signal and a second pulse output clock signal, respectively .

However, the first pulse output clock signal according to the second embodiment of the present invention has two high-level states in the activation period in order to sense the characteristics (threshold voltage and mobility) of the driving TFT.

Accordingly, the first clock signal CLK1 according to the second embodiment of the present invention includes the first clock signal for the first pulse output and the fifth clock signal for the second pulse output, and the first clock signal CLK1 according to the second embodiment of the present invention The second clock signal CLK2 includes a first pulse output second clock signal SCCLK2 and a second pulse output sixth clock signal SECLK6 and outputs the third clock signal CLK3 according to the second embodiment of the present invention. The fourth clock signal CLK4 according to the second embodiment of the present invention includes the first pulse output third clock signal SCCLK3 and the second pulse output seventh clock signal SECLK7, The fifth clock signal CLK5 according to the second embodiment of the present invention includes the fifth clock signal SCCLK4 for the first pulse output and the fourth clock signal SCCLK4 for the second pulse output. And a first clock signal (SECLK1) for a second pulse output. The sixth clock signal (SECLK1) according to the second embodiment of the present invention CLK6 includes the first pulse output sixth clock signal SCCLK6 and the second pulse output second clock signal SECLK2 and the seventh clock signal CLK7 according to the second embodiment of the present invention includes the first pulse The seventh clock signal SCCLK7 for output and the third clock signal SECLK3 for the second pulse output, and the eighth clock signal CLK8 according to the second embodiment of the present invention includes the eighth clock signal for the first pulse output SCCLK8 and a second pulse output fourth clock signal SECLK4.

In FIG. 13, the clock signal indicated by blue is the clock signal for the second pulse output section 16, and the clock signal indicated by black is the clock signal for the first pulse output section 15.

In FIG. 13, the clock signals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8 adjacent to each other are superimposed on each other, but the present invention is not limited thereto and may not overlap.

The clock signals according to the second embodiment of the present invention may also be configured such that the clock signals CLK1-8 of eight phases are supplied to the first and second output sections 15 and 16 of each stage In the case of sharing, the clock signal applied to the first and second output units 15 and 16 is changed by using eight stages as one group.

That is, the first clock signal CLK1 and the fifth clock signal CLK5 are applied to the first pulse output section 15 and the second pulse output section 16 of the (8n-7) The second clock signal CLK2 and the sixth clock signal CLK6 are applied to the first pulse output section 15 and the second pulse output section 16 of the The third pulse signal CLK3 and the seventh clock signal CLK7 are respectively applied to the first pulse output section 15 and the second pulse output section 16 of the stage and the first The fourth pulse signal CLK4 and the eighth clock signal CLK8 are applied to the pulse output section 15 and the second pulse output section 16, respectively.

A fifth clock signal CLK5 and a first clock signal CLK1 are applied to the first pulse output section 15 and the second pulse output section 16 of the (8n-3) The sixth clock signal CLK6 and the second clock signal CLK2 are applied to the first pulse output section 15 and the second pulse output section 16 of the The seventh clock signal CLK7 and the third clock signal CLK3 are respectively applied to the first pulse output section 15 and the second pulse output section 16 of the stage and the first pulse output The eighth clock signal CLK8 and the fourth clock signal CLK4 are applied to the first pulse output unit 15 and the second pulse output unit 16, respectively.

Here, n is a natural number.

Each of the clock signals CLK1 to CLK8 according to the second embodiment of the present invention includes a clock signal for the first pulse output section 15 and a clock signal for the second pulse output section 16, 9, when the eight-phase clock signal CLK1-8 is shared by the first and second output sections 15 and 16 of each stage, the eight stages are grouped into a first group and a second group, The clock signal for the first pulse output section 15 and the clock signal for the second pulse output section 16 are supplied to the first pulse output section 15 and the second pulse output section 16, respectively, (15) and the second pulse output section (16), so that the sub-pixel can be driven accurately.

13, when the clock signal for the second pulse output section 16 and the clock signal for the first pulse output section 15 are simultaneously set to the high level, the characteristics of the driving TFT shown in Fig. 6 (threshold voltage and mobility ) Is initialized and when the clock signal for the first pulse output section 15 goes to the low level state in a state where the clock signal for the second pulse output section 16 is kept at the high level, And mobility). When the clock signal for the first pulse output section 15 is again set to the high level state in a state where the clock signal for the second pulse output section 16 is maintained at the high level, recovery is performed.

7 to 13 illustrate the 8-phase clock signals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8. However, the present invention is not limited thereto, and four-, six-, The clock signals are also generated in the manner as described in FIGS. 10 and 13, and are applied to the first and second output portions 15 and 16 of each stage in the manner as described in FIGS. It can be driven by applying a clock signal.

FIG. 14 is a waveform diagram of four-phase clock signals CLK1-CLK4 shared by the first and second pulse output sections of each stage according to the third embodiment of the present invention, and FIG. Phase clock signals CLK1-CLK6 shared by the first and second pulse output sections of each stage according to the fifth embodiment of the present invention, and Fig. 16 is a waveform diagram of the first and second Phase clock signals CLK1 to CLK12 shared by the pulse output unit.

When the clock signals shared by the first and second pulse output sections of each stage are the four-phase clock signals (CLK1 to CLK4), as shown in Fig. 14, the first pulse output section 15 of each stage The second pulse output clock signal applied to the second pulse output section 16 is added to the inactive period (low level period) of the applied first pulse output clock signal to generate the 4-phase clock signal according to the third embodiment of the present invention CLK1, CLK2, CLK3, and CLK4.

That is, the third clock signal for the second pulse output is added to the inactive period (low level period) of the first pulse output first clock signal to generate the first clock signal CLK1 according to the third embodiment of the present invention .

And the second pulse output fourth clock signal is added to the inactive period (low level period) of the first pulse output second clock signal to generate the second clock signal CLK2 according to the third embodiment of the present invention.

The third clock signal CLK3 according to the third embodiment of the present invention is generated by adding the second pulse output first clock signal to the inactivation period (low level period) of the third pulse signal for the first pulse output.

The second pulse output second clock signal is added to the inactive period (low level period) of the first pulse output fourth clock signal to generate the fourth clock signal CLK4 according to the third embodiment of the present invention.

Therefore, the first clock signal CLK1 according to the third embodiment of the present invention includes the first clock signal for the first pulse output and the third clock signal for the second pulse output, and the first clock signal CLK1 according to the third embodiment of the present invention The second clock signal CLK2 includes a first pulse output second clock signal and a second pulse output fourth clock signal. The third clock signal CLK3 according to the third embodiment of the present invention includes a first pulse output 3 clock signal and a first clock signal for a second pulse output, and the fourth clock signal CLK4 according to the third embodiment of the present invention includes a fourth clock signal for first pulse output and a second clock signal for second pulse output .

The clock signal shown in blue in FIG. 14 is the clock signal for the second pulse output section 16, and the clock signal indicated in black is the clock signal for the first pulse output section 15. FIG.

When the first and second output sections 15 and 16 of each stage share the four-phase clock signals CLK1, CLK2, CLK3 and CLK4 according to the third embodiment of the present invention, The clock signals applied to the first and second output units 15 and 16 are changed.

That is, the first clock signal CLK1 and the third clock signal CLK3 are respectively applied to the first pulse output section 15 and the second pulse output section 16 of the (4n-3) The second clock signal CLK2 and the fourth clock signal CLK4 are respectively applied to the first pulse output section 15 and the second pulse output section 16 of the The third pulse signal CLK3 and the first clock signal CLK1 are respectively applied to the first pulse output section 15 and the second pulse output section 16 of the stage and the first pulse output The fourth pulse signal CLK4 and the second clock signal CLK2 are applied to the first pulse output section 15 and the second pulse output section 16, respectively.

Here, n is a natural number.

On the other hand, when the clock signal shared by the first and second pulse output sections of each stage is the six-phase clock signals CLK1 to CLK6, as shown in Fig. 15, the first pulse output section 15 The second pulse output clock signal applied to the second pulse output section 16 in the inactivation period (low level period) of the first pulse outputting clock signal applied to the sixth pulse output section 16 is added to the sixth pulse output clock signal, Clock signals CLK1, CLK2, CLK3, CLK4, CLK5, and CLK6).

That is, the fourth clock signal for the second pulse output is added to the inactive period (low level period) of the first pulse output first clock signal to generate the first clock signal CLK1 according to the fourth embodiment of the present invention .

The second clock signal CLK2 according to the fourth embodiment of the present invention is generated by adding the second pulse-output fifth clock signal to the inactivation period (low-level period) of the first pulse-output second clock signal.

The third clock signal CLK3 according to the fourth embodiment of the present invention is generated by adding the second pulse outputting sixth clock signal to the inactivation period (low level period) of the third pulse signal for the first pulse output.

The fourth pulse signal CLK4 according to the fourth embodiment of the present invention is generated by adding the second pulse output first clock signal to the inactivation period (low level period) of the fourth pulse signal for the first pulse output.

The second pulse output second clock signal is added to the inactive period (low level period) of the first pulse output fifth clock signal to generate the fifth clock signal CLK5 according to the fourth embodiment of the present invention.

The third clock signal for the second pulse output is added to the inactive period (low level period) of the sixth pulse signal for the first pulse output to generate the sixth clock signal CLK6 according to the fourth embodiment of the present invention.

Therefore, the first clock signal CLK1 according to the fourth embodiment of the present invention includes the first clock signal for the first pulse output and the fourth clock signal for the second pulse output, and the first clock signal CLK1 according to the fourth embodiment of the present invention The second clock signal CLK2 includes a first clock signal for a first pulse output and a fifth clock signal for a second pulse output and the third clock signal CLK3 according to the fourth embodiment of the present invention includes a first pulse output And the fourth clock signal CLK4 according to the fourth embodiment of the present invention includes a fourth clock signal for the first pulse output and a first clock signal for the second pulse output The fifth clock signal CLK5 according to the fourth embodiment of the present invention includes a fifth clock signal for the first pulse output and a second clock signal for the second pulse output, The sixth clock signal CLK6 according to the second clock signal CLK6 is supplied to the first And a third output clock signal.

In FIG. 15, the clock signal indicated by blue is the clock signal for the second pulse output section 16, and the clock signal indicated by black is the clock signal for the first pulse output section 15.

When the first and second output sections 15 and 16 of each stage share the clock signals CLK1, CLK2, CLK3, CLK4, CLK5 and CLK6 of the six phases according to the fourth embodiment of the present invention, So that the clock signals applied to the first and second output units 15 and 16 are changed.

That is, the first clock signal CLK1 and the fourth clock signal CLK4 are respectively applied to the first pulse output section 15 and the second pulse output section 16 of the (6n-5) The second clock signal CLK2 and the fifth clock signal CLK5 are applied to the first pulse output section 15 and the second pulse output section 16 of the The third pulse signal CLK3 and the sixth clock signal CLK6 are respectively applied to the first pulse output section 15 and the second pulse output section 16 of the stage and the first pulse output section 15 and the second pulse output section 16 of the (6n-2) The fourth pulse signal CLK4 and the first clock signal CLK1 are applied to the pulse output section 15 and the second pulse output section 16 respectively and the first pulse output section (6n-1) Th stage and the second pulse output section 16 are applied with the fifth clock signal CLK5 and the second clock signal CLK2 respectively and the first pulse output section 15 and the second pulse output section 16 of the (6n) The output section 16 receives the sixth clock signal CLK6 and 3 is applied to the clock signal (CLK3).

Here, n is a natural number.

On the other hand, when the clock signal shared by the first and second pulse output sections of each stage is the 12-phase clock signals (CLK1 to CLK12), the first pulse output section 15 of each stage, The second pulse output clock signal applied to the second pulse output section 16 in the inactivation period (low level period) of the first pulse output clock signal applied to the first pulse output terminal 16 is added to the 12-phase clock according to the fifth embodiment of the present invention (CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8, CLK9, CLK10, CLK11, CLK12).

That is, the first clock signal CLK1 according to the fifth embodiment of the present invention is generated by adding the second pulse output seventh clock signal to the inactivation period (low level period) of the first pulse output first clock signal .

The eighth clock signal for the second pulse output is added to the inactive period (low level period) of the first pulse output second clock signal to generate the second clock signal CLK2 according to the fifth embodiment of the present invention.

And the ninth clock signal for the second pulse output is added to the inactive period (low level period) of the third pulse signal for the first pulse output to generate the third clock signal CLK3 according to the fifth embodiment of the present invention.

A tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth tenth.

The fifth clock signal CLK5 according to the fifth embodiment of the present invention is generated by adding the eleventh clock signal for the second pulse output in the inactivation period (low level period) of the fifth pulse signal for the first pulse output.

The sixth clock signal CLK6 according to the fifth embodiment of the present invention is generated by adding the twelfth clock signal for the second pulse output in the inactivation period (low level period) of the sixth pulse signal for the first pulse output.

The first pulse output first clock signal is added to the inactivation period (low level period) of the seventh clock signal for the first pulse output to generate the seventh clock signal CLK7 according to the fifth embodiment of the present invention.

The second pulse output second clock signal is added to the inactivation period (low level period) of the eighth clock signal for the first pulse output to generate the eighth clock signal CLK8 according to the fifth embodiment of the present invention.

The third pulse signal for the second pulse output is added to the inactivation period (low level period) of the ninth clock signal for the first pulse output to generate the ninth clock signal CLK9 according to the fifth embodiment of the present invention.

The fourth pulse signal for the second pulse output is added to the inactive period (low level period) of the tenth pulse signal for the first pulse output to generate the tenth clock signal CLK10 according to the fifth embodiment of the present invention.

The fifth clock signal for the second pulse output is added to the inactive period (low level period) of the eleventh clock signal for the first pulse output to generate the eleventh clock signal CLK11 according to the fifth embodiment of the present invention.

The sixth clock signal for the second pulse output is added to the inactivation period (low level period) of the twelfth clock signal for the first pulse output to generate the twelfth clock signal CLK12 according to the fifth embodiment of the present invention.

Therefore, the first clock signal CLK1 according to the fifth embodiment of the present invention includes the first clock signal for the first pulse output and the seventh clock signal for the second pulse output, and the first clock signal CLK1 according to the fifth embodiment of the present invention The second clock signal CLK2 includes a first pulse output second clock signal and a second pulse output eighth clock signal and the third clock signal CLK3 according to the fifth embodiment of the present invention includes a first pulse output 3 clock signal and the ninth clock signal for the second pulse output, and the fourth clock signal CLK4 according to the fifth embodiment of the present invention includes the fourth clock signal for the first pulse output and the tenth clock signal for the second pulse output And the fifth clock signal CLK5 according to the fifth embodiment of the present invention includes the fifth clock signal for the first pulse output and the eleventh clock signal for the second pulse output. In the fifth embodiment of the present invention, The sixth clock signal CLK6 according to the second clock signal CLK6 is supplied to the first And a twelfth clock signal for outputting the clock signal.

The seventh clock signal CLK7 according to the fifth embodiment of the present invention includes the seventh clock signal for the first pulse output and the first clock signal for the second pulse output, The ninth clock signal CLK9 according to the fifth embodiment of the present invention includes the ninth clock signal CLK8 for the first pulse output and the ninth clock signal CLK9 for the second pulse output, Signal and a third clock signal for a second pulse output, and the tenth clock signal CLK10 according to the fifth embodiment of the present invention includes a tenth clock signal for the first pulse output and a fourth clock signal for the second pulse output And the eleventh clock signal CLK11 according to the fifth embodiment of the present invention includes the eleventh clock signal for the first pulse output and the fifth clock signal for the second pulse output, The 12-clock signal (CLK12) is generated by the 12th clock signal for the first pulse output and the 2 < And a sixth clock signal for output.

16 is a clock signal for the second pulse output unit 16, and a clock signal indicated in black is a clock signal for the first pulse output unit 15. In FIG.

The 12-phase clock signals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8, CLK9, CLK10, CLK11, CLK12 according to the fifth embodiment of the present invention are applied to the first and second output sections 15, and 16, the clock signals applied to the first and second output units 15 and 16 are changed into one group of twelve stages.

That is, the first clock signal (CLK1) and the seventh clock signal (CLK7) are applied to the first pulse output section (15) and the second pulse output section (16) of the (12n-11) The second pulse signal CLK2 and the eighth clock signal CLK8 are applied to the first pulse output section 15 and the second pulse output section 16 of the The third pulse signal CLK3 and the ninth clock signal CLK9 are respectively applied to the first pulse output section 15 and the second pulse output section 16 of the stage and the first pulse output section 15 and the second pulse output section 16 of the (12n-8) The fourth pulse signal CLK4 and the tenth clock signal CLK10 are respectively applied to the pulse output section 15 and the second pulse output section 16 and the first pulse output section 16b of the (12n-7) The first pulse output section 15 and the second pulse output section 16 of the (12n-6) th stage are applied with the fifth clock signal CLK5 and the eleventh clock signal CLK11 respectively, The 2-pulse output section 16 is supplied with a sixth clock signal (CLK6) and 12 is applied to the clock signal (CLK12).

The seventh clock signal CLK7 and the first clock signal CLK1 are applied to the first pulse output section 15 and the second pulse output section 16 of the (12n-5) th stage, Th stage is applied to the first pulse output section 15 and the second pulse output section 16 of the (n-1) th stage, the eighth clock signal CLK8 and the second clock signal CLK2 are applied to the The ninth clock signal CLK9 and the third clock signal CLK3 are respectively applied to the first pulse output section 15 and the second pulse output section 16 and the first pulse output of the (12n-2) The first pulse output section 15 of the (12n-1) -th stage is supplied with the tenth and tenth clock signals CLK10 and CLK4 respectively to the first pulse output section 15 and the second pulse output section 16, Th stage and the second pulse output section 16 are applied with the eleventh clock signal CLK11 and the fifth clock signal CLK5 respectively and the first pulse output section 15 and the second pulse output section 15 of the (12n) (16) are respectively provided with a twelfth clock signal (CLK12) And the sixth clock signal CLK6 are applied.

Here, n is a natural number.

In the above description, the first pulse output section 15 outputs the scan pulse and the second pulse output section 16 outputs the sensing pulse. However, the present invention is not limited to this, and the second pulse output section 16 Another scan pulse can be output and a carry pulse can be output.

Thus, since the first and second pulse outputs of each stage can share a clock signal, the number of clock signals decreases and the number of clock signal lines decreases.

Therefore, the present invention can implement a narrow bezel, reduce the PCP area, the number of pins of the connector, the number of pins of the level shifter, and the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

1: display panel 2: gate driving circuit
3: Data driving circuit 4: Timing controller

Claims (10)

Each stage of the gate drive circuit has first and second pulse output sections and each of the clock signals for the first pulse output section on n (n is a natural number) is deactivated in order to allow the first and second pulse output sections to share Wherein the clock signal for the second pulse output of the n-phase is added so that the activation period does not overlap with the n-phase clock signal. The method according to claim 1,
When the clock signals for the first and second pulse output units are four-phase,
A first clock signal to which a third clock signal for the second pulse output unit is added in a deactivation period of the first clock signal for the first pulse output unit,
A second clock signal to which a fourth clock signal for the second pulse output unit is added in a deactivation period of the second clock signal for the first pulse output unit,
A third clock signal to which a first clock signal for a second pulse output section is added in a deactivation period of a third clock signal for the first pulse output section,
And a fourth clock signal (CLK4) to which a second clock signal for the second pulse output section is added in a deactivation period of the fourth clock signal for the first pulse output section. The method according to claim 1,
When the clock signals for the first and second pulse output units are six-phase,
A first clock signal to which a fourth clock signal for the second pulse output unit is added in a deactivation period of the first clock signal for the first pulse output unit,
A second clock signal to which a fifth clock signal for the second pulse output section is added in a deactivation period of the second clock signal for the first pulse output section,
A third clock signal to which a sixth clock signal for the second pulse output unit is added in a deactivation period of the third clock signal for the first pulse output unit,
A fourth clock signal to which the first clock signal for the second pulse output section is added in the inactivation period of the fourth clock signal for the first pulse output section,
A fifth clock signal to which a second clock signal for the second pulse output section is added in a deactivation period of the fifth clock signal for the first pulse output section,
A sixth clock signal having a sixth clock signal to which a third clock signal for a second pulse output unit is added in a deactivation period of the sixth clock signal for the first pulse output unit. The method according to claim 1,
When the clock signals for the first and second pulse output units are eight-phase,
A first clock signal to which a fifth clock signal for the second pulse output unit is added in a deactivation period of the first clock signal for the first pulse output unit,
A second clock signal to which a sixth clock signal for the second pulse output unit is added in a deactivation period of the second clock signal for the first pulse output unit,
A third clock signal to which a seventh clock signal for the second pulse output unit is added in a deactivation period of the third clock signal for the first pulse output unit,
A fourth clock signal to which an eighth clock signal for the second pulse output unit is added in a deactivation period of the fourth clock signal for the first pulse output unit,
A fifth clock signal to which a first clock signal for a second pulse output section is added in a deactivation period of a fifth clock signal for the first pulse output section,
A sixth clock signal to which a second clock signal for the second pulse output unit is added in a deactivation period of the sixth clock signal for the first pulse output unit,
A seventh clock signal to which a third clock signal for the second pulse output section is added in the inactivation period of the seventh clock signal for the first pulse output section,
An eighth clock signal having an eighth clock signal to which a fourth clock signal for the second pulse output unit is added in an inactivation period of the eighth clock signal for the first pulse output unit. The method according to claim 1,
When the clock signals for the first and second pulse output units are 12-phase,
A first clock signal to which a seventh clock signal for the second pulse output unit is added in a deactivation period of the first clock signal for the first pulse output unit,
A second clock signal to which an eighth clock signal for the second pulse output unit is added in a deactivation period of the second clock signal for the first pulse output unit,
A third clock signal to which a ninth clock signal for the second pulse output unit is added in a deactivation period of the third clock signal for the first pulse output unit,
A fourth clock signal to which a tenth clock signal for the second pulse output unit is added in a deactivation period of the fourth clock signal for the first pulse output unit,
A fifth clock signal to which an eleventh clock signal for the second pulse output unit is added in a deactivation period of the fifth clock signal for the first pulse output unit,
A sixth clock signal to which a twelfth clock signal for the second pulse output unit is added in a deactivation period of the sixth clock signal for the first pulse output unit,
A seventh clock signal to which the first clock signal for the second pulse output section is added in the inactivation period of the seventh clock signal for the first pulse output section,
An eighth clock signal to which the second clock signal for the second pulse output section is added in the inactivation period of the eighth clock signal for the first pulse output section,
A ninth clock signal to which the third clock signal for the second pulse output section is added in the inactivation period of the ninth clock signal for the first pulse output section,
A tenth clock signal to which a fourth clock signal for the second pulse output unit is added in a deactivation period of the tenth clock signal for the first pulse output unit,
An eleventh clock signal to which a fifth clock signal for the second pulse output unit is added in a deactivation period of the eleventh clock signal for the first pulse output unit,
And a twelfth clock signal having a twelfth clock signal to which a sixth clock signal for the second pulse output unit is added in a deactivation period of the twelfth clock signal for the first pulse output unit. A plurality of stages are obtained, and each stage includes a first pulse output section and a second pulse output section,
The clock signals on n (n is a natural number) are shared by the first and second output sections of each stage, and n stages are grouped so that the clock signal applied to the first and second output sections of each stage is The gate drive circuit is changed. The method according to claim 6,
If the four clock signals are shared by the first and second outputs of each stage,
The first clock signal and the third clock signal are respectively applied to the first pulse output unit and the second pulse output unit of the (4n-3) th stage,
The second clock signal and the fourth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (4n-2) th stage,
A third clock signal and a first clock signal are respectively applied to the first pulse output section and the second pulse output section of the (4n-1) -th stage,
And a fourth clock signal and a second clock signal are respectively applied to the first pulse output section and the second pulse output section of the (4n) th stage. The method according to claim 6,
If the clock signals on six are shared by the first and second outputs of each stage,
The first clock signal and the fourth clock signal are respectively applied to the first pulse output unit and the second pulse output unit of the (6n-5) th stage,
A second clock signal and a fifth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (6n-4) th stage,
A third clock signal and a sixth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (6n-3) th stage,
The fourth clock signal and the first clock signal are respectively applied to the first pulse output unit and the second pulse output unit of the (6n-2) th stage,
A fifth clock signal and a second clock signal are respectively applied to the first pulse output section and the second pulse output section of the (6n-1) -th stage,
And a sixth clock signal and a third clock signal are respectively applied to the first pulse output section and the second pulse output section of the (6n) th stage. The method according to claim 6,
If the eight clock signals are shared by the first and second outputs of each stage,
The first clock signal and the fifth clock signal are respectively applied to the first pulse output unit and the second pulse output unit of the (8n-7) th stage,
The second clock signal and the sixth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (8n-6) th stage,
A third clock signal and a seventh clock signal are respectively applied to the first pulse output section and the second pulse output section of the (8n-5) th stage,
The fourth clock signal and the eighth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (8n-4) th stage,
A fifth clock signal and a first clock signal are respectively applied to the first pulse output section and the second pulse output section of the (8n-3) th stage,
The sixth clock signal and the second clock signal are respectively applied to the first pulse output section and the second pulse output section of the (8n-2) th stage,
The seventh clock signal and the third clock signal are respectively applied to the first pulse output section and the second pulse output section of the (8n-1) th stage,
And the eighth clock signal and the fourth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (8n) th stage. The method according to claim 6,
If the 12 clock signals are shared by the first and second outputs of each stage,
A first clock signal and a seventh clock signal are respectively applied to the first pulse output section and the second pulse output section of the (12n-11) th stage,
The second clock signal and the eighth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (12n-10) th stage,
The third clock signal and the ninth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (12n-9) th stage,
The first pulse output unit and the second pulse output unit of the (12n-8) th stage) are respectively applied with the fourth clock signal and the tenth clock signal,
A fifth clock signal and an eleventh clock signal are respectively applied to the first pulse output section and the second pulse output section of the (12n-7) th stage,
A sixth clock signal and a twelfth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (12n-6) th stage,
The seventh clock signal and the first clock signal are respectively applied to the first pulse output section and the second pulse output section of the (12n-5) th stage,
The eighth clock signal and the second clock signal are respectively applied to the first pulse output section and the second pulse output section of the (12n-4) th stage
The ninth clock signal and the third clock signal are respectively applied to the first pulse output section and the second pulse output section of the (12n-3) th stage,
A tenth and a fourth clock signals are respectively applied to the first pulse output section and the second pulse output section of the (12n-2) th stage,
An 11th clock signal and a 5th clock signal are respectively applied to the first pulse output unit and the second pulse output unit of the (12n-1) th stage,
And a twelfth clock signal and a sixth clock signal are respectively applied to the first pulse output section and the second pulse output section of the (12n) th stage.

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