KR102478374B1 - Gate draiver and display device having the same - Google Patents

Abstract

According to the present invention, a shift register for generating a scan signal and an inverter for generating an emission signal share a plurality of clock signals, thereby reducing clock signal wires in a gate driving circuit. Accordingly, the present invention has an effect of realizing a narrow bezel by simplifying the wiring structure of the gate driving circuit.

Description

Gate driving circuit and display device including the same {GATE DRAIVER AND DISPLAY DEVICE HAVING THE SAME}

The present invention relates to a gate driving circuit and a display device including the same.

As various portable devices such as mobile phones, laptops, and computers, and information electronic devices that implement high-resolution and high-quality images such as HDTVs develop, flat panel displays applied thereto device) is gradually increasing. As such a flat panel display device, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), organic light emitting diodes (OLED), and the like are being actively researched.

Among the flat panel display devices, the organic light emitting display device uses a self-light emitting element, and thus has a fast response speed and a large light emitting efficiency, luminance, and viewing angle.

A typical organic light emitting display device includes a display panel including an organic light emitting element in each pixel, a data driving circuit for supplying data to a data line of the display panel, and a gate driving circuit for supplying a gate pulse to a gate line of the display panel. and a timing controller for controlling the data driving circuit and the gate driving circuit. The gate driving circuit sequentially supplies a scan signal and an emission signal to gate lines in response to a gate control signal input from a timing controller. In the display panel, transistors of horizontal lines are turned on by the scan signal, and the emission time of each pixel is determined by the emission signal.

A general gate driving circuit includes a shift register generating a scan signal and an inverter generating an emission signal, and may be configured as a GIP (Gate In Panel) at an edge of a display panel.

However, in a general gate driving circuit, each of the shift register and the inverter includes a plurality of control signals, for example, a gate start pulse, including four or more clock signals provided to the shift register and four or more clock signals provided to the inverter. There is a problem that the area increases according to the number of wirings by signals. A general gate driving circuit has a problem in that a bezel area of a display device is widened.

An object of the present invention is to provide a gate driving circuit capable of simplifying the wiring structure of the gate driving circuit and a display device including the same.

An object of the present invention is to provide a gate driving circuit capable of realizing a narrow bezel by simplifying the wiring structure of the gate driving circuit and a display device including the same.

In the gate driving circuit of the present invention for solving the problems of the prior art as described above, a shift register generating a scan signal and an inverter generating an emission signal share a plurality of clock signals, thereby providing clock signal wiring of the gate driving circuit. can reduce That is, clock signal wiring of the gate driving circuit of the present invention can be reduced.

The embodiment has an effect of implementing a narrow bezel by simplifying the wiring structure of the gate driving circuit.

In the display device according to the present invention, the clock signal wiring of the gate driving circuit can be reduced because the shift register and the inverter share clock signals.

In the embodiment, a clock signal wiring structure can be simplified by a gate driving circuit having a shift register and an inverter that share a clock signal. In the embodiment, at least 8 or more clock wires of a general gate driving circuit can be reduced to 5.

The embodiment has an effect of implementing a narrow bezel by simplifying the wiring structure of the gate driving circuit.

1 is a block diagram schematically illustrating the configuration of a display device according to an exemplary embodiment of the present invention.
2 is a diagram illustrating a gate driving circuit according to an embodiment.
3 is a diagram showing the configuration of a first stage of a gate driving circuit according to an embodiment.
4 is a diagram illustrating input signals and output signals of a gate driving circuit according to an exemplary embodiment.

Advantages and features of the present invention, and methods for achieving them, will become clear with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only the present embodiments make the disclosure of the present invention complete, and those skilled in the art in the art to which the present invention belongs It is provided to fully inform the person of the scope of the invention, and the invention is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiment of the present invention are exemplary, the present invention is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, when a temporal precedence relationship is described as 'after', 'continue to', 'after ~', 'before', etc., 'immediately' or 'directly' As long as ' is not used, non-continuous cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in an association relationship. may be

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. And in the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numbers indicate like elements throughout the specification.

1 is a block diagram schematically showing the configuration of a display device according to an embodiment of the present invention, FIG. 2 is a diagram showing a gate driving circuit of an embodiment, and FIG. 3 is a first stage of the gate driving circuit of the embodiment. It is a drawing showing the configuration.

As shown in FIGS. 1 to 3 , the display device of the embodiment may be an organic light emitting display (OLED), but is not limited thereto. For example, the display device may be a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), or an electrophoretic display (EPD).

The display device may include a display panel 2 , a timing controller 8 , a gate driving circuit 4 and a data driving circuit 6 .

The display panel 2 may be divided into a display area and a non-display area. The display panel 2 includes a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm and an intersection region of the plurality of gate lines G1 to Gn and the plurality of data lines D1 to Dm. Each pixel P may be disposed. Here, the pixel P may include an organic light emitting device that emits light and driving devices that drive the organic light emitting device.

When the display panel 2 is a liquid crystal display panel including a liquid crystal layer, the liquid crystal display panel may include first and second transparent substrates facing each other and a liquid crystal layer between the first and second transparent substrates. there is. The liquid crystal display panel may include a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm, and the plurality of gate lines G1 to Gn and the plurality of data lines D1 to Dm and a liquid crystal cell, a pixel electrode, and a storage capacitor connected to the transistors respectively.

The timing controller 8 aligns RGB data (RGB) input from the outside to suit the size and resolution of the display panel 2 and supplies the aligned digital image data to the data driving circuit 6 . The timing controller 8 uses synchronizing signals input from the outside, such as a dot clock (DCLK), a data enable signal (DE), a horizontal synchronizing signal (Hsync), and a vertical synchronizing signal (Vsync). A control signal (GCS) and a data control signal (DCS) are generated and supplied to the gate driving circuit 4 and the data driving circuit 6, respectively.

The data driving circuit 6 may be mounted in the display panel 2 in a COG (Chip on Glass) method. The data driving circuit 6 converts digital image data input from the timing controller 8 using a source start pulse (SSP) and a source shift clock (SSC) among the data control signals. Convert to analog data voltage. In addition, a data voltage is supplied to each of the data lines D1 to Dm in response to a source output enable (SOE) signal.

The gate driving circuit 4 may supply a scan signal and an emission signal to the gate lines G1 to Gn using the gate control signal GCS. The gate control signal is input to the gate start pulse (GSP) indicating the start gate line where the scan starts during one vertical period when one screen is displayed and the shift registers 41a, 41b, 41c, and 41d, and then the gate As a timing control signal for sequentially shifting the start pulse (GSP), a gate shift clock (GSC) generated with a pulse width corresponding to the ON period of the transistor in the pixel (P), a gate driving circuit ( 4) may include a Gate Output Enable (GOE) signal indicating an output.

The gate driving circuit 4 of the embodiment may be mounted in the non-display area of the display panel 2 in a GIP (Gate In Panel) method.

The gate driving circuit 4 of the embodiment may include a plurality of shift registers 41a, 41b, 41c, and 41d and a plurality of inverters 43a, 43b, 43c, and 43d. The plurality of shift registers 41a, 41b, 41c, and 41d generate a scan signal SCAN1 using the gate control signal, and the plurality of inverters 43a, 43b, 43c, and 43d generate the gate control signal and An emission signal EM1 may be generated from the scan signal. Here, the plurality of shift registers 41a, 41b, 41c, and 41d and the plurality of inverters 43a, 43b, 43c, and 43d may share the first to fifth clock signals CLK1 to CLK5. According to an embodiment, the plurality of shift registers 41a, 41b, 41c, and 41d and the plurality of inverters 43a, 43b, 43c, and 43d share the first to fifth clock signals CLK1 to CLK5, thereby wiring clock signals. can be reduced to 5. The first to fifth clock signals CLK1 to CLK5 may have five phases. The plurality of shift registers 41a, 41b, 41c, and 41d and the plurality of inverters 43a, 43b, 43c, and 43d of the embodiment may share the first to fifth clock signals CLK1 to CLK5 of five phases. . The gate driving circuit 4 may further include a gate start pulse input terminal VST to which the gate start pulse GSP provided to the first shift register 41a is input and a gate start pulse input wire.

The embodiment is a gate driving circuit (4) including a plurality of shift registers (41a, 41b, 41c, 41d) and a plurality of inverters (43a, 43b, 43c, 43d) sharing clock signals except for the gate start pulse (GSP). ) structure, it is possible to simplify the wiring structure of the gate driving circuit 4 by reducing clock wires from 8 to 5 compared to general gate driving circuits.

The embodiment has an effect of implementing a narrow bezel by simplifying the wiring structure of the gate driving circuit 4.

For example, taking the first stage STG1 as an example, the first shift register 41a provides the first clock signal CLK1, the third clock signal CLK3, and the fifth clock signal CLK5 to the clock terminal. and the second clock signal CLK2 may be provided to the clock terminal of the first inverter 43a.

The first shift resist 41a may include first to ninth transistors T1 to T9 and a first driving capacitor CB1.

The gate start pulse VST and the gate electrode of the first transistor T1 are connected, the drain electrode is connected to the high potential voltage VDD, and the source electrode is connected to the drain electrode of the second transistor T2.

The second transistor T2 has a gate electrode connected to the clock terminal to which the fifth clock signal CLK5 is input, a drain electrode connected to the source electrode of the first transistor T1, and a Q1 node Q1. A source electrode is connected.

The gate electrode of the third transistor T3 is connected to the QB1 node QB1, the drain electrode is connected to the source electrode of the fourth transistor T4, and the source electrode is connected to the low potential voltage VSS.

The fourth transistor T4 has a gate electrode connected to the high potential voltage VDD, a source electrode connected to the drain electrode of the third transistor T3, and a drain electrode connected to the source electrode of the second transistor T2. is connected

The fifth transistor T5 has a gate electrode connected to a terminal to which the third clock signal CLK3 is supplied, a drain electrode connected to a high potential voltage VDD, and a source electrode connected to the QB1 node QB1. .

The gate electrode of the sixth transistor T6 is connected to the gate start pulse VST, the drain electrode is connected to the source electrode of the fifth transistor T5, and the source electrode is connected to the low potential voltage VSS.

The seventh transistor T7 has a gate electrode connected to the source electrode of the fourth transistor T4, a drain electrode connected to the QB1 node QB1, and a source electrode connected to the low potential voltage VSS.

The eighth transistor T8 has a gate electrode connected to the Q1 node Q1, a drain electrode connected to a terminal to which the first clock signal CLK1 is supplied, and a scan signal SCAN1 supplied to a gate line output. The output node Vout1 and the source electrode are connected. Here, a first driving capacitor CB1 is positioned between the gate electrode and the source electrode.

The gate electrode of the ninth transistor T9 is connected to the QB1 node QB1, the drain electrode is connected to the source electrode of the eighth transistor T8, and the source electrode is connected to the low potential voltage VSS.

The first inverter 43a may include tenth to fifteenth transistors T10 to T15 and a second driving capacitor CB2.

The tenth transistor T10 has a gate electrode connected to the terminal to which the second clock signal CLK2 is supplied, a drain electrode connected to the high potential voltage VDD, and a source electrode connected to the Q2 node Q2. .

The eleventh transistor T11 has its gate electrode connected to the QB2 node QB2, its drain electrode connected to the Q2 node Q2, and its source electrode connected to the low potential voltage VSS.

The twelfth transistor T12 has a gate electrode connected to the emission signal EM1 output line, a drain electrode connected to a high potential voltage VDD, and a source electrode of the fourteenth transistor T14 and a fifteenth transistor ( A source electrode is connected to the drain electrode of T15).

The thirteenth transistor T13 has its gate electrode connected to the Q2 node Q2, its drain electrode connected to the high potential voltage VDD, and its source electrode connected to the emission signal EM1 output line Vout2. . Here, a second driving capacitor CB2 is disposed between the gate electrode and the source electrode of the thirteenth transistor T13.

The 14th transistor T14 has its gate electrode connected to the QB2 node QB2, its drain electrode connected to the emission signal EM1 output line, and its source electrode connected to the source electrode of the twelfth transistor T12. .

The gate electrode of the fifteenth transistor T15 is connected to the QB2 node QB2, the drain electrode is connected to the source electrode of the fourteenth transistor T14, and the source electrode is connected to the low potential voltage VSS.

4 is a diagram illustrating input signals and output signals of a gate driving circuit according to an exemplary embodiment.

2 to 4, in the gate driving circuit of the embodiment, the gate start pulse VST and the fifth clock signal CLK5 are synchronized and input to the first shift register 41a in the first stage STG1. Then, the first and second transistors T1 and T2 are turned on and the Q1 node Q1 is in a high state. In addition, the QB1 node QB1 is in a low state.

In the next second period (a2), when the first clock signal (CLK1) is input, High is output to the output node (Vout), and the Q1 node (Q1) is bootstrapping by the first driving capacitor (CB1). (Bootstrapping) can be done. The first inverter 43a is an output node Vout, and the fourteenth transistor T14 is turned on by a high signal, so that the emission signal EM1 becomes a low state. At this time, the 11th transistor T11 is turned on and the 13th transistor T13 is turned off.

In the next third period a3, when the second clock signal CLK2 is input, the thirteenth transistor T13 is turned on and the emission signal EM1 becomes high. Thereafter, the first clock signal CLK1 is input and the emission signal EM1 becomes low.

In the next fourth section a4, when the third clock signal CLK3 is input to the first shift register 41a, the third transistor T3 and the fifth transistor T5 are turned on to form the QB1 node QB1. becomes high, and the Q1 node Q1 becomes low. Thereafter, the second clock signal CLK2 is input and the emission signal EM1 becomes a high state.

In the next fifth period a5, the third clock signal CLK3 is input and the QB1 node QB1 is in a high state, so the emission signal EM1 remains high.

According to an embodiment, the plurality of shift registers 41a, 41b, 41c, and 41d and the plurality of inverters 43a, 43b, 43c, and 43d share the first to fifth clock signals CLK1 to CLK5, thereby wiring clock signals. can be reduced to 5. The embodiment is a general gate by a gate driving circuit structure including a plurality of shift registers (41a, 41b, 41c, 41d) and a plurality of inverters (43a, 43b, 43c, 43d) sharing clock signals except for the gate start pulse. The wiring structure of the gate driving circuit 4 can be simplified by reducing the number of clock wires from 8 to 5 compared to the driving circuit.

The embodiment has an effect of implementing a narrow bezel by simplifying the wiring structure of the gate driving circuit 4.

Features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified with respect to other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to these combinations and variations should be interpreted as being included in the scope of the embodiments.

Although the above has been described centering on the embodiment, this is only an example and is not intended to limit the embodiment, and those skilled in the art to which the embodiment belongs may find various things not exemplified above to the extent that they do not deviate from the essential characteristics of the present embodiment. It will be appreciated that variations and applications of branches are possible. For example, each component specifically shown in the embodiment can be modified and implemented. And differences related to these modifications and applications should be interpreted as being included in the scope of the embodiments set forth in the appended claims.

4: gate driving circuit
41a, 41b, 41c, 41d: a plurality of shift registers
43a, 43b, 43c, 43d: a plurality of inverters

Claims (9)

a plurality of clock signal lines;
a plurality of shift registers receiving a plurality of clock signals from the plurality of clock signal lines and generating a plurality of scan signals, each including first to ninth transistors and a first driving capacitor; and
A plurality of inverters receiving the plurality of clock signals and generating a plurality of emission signals;
The plurality of shift registers and the plurality of inverters share a plurality of clock signals,
Each of the plurality of inverters generates the plurality of emission signals based on one scan signal output from one shift register among the plurality of shift registers;
Each of the plurality of inverters,
a tenth transistor including a gate electrode receiving one of the plurality of clock signals and a source electrode connected to a node Q2;
an eleventh transistor including a gate electrode connected to the QB2 node to receive the scan signal and a drain electrode connected to the Q2 node;
a twelfth transistor including a gate electrode connected to an emission signal output line through which the plurality of emission signals are output;
a thirteenth transistor including a gate electrode connected to the Q2 node and a source electrode connected to the emission signal output line;
a fourteenth transistor including a gate electrode connected to the QB2 node to receive the scan signal and a drain electrode connected to the emission signal output line;
a fifteenth transistor including a gate electrode connected to the QB2 node and a drain electrode connected to the source electrode of the fourteenth transistor; and
and a second driving capacitor coupled between a gate electrode and a source electrode of the thirteenth transistor.
According to claim 1,
The gate driving circuit further comprising a gate start pulse input terminal and an input wire for providing a start timing signal of the plurality of shift registers.
According to claim 1,
The plurality of clock signals have a gate driving circuit having five phases.
a timing controller generating a plurality of clock signals and gate control signals;
a display panel having a plurality of pixels; and
A plurality of clock signal lines at the edge of the display panel, a plurality of shift registers for receiving a plurality of clock signals from the plurality of clock signal lines and generating a plurality of scan signals, and a plurality of emissions for receiving the plurality of clock signals a gate driving circuit including a plurality of inverters generating signals;
The plurality of shift registers and the plurality of inverters of the gate driving circuit share a plurality of clock signals;
Each of the plurality of inverters generates the plurality of emission signals based on one scan signal output from one shift register among the plurality of shift registers;
Each of the plurality of shift registers is connected one-to-one with each of the plurality of inverters,
wherein among the plurality of inverters and the plurality of shift registers, one inverter and one shift register connected to each other one-to-one receive clock signals of different phases among the plurality of clock signals.
According to claim 4,
The display device further comprises a gate start pulse input terminal and an input wire for providing a start timing signal of the plurality of shift registers.
According to claim 4,
The plurality of clock signals have five phases.
According to claim 1,
Wherein each of the plurality of shift registers is connected to the plurality of inverters one-to-one.
According to claim 7,
One inverter and one shift register connected to each other one-to-one among the plurality of inverters and the plurality of shift registers receive clock signals of different phases among the plurality of clock signals.
According to claim 8,
A first inverter among the plurality of inverters generates the emission signal based on a scan signal output from a first shift register among the plurality of shift registers and one clock signal among the plurality of clock signals;
wherein the first shift register generates the scan signal based on three clock signals among the remaining clock signals except for the one clock signal among the plurality of clock signals.

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