KR20160081649A - Gata driver and touch screen integrated display device including thereof - Google Patents

Abstract

According to an embodiment of the present invention, provided is a gate drive circuit comprising: an (N+1)^th (N is a natural number) stage which receives a scan pulse output by an N^th stage as a start signal, and outputs the scan pulse to a gate line during (N+1)^th display driving; and a dummy stage which outputs a holding signal to the (N+1)^th stage during touch driving before the (N+1)^th display driving. The (N+1)^th stage comprises an (N+1)^th pull-up transistor which is controlled by a voltage at an (N+1)^th Q node to output an applied clock signal as the scan pulse of the gate line. The holding signal is provided to the (N+1)^th Q node. Also provided is a touch screen-integrated display device comprising the same. The gate drive circuit and the touch screen-integrated display device comprising the same can maintain voltages at Q nodes of stages in a standby state during display driving.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate driver circuit and a touch screen integrated display device including the same,

The present invention relates to a gate driver circuit and a touch screen integrated type display device including the same.

The touch screen may be a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an electroluminescence device (EL) , And is a kind of an input device that presses (presses or touches) a touch sensor in a touch screen while the user views the image display device and inputs predetermined information.

The touch screen used in the above-described display device can be divided into an add-on type, an on-cell type, and an in-cell type according to its structure. The attachment type is a method in which a touch screen is attached to an upper plate of a display device after separately manufacturing a display device and a touch screen. The upper type is a method of directly forming elements constituting the touch screen on the upper glass substrate surface of the display device. The built-in type incorporates a touch screen inside the display device to achieve a thin display device and enhance durability. However, the attachable touch screen has a structure in which the completed touch screen is mounted on the display device and is thick, and the brightness of the display device becomes dark, thereby reducing visibility. In addition, the upper-surface type touch screen has a structure in which a separate touch screen is formed on the upper surface of the display device. Though it is possible to reduce the thickness of the touch screen, the thickness of the driving electrode and the sensing electrode constituting the touch screen, There is a problem that the manufacturing cost increases due to an increase in thickness and an increase in the number of processes.

On the other hand, the integrated touch screen has advantages of improving durability and thinning, and solving the problems caused by the attachment type and the upper type touch screen. Such an integrated touch screen can be classified into a light type and a capacitive touch screen.

The optical touch screen forms a light sensing layer on a thin film transistor substrate array of a display device and recognizes light reflected through an object existing in a touched portion by using light from a backlight unit or infrared light. However, the optical touch screen exhibits a relatively stable driving performance in the case of a dark environment, but stronger lights than the reflected light act as noise when the surroundings are bright. This is because the intensity of the light reflected by the actual touch is very weak, which may cause an error in touch recognition even if the outside is slightly bright. Particularly, the optical touch screen has a problem that when the surrounding environment is exposed to sunlight, the light intensity is so strong that the touch recognition may not be performed in some cases.

The capacitance type touch screen can be divided into a self capacitance type and a mutual capacitance type. The mutual capacitive touch screen divides a common electrode into two parts, a drive electrode and a sensing electrode, so that a mutual capacitance is formed between the driving electrode and the sensing electrode, thereby measuring the amount of mutual capacitance generated during touch Thereby recognizing the touch. However, mutual capacitance type touch screen has a very small mutual capacitance generated when a touch is recognized, while parasitic capacitance between a gate line and a data line constituting a display device is very large, There is a problem that is difficult to recognize. In addition, since the mutual capacitance type touch sensor requires a plurality of touch driving lines for touch driving and a plurality of touch sensing lines for touch sensing on the common electrode, a complicated wiring structure is required. In order to solve such a problem, a plurality of electrodes are formed so as to overlap with a plurality of pixel electrodes when the plurality of electrodes are formed in the display region of the panel, and these electrodes are driven with the pixel electrodes formed in each pixel during the display driving period There has been proposed a display method and a touch driving method which operate as a common electrode and operate as a touch electrode for sensing a touch position by a touch scan signal applied from a touch driver during a touch driving period.

In the case of the display and the touch split driving method, there is a stage in which the Q node is held in a stand-by state among the stages constituting the shift register of the gate driving circuit during the touch driving time. There is a problem that a voltage drop due to a leakage current occurs because the Q node of the stage is a floating state in which there is no power supply during the touch driving time. Such a problem is accompanied by a problem that an abnormal signal is output on the gate line, and there is a problem of poor image quality such as a dim phenomenon in which a horizontal line is visible on a display panel corresponding to the gate line. Furthermore, there is a limitation in increasing the touch driving time due to a problem that the Q-node voltage of the stage in the standby state drops.

The gate driver circuit and the touch screen integrated display device including the gate driver circuit according to the embodiments of the present invention include a gate driving circuit having a gate driving circuit including a dummy stage for holding a voltage of a Q node of a standby stage in touch operation, It is possible to provide a touch screen integrated display device including the same.

The gate driver circuit and the touch screen integrated display device including the same according to the embodiment of the present invention can secure a clock time (CLK time) at a high resolution by reducing the margin time between the display driving time and the touch driving time A gate driver circuit and a touch screen integrated display device including the same may be provided.

The gate driving circuit and the touch screen integrated type display device including the same according to the embodiment of the present invention include a gate driving circuit capable of increasing the touch driving time according to the Q node voltage holding of a stable standby stage, An integrated display device may be provided.

The gate driver circuit and the touch screen integrated display device including the gate driver circuit according to the embodiment of the present invention receive a scan pulse output from the Nth (N is a natural number) stage as a start signal and scan And a dummy stage for outputting a holding signal to the (N + 1) th stage during the touch driving before the (N + 1) th display drive, and the (N + 1) And an (N + 1) -th pull-up transistor controlled by a voltage on a Q-node and outputting an applied clock signal as a scan pulse of a gate line, wherein the holding signal is supplied to the (N + A gate driver circuit including the gate driver circuit and the touch panel integrated display device including the same, Can be provided.

The gate driver circuit and the touch screen integrated type display device including the gate driver circuit according to the embodiment of the present invention may include a touch screen integrated type display device having a gate driving circuit including a dummy stage for holding a voltage of a Q node of a stage in a stand- Device can be provided and the clock time (CLK time) can be secured at a high resolution by reducing the margin time between the display driving time and the touch driving time, and the stable Q-node voltage holding And a touch screen integrated display device including the gate driver circuit.

1A is a diagram illustrating a touch panel integrated type display apparatus and a driving unit thereof according to an embodiment having one gate driving circuit.
1B shows a plurality of pixels of a display panel and corresponding pattern electrodes.
1C is a view showing a connection relation between a pattern electrode and a sensing line;
2 is a diagram illustrating a touch panel integrated display device and its driving unit according to an embodiment having two gate driving circuits.
FIG. 3 and FIG. 4 are diagrams showing connection relationships of a plurality of stages constituting a shift register according to different embodiments of the present invention; FIG.
Figure 5 shows a forward gate scan;
6 is a time flow diagram illustrating display and touch time-division driving;
Figs. 7 to 9 are circuit diagrams
10 is a view showing a Q-node charge, a QB node discharge, and a scan pulse output operation of the N-th stage in the forward driving.
11 is a diagram showing a Q-node discharge and a QB node charge in an N-th stage in forward driving;
12 is a diagram illustrating Q node charging, QB node discharging, and scan pulse output operation of the N stage in the reverse driving.
13 is a diagram showing a Q-node discharge and a QB node charge in an N-th stage in a reverse drive.
14A is a circuit diagram of a gate drive circuit.
14B is a diagram illustrating an operation process of a plurality of stages around an N-th stage operation.
15 is a view showing an operation process of a plurality of stages around a dummy stage operation.
16 is a diagram illustrating an operation process of a plurality of stages around an (N + 1) stage operation.
17 is a waveform diagram showing the Q node voltage in the (N + 1) stage operation;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description will be given with reference to drawings of a gate driver circuit and a touch screen integrated display device including the same according to an embodiment of the present invention. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. However, it should be understood that the present invention is not limited to the embodiments disclosed herein but may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification. The dimensions and relative sizes of the layers and regions in the figures may be exaggerated for clarity of illustration.

It will be understood that when an element or layer is referred to as being another element or "on" or "on ", it includes both intervening layers or other elements in the middle, do. On the other hand, when a device is referred to as "directly on" or "directly above ", it does not intervene another device or layer in the middle.

The terms spatially relative, "below," "lower," "above," "upper," and the like, And may be used to easily describe the correlation with other elements or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions.

The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. &Quot; comprise "and / or" comprising ", as used in the specification, means that the presence of stated elements, Or additions.

FIG. 1A is a diagram illustrating a touch panel integrated display device and a driving unit thereof according to an embodiment having one gate driving circuit, and FIG. 1B is a view showing a plurality of pixels of a display panel and corresponding pattern electrodes And Fig. 1C is a view showing the connection relationship between the pattern electrode and the sensing line. And FIG. 2 is a diagram illustrating a touch panel integrated display device and its driving unit according to an embodiment having two gate driving circuits.

As shown in the figure, the display apparatus of the present invention includes a liquid crystal panel 100 for displaying an image, a timing controller 400 receiving a timing signal from an external system to generate various control signals, And a data driver circuit (200, 300) for controlling the touch panel (100), and includes a touch driver circuit (500) for touch driving.

The liquid crystal panel 100 has a structure in which K (K is a natural number) gate lines GL and a plurality of data lines DL are crossed in a matrix form on a substrate using a glass, and a plurality of pixels 110 define. Each pixel 110 is provided with a thin film transistor (TFT), a liquid crystal capacitor Clc and a storage capacitor Cst, and all the pixels 110 constitute one display area A / A. A region where the pixel 110 is not defined is divided into a non-display region (N).

In addition, the liquid crystal panel 100 has a built-in touch screen, and the touch screen senses a touch position of the user. In particular, the liquid crystal panel according to the present invention includes a touch screen of an inser- can do. As shown in FIG. 1B, the liquid crystal panel 100 may further include a plurality of pattern electrodes 120 grouped into a plurality of pixel groups 110 corresponding to all the pixels 110 and corresponding to each group at a ratio of 1: 1. 1C, the plurality of pattern electrodes 120 may be connected to the touch driving circuit 500 through a sensing line SL.

A common voltage may be applied to the pattern electrode 120 to drive the display of the liquid crystal panel 100, and thus the common electrode may be operated as a common electrode for driving the liquid crystal together with the pixel electrode. In addition, a touch scan signal may be applied to the pattern electrode 120 to sense the touch, and may act as a touch electrode to sense the touch position. For example, since the present invention is a touch screen integrated type display device according to an embodiment, display driving and touch driving are temporally divided and driven within one frame, and when the driving mode of the liquid crystal panel 100 is a display driving mode When the driving mode of the liquid crystal panel 100 is the touch driving mode, the plurality of pattern electrodes 120 receive a common voltage and operate as a common electrode for driving the display together with the pixel electrodes. And operates as a touch electrode for touch position sensing. Here, the common voltage may be applied from the touch driving circuit 500 or may be directly applied to the liquid crystal panel 100 without the touch driving circuit 500 having a separate common voltage generating part.

In addition, the touch driving circuit 500 includes a touch scan signal generating unit for generating a touch scan signal, a touch sensing unit for sensing a touch using a difference between the received touch sensing signals, A common voltage may be applied to each of the plurality of pattern electrodes 120 through the sensing lines SL according to the driving mode of the liquid crystal panel 100 or a touch scan signal may be applied to the plurality of pattern electrodes 120 through the sensing lines SL , Receives a touch sensing signal generated by a touch scan signal from the plurality of pattern electrodes 120, and senses whether or not the touch is sensed by using the difference of the received touch sensing signal.

Meanwhile, the pattern electrodes 120 may be grouped and operated sequentially for one frame, and the number of the pattern electrodes 120 may be varied in consideration of the touch driving time and the display driving time.

The timing controller 400 outputs a timing signal such as a video signal RGB transmitted from an external system and a clock signal DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE And generates a control signal for the gate drive circuit 200 and the data drive circuit 300.

Here, the horizontal synchronization signal Hsync is a signal indicating the time taken to display one horizontal line of the screen, and the vertical synchronization signal Vsync is a signal indicating the time taken to display a frame of one frame. The data enable signal DE is a signal indicating a period during which the data voltage is supplied to the pixel defined in the liquid crystal panel 100.

The timing controller 400 generates the control signal GCS of the gate driving circuit 200 and the control signal DCS of the data driving circuit 300 in synchronization with the input timing signal.

In addition, the timing controller 400 generates a plurality of clock signals for determining the driving timing of each stage of the gate driving circuit 200, and supplies the generated clock signals to the gate driving circuit 200. The timing controller 400 arranges and modulates the received image data (RGB DATA) in a form that the data driving circuit 300 can process. Here, the aligned image data may be a form in which a color coordinate correction algorithm for improving image quality is applied.

The timing controller 400 may provide a touch enable signal TouchEN for the touch driving to the gate driving circuit 200 and the touch driving circuit 500.

Next, the data driving circuit 300 generates a sampling signal by shifting a source start pulse (SSP) from the timing controller 400 according to a source shift clock (SSC). The data driving circuit 300 latches the image data input according to the source shift clock SSC according to the sampling signal and changes the data into a data signal and then outputs the data signal to the data driver 300 in response to a source output enable And supplies a data signal to the data lines DL in units of horizontal lines. To this end, the data driving circuit 300 may include a data sampling unit, a latch unit, a digital-analog converting unit, and an output buffer.

Next, the gate driving circuit 200 shifts a gate start pulse (GSP) transmitted from the timing controller 400 according to a gate shift clock (GSC) GL1 to GLn to the gate lines GL1 to GLn during the rest of the period in which the scan pulse of the gate high voltage VGH is not supplied, (VGL).

The gate driving circuit 200 may be formed independently of the panel and may be electrically connected to the panel in various ways. The gate driving circuit 200 may include a liquid crystal panel (not shown) (GIP) method on the non-display area N in the form of a thin film pattern during the fabrication of the substrate of the TFT array substrate 100 shown in FIG. In this case, the gate control signal for controlling the gate driving circuit 200 may be the clock signal CLK and the start signal VST for driving the first driven stage of the shift register.

2, the gate driving circuit 200 may be provided at both ends of the liquid crystal panel 100 and in the non-display area N. In FIG. The first and second gate driver circuits 200a and 200b include a plurality of stages including shift registers. The first and second gate driving circuits 200a and 200b are connected to a plurality of gate lines GL1 to GLn formed in the liquid crystal panel 100 in response to a gate control signal GCS input from the timing controller 400 It is possible to alternately output the gate high voltage VGH which is a scan pulse. Here, the output gate high voltage VGH may be overlapped during a certain horizontal period. This is for precharging the gate lines GL1 to GLn, so that it is possible to more stably charge the pixel when the data voltage is applied.

FIGS. 3 and 4 are diagrams illustrating connection relationships of a plurality of stages constituting a shift register according to different embodiments of the present invention. And Figure 5 shows a forward gate scan. 6 is a time-flow diagram illustrating display and touch time-division driving.

In Fig. 5, the stage is driven in the order of B, C, and A in forward driving, and the stage is driven in the order of A, B, and C in the backward driving. A is a stage for performing a Q node holding operation, B is a stage for outputting a scan pulse before the dummy stage operation, and C is a dummy stage for driving during a touch operation.

For convenience of explanation, the connection relationship of N stages (N is a natural number and N stage is N stage) of the plurality of stages and the gate high voltage (VGH) is outputted to the corresponding gate line from the N stage .

Referring to FIG. 3, the shift register 210 according to the first embodiment is a shift register included in the gate driving circuit 200 according to the first embodiment as shown in FIG. 1. Referring to FIG. 4, The shift register 210 according to the example is a shift register included in the gate driving circuits 200a and 200b according to the second embodiment as shown in FIG.

N, N + 1, N + 2 and dummy stages are shown as a plurality of stages constituting the shift register 210 according to the first and second embodiments.

Each of the N, N + 1, and N + 2 stages outputs at least three clock signals CLK (first clock signal line CLK 1 and second clock signal line CLK 2 in the case of the second embodiment) . One of the output signals of the adjacent stages may be supplied as a start signal and the other as a reset signal.

In addition, the dummy stage may receive at least two clock signals from the clock signal line CLK and may receive a touch enable signal TouchEN from the touch enable signal line, a first touch enable signal TouchEN 1 in the case of the second embodiment ) Or a touch enable signal (TouchEN 2)). One of the output signals of the adjacent stages may be applied as the start signal VST and the other as the reset signal RST.

The stages may perform an operation of supplying a scan pulse when the start signal VST is received and discharging the gate line GL when the reset signal RST is inputted.

Specifically, the N stage includes a start signal (VST) input terminal and a reset signal (RST) input terminal, and a scan pulse output from the output terminal G (n-1) of the (N-1) The holding signal Hd input from the start signal VST input terminal and output from the output terminal G (n + 1/2) of the next stage dummy stage is input to the reset signal RST input terminal .

The dummy stage includes a start signal VST input terminal and a reset signal RST input terminal and outputs a scan pulse output from the output terminal G (n) of the N stage, which is a previous stage, And the scan signal output from the output terminal G (n + 1) of the (N + 1) th stage, which is the next stage, can be input to the reset signal RST input terminal.

The (N + 1) th stage includes a start signal (VST) input terminal and a reset signal (RST) input terminal, and a scan pulse output from the output terminal G (n) VST input terminal and receives a scan signal output from the output terminal G (n + 2) of the (N + 1) th stage as the next stage to the reset terminal RST. The (N + 1) th stage further includes a holding signal Hd input terminal. The holding signal Hd, which is an output signal of the dummy stage, is input to the holding signal Hd.

The (N + 2) stage includes a start signal (VST) input terminal and a reset signal (RST) input terminal, and a scan pulse output from the output terminal G (n + 1) of the The scan signal inputted to the start signal VST input terminal and the scan signal outputted from the output terminal G (n + 3) of the (N + 3) th stage next stage can be inputted to the reset signal RST input terminal .

As described above, the shift register 210 according to the embodiment of the present invention may include a plurality of dummy stages. For example, as shown in FIG. 5, the first to 64th stages and the 65th to 128th gate lines (GL65 to GL128) for sequentially supplying scan pulses to the first to 64th gate lines (GL1 to GL64) And a dummy stage arranged between stages 65 to 128 for sequentially supplying the dummy stage. However, the present invention is not limited to this. It is also possible to group the stages corresponding to gate lines to be activated during one display period of a plurality of display periods in one frame as shown in FIG. 6, A dummy stage may be included in each of the dummy stages. And the stage next to the dummy stage may be a stage including a holding signal (Hd) input terminal.

However, the present invention is not limited to this. For example, when the reverse operation is performed in the order of the first stage in the last stage, that is, in the case where the (N + 1) When the dummy stage is operated after the pulse output and then the Nth stage is operated, the Nth stage may be a stage including a holding signal Hd input terminal.

Meanwhile, the scan pulse output stages may output a gate high voltage VGH as a scan pulse to any one of the plurality of gate lines GL 1 to GL n in synchronization with any one of the clock signals CLK.

Further, each of all the stages may receive a low potential power supply (VSS) and a forward power supply (FWD) and a reverse power supply (REV) from the high potential power supply (VDD) and the low potential power supply terminal from the high potential power supply terminal.

7 to 9 are circuit diagrams of the N-th stage.

≪ Circuit diagram of the N stage >

Stage circuit constituting the shift register 210 according to the embodiment of the present invention.

7 to 9, the N stage may include a pull-up transistor Tup, a pull-down transistor Tdown, a first capacitor CQ and a second capacitor CQB. In addition, the N stage may include a pull- And a QB node charging unit 212. [

The gate terminal of the pull-up transistor Tup is connected to the Q node, the drain terminal is connected to the N-th clock signal (CLK n) supply terminal, and the source terminal of the pull- The gate terminal of the pull-down transistor Tdown is connected to the QB node and the drain terminal thereof is connected to the output terminal G (n) of the Nth stage, And the source terminal can be connected to the low potential power supply terminal (VSS). The first capacitor CQ may be connected to the QB node and the low potential power supply terminal VSS. The second capacitor CQB may be connected to the Q node and the low potential power supply terminal VSS.

Further, the charging and discharging unit 211 may function to charge or discharge the Q and QB nodes. And the gate terminal of the first transistor T1 may include the output terminal G (n-1) of the (N-1) th stage, ), A drain terminal connected to the forward power supply terminal FWD, and a source terminal connected to the Q node. The gate terminal of the second transistor T2 is connected to the output terminal G (n + 1) of the (N + 1) th stage, the drain terminal thereof is connected to the reverse power supply terminal REV, Lt; / RTI > node. The gate terminal of the third transistor T3 may be connected to the Q node, the drain terminal may be connected to the QB node, and the source terminal may be connected to the low potential power supply terminal VSS.

The QB node charging unit 212 may charge the QB node and may include the fourth to seventh transistors T4 to T7 and the gate terminal of the fourth transistor T4 may be connected to the positive power supply terminal FWD, the drain terminal thereof is connected to the (N + 1) th clock signal CLC (n + 1) supply terminal, and the source terminal thereof is connected to the first node N1. The gate terminal of the fifth transistor T5 is connected to the reverse power supply terminal REV and the drain terminal of the fifth transistor T5 is connected to the supply terminal of the (N-1) th clock signal CLC (n-1) 1 node < RTI ID = 0.0 > N1. ≪ / RTI > The gate terminal of the sixth transistor T6 may be connected to the first node N1, the drain terminal may be connected to the high potential power supply terminal VDD, and the source terminal may be connected to the QB node. The gate terminal of the seventh transistor T7 may be connected to the QB node, the drain terminal thereof may be connected to the Q node, and the source terminal thereof may be connected to the low potential power supply terminal VSS.

The (N + 1) -th clock signal CLC (n + 1) supply terminal to which the drain terminal of the fourth transistor T4 is connected is connected to the pull-up transistor Tup of the (N + 1) supply terminal connected to the drain terminal of the fifth transistor T5 and the N-1th clock signal CLC (n-1) supplying terminal connected to the drain terminal of the fifth transistor T5 is connected to the pull- And may be connected to the drain terminal of the transistor Tup. Therefore, the above description will be made with reference to the (N + 1) th stage. The drain terminal of the fourth transistor T4 of the QB node charging unit (not shown) of the (N + (N + 2) -th stage is simultaneously supplied to the drain terminal of the pull-up transistor Tup of the (N + 2) It can be explained that the Nth clock signal CLK (n) is simultaneously supplied to the drain terminal of the fifth transistor T5 and the drain terminal of the pull-up transistor Tup of the Nth stage which is the previous stage of the (N + 1) .

FIG. 10 is a diagram illustrating a Q node charge, a QB node discharge, and a scan pulse output operation of the Nth stage in forward driving, and FIG. 11 illustrates a Q node discharge and a QB node charge of the N stage in forward driving .

≪ Display driving period: forward driving >

The first transistor T1 is turned on by the output signal of the (N-1) th stage during the first time period of the display driving period T1 to supply the forward power FWD to the Q node, The third transistor T3 is turned on to discharge the QB node and the pull-up transistor Tup is turned on according to the bootstrap by the high logic level of the Nth clock signal CLK n, A scan pulse of a logic level can be output.

During the second time period following the first time period during the display driving period T1, the second transistor T2 is turned on by the output signal of the (N + 1) th stage and the reverse power supply REV is supplied to the Q node The Q-node is discharged, and the (N + 1) -th clock signal (CLK n + 1) of the high logic level to the drain terminal of the fourth transistor T4 turned on by the forward power source FWD charges the QB node, The output terminal G (n) of the Q-th stage and the output stage G (n) of the N-th stage can be discharged by the low potential power supply VSS, respectively, while the pull-down transistor T7 and the pull-down transistor Tdown are turned on.

FIG. 12 is a diagram showing Q node charging, QB node discharging and scan pulse output operations of the N stage in the reverse driving, and FIG. 13 is a diagram showing Q node discharging and QB node charging of the N stage in the reverse driving .

<Display driving period: reverse driving>

The second transistor T2 is turned on by the output signal of the (N + 1) th stage during the first time period of the display driving period T1 to supply the reverse power source REV to the Q node, The third transistor T3 is turned on to discharge the QB node and the pull-up transistor Tup is turned on according to the bootstrap by the high logic level of the Nth clock signal CLK n, A scan pulse of a logic level can be output.

The first transistor T1 is turned on by the output signal of the (N-1) th stage during the second time period subsequent to the first time period during the display driving period T1 and the forward power FWD is supplied to the Q node The Q-node is discharged and the N-1-th clock signal CLK (n-1) of the high logic level to the drain terminal of the fifth transistor T5 turned on by the reverse power supply REV charges the QB node The seventh transistor T7 and the pull-down transistor Tdown are turned on so that the output terminal G (n) of the Q node and the Nth stage can be discharged by the low potential power supply VSS, respectively.

Each of the first and second transistors T1 and T2 may operate either the forward or the reverse operation of the gate driving circuit 200 to provide the forward power FWD or the reverse power REV to the Q node The forward power supply FWD may be higher than the reverse power supply REV during forward driving and the forward power supply FWD may be higher than the reverse power supply REV during reverse driving.

<Diode connection transistor>

At least one of the N-th stage and the (N + 1) th stage may include a diode connection transistor (Td), and the diode connection transistor (Td) may electrically connect the gate terminal and the drain terminal, The source terminal of the diode connection transistor Td may be connected to the Q node and the drain terminal may be connected to the output terminal G (n + 1/2) of the dummy stage.

The diode connection transistor Td is connected to the (N + 1) th stage in the forward operation, and the (N + 1) th stage, the dummy stage and the N &lt; th &gt; Stage connection, the diode connection transistor Td can be connected to the Q-node of the N-th stage.

On the other hand, when the holding signal Hd is supplied, the Q node of the stage next to the dummy stage can maintain the charge without a separate control signal for controlling the transistor by using the diode connection transistor Td.

<Dummy stage>

The touch enable signal TouchEN may be applied to the drain terminal of the pull-up transistor Tup of the dummy stage and the drain terminal of the fourth transistor T4 of the QB node charging unit 212 of the dummy stage may be supplied with the 1) -th clock signal (CLK (n + 1)) may be applied to the drain terminal of the fifth transistor T5. That is, the N-1th clock signal CLK (n-1) applied to the pull-up transistor Tup of the two stage stages with respect to the dummy stage and the N-1th clock signal CLK +2 clock signal CLK (n + 2) may be applied. The scan pulse from the output signal terminal G (n) of the first stage is supplied to the gate terminal of the first transistor T1 of the dummy stage on the basis of the dummy stage, A scan pulse from the scan line G (n + 1) may be supplied to the gate terminal of the second transistor T2 of the dummy stage. By using the output signal of the last stage of the display driving section as the start (VST) signal of the dummy stage, the dummy stage can be driven at the touch driving timing.

<Circuit diagram of gate drive circuit>

14A is a circuit diagram of a gate drive circuit.

The functions of the stages, which are components of the shift register 210 constituting the gate driving circuit 200 according to the embodiment of the present invention, will be described with reference to FIG. 14A.

The gate driving circuit 200 according to the embodiment applies the scan pulse output from the Nth (N is a natural number) stage to the start signal VST (G (n-1) 1 stage for outputting a scan pulse and a dummy stage for outputting a hold signal Hd to the (N + 1) th stage during the touch driving before the (N + 1) th display drive, And an (N + 1) -th pull-up transistor controlled by a voltage on an (N + 1) -th node to output an applied clock signal CLK (n + 1) as a scan pulse of a gate line, And may be supplied to the (N + 1) -th node. And the Nth stage may include a diode connection transistor Td for supplying the holding signal Hd to the (N + 1) th node. The dummy stage may receive the scan pulse of the N-th stage as a start signal (VST: G (n)). The Nth stage is controlled by a voltage on an NQ node controlled by a scan pulse (VST: G (n-1)) of an (N-1) And an Nth pull-up transistor for outputting a scan pulse (CLK (n)) as a scan pulse, wherein the dummy stage is controlled by a scan pulse (VST: G (n) And an (N + 1/2) pull-up transistor controlled by the voltage on the 1/2 Q node and outputting the touch enable signal TouchEN as the holding signal. The Nth display driving may be performed before the touch driving. Also, the touch enable signal (TouchEN) may be at a high level during the touch driving and may be at a low level during the display driving.

FIG. 14B is a diagram illustrating an operation process of a plurality of stages around an Nth stage operation, FIG. 15 is a diagram illustrating an operation process of a plurality of stages around a dummy stage operation, and FIG. FIG. 2 is a diagram illustrating an operation process of a plurality of stages, with reference to FIG.

<Display and touch time division driving method>

During the display period T1, the first through 64th stages sequentially operate to output scan pulses to the output terminals of the stages, and the output signal of the 64th stage, which is the Nth stage, 1 is supplied to the gate terminal of the first transistor T1 and the gate terminal of the first transistor T1 of the charging portion 211 of the (N + 1) -th stage.

During the touch period T2, the first transistor T1 is turned on by the output signal of the Nth stage to charge the Q node of the dummy stage and the touch enable signal TouchEN is applied to the drain of the pull-up transistor Tup of the dummy stage The Q node is bootstrapped so that the pull-up transistor Tup is turned on and the touch enable signal TouchEN is output to the output terminal G (n + 1/2) of the dummy stage. The touch enable signal TouchEN of the high logic level output to the output terminal G (n + 1/2) of the dummy stage is supplied to the diode connection transistor Td of the (N + 1) Q nodes can be continuously charged.

During the next display period T2, the 65th stage of the (N + 1) -th stage outputs the output terminal G (n + 1) while the Q-node is bootstrapped by the (N + 1) -th clock signal CLK So that a high-level scan pulse can be output.

17 is a waveform diagram showing the Q node voltage in the (N + 1) stage operation.

Referring to FIG. 17, the dummy stage may serve as a voltage source so that the Q-node voltage of the (N + 1) -th stage, which is the next stage, is not floating. Comparing the case where the holding signal Hd is supplied (Hd (o)) and the case where it is not supplied (Hd (x)), the Q node voltage of the (N + 1) (Bootstrap 1_Hd (o) > bootstrap 2_Hd (x)) when bootstrapping. Therefore, since the scan pulse of the on-voltage gate high voltage (VGH) is outputted, the dim phenomenon which is the phenomenon of the horizontal lag can be eliminated.

Since the voltage of the Q node of the stage in the standby state like the (N + 1) th stage can be maintained in the touch driving period, the number of C block periods in FIG. 5 is reduced, that is, the number of times of the touch driving period is reduced The time length of one touch driving section can be increased. Also, the margin time between the display driving period and the touch driving period is set to be a point, and the clock time (CLK time) can be secured at a high resolution.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10 display device
100 liquid crystal panel
110 pixels
120 pattern electrode
200 gate drive circuit
200a First gate drive circuit
200b second gate drive circuit
210 Shift registers
211 Crying
212 QB node active part
300 data drive circuit
400 timing controller
500 touch drive circuit

Claims (14)

An (N + 1) th stage in which a scan pulse outputted by the Nth (N is a natural number) stage is supplied as a start signal and a scan pulse is outputted to the gate line in the (N + 1) th display drive; And
And a dummy stage for outputting a holding signal to the (N + 1) th stage during a touch driving operation before the (N + 1) th display driving,
And the (N + 1) th stage includes an (N + 1) th pull-up transistor controlled by a voltage on the (N + 1) th node to output an applied clock signal as a scan pulse of the gate line,
And the holding signal is supplied to the (N + 1) -th node. The method according to claim 1,
And the (N + 1) th stage includes a diode connection transistor for supplying the holding signal to the (N + 1) th node. 3. The method of claim 2,
And the dummy stage receives a scan pulse of the N stage as a start signal. The method of claim 3,
The Nth stage is controlled by a voltage on an NQ node controlled by a scan pulse of the (N-1) -th stage during the Nth display driving and a voltage is charged, and an Nth pull-up transistor for outputting an Nth clock signal as a scan pulse Including,
The dummy stage is controlled by a voltage on an (N + 1) th Q-node controlled by a scan pulse of the (N + 1) th stage and charged with a voltage, and outputs a touch enable signal to the (N + And a pull-up transistor. 5. The method of claim 4,
And the Nth display driving is performed before the touch driving. 5. The method of claim 4,
Wherein the touch enable signal is at a high level during the touch driving and becomes a low level during the display driving. 6. The method of claim 5,
And each of the Nth, N + 1, and dummy stages includes a charging and discharging unit for charging and discharging respective Q nodes,
The charge and discharge unit of the Nth stage is controlled by a scan pulse of the (N + 1) th stage and a first transistor which is controlled by a scan pulse of the (N-1) th stage to provide a first voltage to the NQ node And a second transistor for providing a second voltage to the NQ node,
The charge / discharge unit of the dummy stage includes a first transistor controlled by a scan pulse of the Nth stage to provide a first voltage to the (N + 1) th and (N + 2) th nodes, And a second transistor controlled to provide a second voltage to the (N + 1) th Q node,
The charge and discharge unit of the (N + 1) -th stage is controlled by a scan pulse of the (N + 2) -th stage and a first transistor controlled by the scan pulse of the (N + 1) th stage to provide a first voltage to the And a second transistor controlled to provide a second voltage to the (N + 1) th node. 8. The method of claim 7,
Wherein the first voltage is higher than the second voltage. A gate driving circuit according to claim 1;
A panel for displaying an image; And
And a touch driving circuit for sensing a touch of the panel,
The panel includes a plurality of pixels, a plurality of pattern electrodes grouping the plurality of pixels into a plurality of pixel groups and corresponding to each group on a one-to-one basis, and a sensing line connecting each of the pattern electrodes to the touch driving circuit A display comprising. 10. The method of claim 9,
And the Nth stage includes a diode connection transistor for supplying the holding signal to the (N + 1) th node. 11. The method of claim 10,
Wherein the dummy stage receives the scan pulse of the Nth stage as a start signal. 12. The method of claim 11,
The Nth stage is controlled by a voltage on an NQ node controlled by a scan pulse of the (N-1) -th stage during the Nth display driving and a voltage is charged, and an Nth pull-up transistor for outputting an Nth clock signal as a scan pulse Including,
The dummy stage is controlled by a voltage on an (N + 1) th Q-node controlled by a scan pulse of the (N + 1) th stage and charged with a voltage, and outputs a touch enable signal to the (N + And a pull-up transistor. 13. The method of claim 12,
And the (N + 1) th display driving is performed before the touch driving. 14. The method of claim 13,
Wherein the touch enable signal becomes a high level during the touch driving and becomes a low level during the display driving.

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