JPH08254969A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: To prevent a DC voltage from being impressed on a liquid crystal layer by selecting and outputting an internal clock when the stoppage of the clock to be input from a main computer is detected. CONSTITUTION: When the output of an integration circuit A101 or an integration circuit B102 is fixed to an H level, the output of an inveter 131 or an inverter 132 is turned to an L level and since the L level is inputted to the input terminal of one side of a NAND circuit 121, the NAND circuit 121 is fixed to the H level. When the NAND circuit 121 is fixed to the H level, the output of an inverter 112 is turned to the L level and since the L level is inputted to the input terminal of one side of a NAND circuit 122, the output of the NAND 122 is fixed to the H level and then the clock from the main computer is stopped. Moreover, when the NAND circuits 121, 122 are fixed to the H levels, the internal clock from an oscillator 140 is outputted through NAND circuits 123, 124.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a technique effectively applied to a liquid crystal display device to which a control signal such as a clock is inputted from a main body computer.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display module has been known as one of liquid crystal display devices.

FIG. 6 shows a conventional TFT (Thin Fil).
FIG. 3 is a block diagram showing a schematic configuration of a liquid crystal display module of the (m Transistor) system.

In FIG. 6, TFT-LCD is a TFT liquid crystal display panel, 500 is an interface unit, 510 is a display control device, 520 is a power supply unit, 521 is a positive voltage generation circuit, 522 is a negative voltage generation circuit, and 523 is a common electrode. (Counter electrode) voltage generation circuit, 524 is a gate electrode voltage generation circuit, 525 is a multiplexer, 530 is a drain driver, 531, 532, 541 are signal lines, 533 is a data bus for display data, and 540 is a gate driver.

In the TFT type liquid crystal display module shown in FIG. 6, a TFT liquid crystal display panel (TFT-LC) is used.
The drain driver 530 is disposed above D), and the gate driver 540 and the interface unit 500 are provided on the side surface of the TFT liquid crystal display panel (TFT-LCD).
Is arranged.

The interface section 500 is mounted on an interface board, and the drain driver 530 and the gate driver 540 are also mounted on dedicated printed boards.

The TFT liquid crystal display panel (TFT shown in FIG.
-LCD) has thin film transistors (TFTs) arranged in a matrix, and the thin film transistors (TFs) are
T) is arranged in an intersecting region between two adjacent drain signal lines (D) and two adjacent gate signal lines (G).

The drain electrodes of the thin film transistors (TFTs) in the column direction are connected to the drain signal lines (D), and the gate electrodes of the thin film transistors (TFT) in the row direction are connected to the gate signal line (G). .

The source electrode of the thin film transistor TFT is connected to the pixel electrode, and the pixel electrode and the common electrode (counter electrode)
And the liquid crystal layer is sandwiched between.

The thin film transistor TFT becomes conductive when a positive bias voltage is applied to its gate electrode and becomes non-conductive when a negative bias voltage is applied to its gate electrode.

Here, the liquid crystal display panel (TF) shown in FIG.
The T-LCD) is composed of 640 × 3 × 480 pixels.

In the TFT type liquid crystal display module shown in FIG. 6, the interface section 500 includes the display control unit 5.
10 and a power supply unit 520.

The display control device 510 is composed of one semiconductor integrated circuit (LSI), and has a clock and a display timing signal transmitted from the main computer.
The drain driver 530 and the gate driver 540 are controlled and driven on the basis of the respective control signals of the horizontal synchronizing signal and the vertical synchronizing signal and the display data.

Further, the power supply unit 520 has a positive voltage generating circuit 5
21, negative voltage generation circuit 522, common electrode (counter electrode)
A voltage generation circuit 523, a gate electrode voltage generation circuit 524,
It is composed of a multiplexer 525.

Positive voltage generation circuit 521, negative voltage generation circuit 5
Reference numeral 22 is composed of a series resistance voltage dividing circuit, and generates a gradation gradation reference voltage of a positive voltage or a gradation gradation reference voltage of a negative voltage.

Further, the multiplexer 525 switches the output voltage from the positive voltage generation circuit 521 or the negative voltage generation circuit 522 according to the AC timing signal from the display control device 510 and outputs it to the drain driver 530.

The common electrode (counter electrode) voltage generation circuit 523 supplies the drive voltage to be applied to the common electrode, and the gate electrode voltage generation circuit 524 uses the thin film transistor (TFT).
Drive voltage to be applied to the gate of.

FIG. 7 is a timing chart of the display control signals from the main computer shown in FIG. 6 and the display control signals generated by the display control device 510.

When the display timing signal is input, the display control device 510 determines that this is the display start position, outputs a start pulse via the signal line 532, and receives the received display data of a simple column. The data is output to the drain driver 530 via the data bus 533.

At this time, a clock (D2) is also output as a latch clock of the drain driver 530 via the signal line 531.

In this case, the display data from the main body computer is transferred in unit of one pixel, that is, each data of red (R), green (G), and blue (B) is made into one group and transferred every unit time. .

Here, the display data is composed of 12 bits of 4 bits for each color or 18 bits of 6 bits for each color.

In this case, the carry output of the preceding stage of the drain driver 530 is directly applied to the drain driver 5 of the next stage.
This carry signal controls the latching operation of the data latch unit of the drain driver 530 to prevent erroneous display data from being written in the data latch unit.

Further, the display control device 510 determines that one horizontal display data is completed when the input of the display timing signal is completed or when a predetermined fixed time has elapsed after the display timing signal is inputted. , A clock (D1) which is a display control signal for outputting the display data stored in the latch circuit of the drain driver 530 to the drain line of the thin film transistor (TFT).
Is output to the drain driver 530 via the signal line 531.

Further, the display control device 510 sequentially applies a positive bias voltage to each gate signal line (G) of the TFT liquid crystal display panel (TFT-LCD) every horizontal scanning time based on the horizontal synchronizing signal. Thus, the clock (G1) which is a shift clock of one horizontal scanning time period is output to the gate driver 540 through the signal line 541.

As a result, the TFT liquid crystal display panel (TF
A plurality of thin film transistors (TFTs) connected to each gate signal line (G) of the T-LCD) are conductive for one horizontal scanning time.

Furthermore, when the first display timing signal is input after the vertical synchronizing signal is input, the display control device 510 determines that this is the first display line and determines that it is the first display line, and the gate driver via the signal line 541. A frame start instruction signal is output to 540.

Further, the display control device 510 uses an AC timing signal for alternating the drive voltage applied to the liquid crystal layer at regular intervals so that the same voltage (DC voltage) is not applied to the liquid crystal layer for a long time. Is output to the power supply unit 520.

Here, alternating current means that the drain driver 530 is based on the drive voltage of the common electrode (counter electrode).
It means that the gradation reference voltage input to the pixel electrode, that is, the drive voltage applied to the pixel electrode of the liquid crystal layer is changed to the positive voltage side / negative voltage side at regular intervals.

[0030]

Generally, when the same voltage (DC voltage) is applied to the liquid crystal layer for a long time, the inclination of the liquid crystal layer is fixed, and as a result, an afterimage phenomenon is caused and the life of the liquid crystal layer is increased. Will be shortened.

In order to prevent this, in the conventional liquid crystal display device, like the TFT type liquid crystal display module shown in FIG. 6, the drive voltage applied to the liquid crystal layer is switched to an alternating current at a constant time interval. I have to.

Although various methods are known as the alternating current method, the most frequently used method is the alternating current method every one frame time unit and every one line time unit. .

FIG. 8 is a diagram showing a circuit configuration of an example of an alternating timing signal generating circuit of the type that performs alternating current for each line time unit and each frame time unit.

In FIG. 8, 601, 602 and 603 are D-type flip-flop circuits, 604 is a NOR circuit and 60
Reference numeral 5 is an exclusive OR circuit, and 606 is an RS flip-flop circuit.

In the AC timing signal generating circuit shown in FIG. 8, the D-type flip-flop circuit 601 has its inverting output terminal (bar Q) and data input terminal (D) connected to each other.・ Flop circuit 60
Every time a vertical synchronizing signal is input to the first clock input terminal (CK), the output terminal (Q) alternately outputs "H level" or "L level".

Further, the D-type flip-flop circuit 602
Output terminal (Q) and the output terminal (Q) output of the RS flip-flop circuit 606 are NOR circuits 604.
And the output of the NOR circuit 604 is input to the data input terminal (D) of the D-type flip-flop circuit 602.

Since the vertical synchronizing signal is input to the set terminal of the RS flip-flop circuit 606, the RS flip-flop circuit 606 receives the vertical synchronizing signal when the vertical synchronizing signal is input.
The flop circuit 606 outputs "H level" from its output terminal (Q), and the output of the NOR circuit 604 is "L level".
Becomes

Therefore, when the first display timing signal is input to the clock input terminal (CK) of the D-type flip-flop circuit 602 after the vertical synchronizing signal is input, the D-type flip-flop circuit 602 of the D-type flip-flop circuit 602 is input. The output terminal (Q) becomes "L level", and the output of the inverting output terminal (bar Q) of the D-type flip-flop circuit 602 becomes "H level".

Further, the RS flip-flop circuit 6
06 is a D-type flip-flop circuit 6 at the reset terminal
Since the output of the inverting output terminal (bar Q) of 02 is input, when the inverting output terminal (bar Q) of the D-type flip-flop circuit 602 becomes “H level”, the RS flip-flop circuit 606 is Will be reset.

When the RS flip-flop circuit 606 is reset, it outputs "L level" from its output terminal (Q).

Here, when the "L level" is input to one input terminal of the NOR circuit 604, the output terminal (Q) of the output terminal (Q) of the D-type flip-flop circuit 602 is input to the other input terminal. The inverted output is output from the output terminal.

Therefore, every time the display timing signal is input to the clock input terminal (CK) of the D-type flip-flop circuit 602, "H level" or "L level" is alternately output from the inverting output terminal (bar Q) thereof. Output to.

Further, the D-type flip-flop circuit 601
Of the output terminal (Q) of the D type flip-flop circuit 602 and the output of the inverting output terminal (bar Q) of the D-type flip-flop circuit 602 are input to the exclusive OR circuit 605, and the output of the exclusive OR circuit 605. Is a D-type flip-flop circuit 6
03 data input terminal (D).

In this case, the D-type flip-flop circuit 6
When the output of the output terminal (Q) of 01 is "H level",
The output from the inverting output terminal (bar Q) of the D-type flip-flop circuit 602 is inverted by the exclusive OR circuit 605 and input to the data input terminal (D) of the D-type flip-flop circuit 603. When the output terminal (Q) of the D-type flip-flop circuit 601 is at “L level”, the output from the inverting output terminal (bar Q) of the D-type flip-flop circuit 602 is the same as that of the D-type flip-flop circuit. The data is input to the data input terminal (D) of the circuit 603.

Further, the D-type flip-flop circuit 603
Outputs an AC timing signal from its output terminal (Q) every time a clock synchronized with the drain driver is input to its clock input terminal (CK).

Therefore, in the alternating timing signal generating circuit shown in FIG. 8, every time the display timing signal is input to the clock input terminal (CK) of the D-type flip-flop circuit 602, and when the D-type flip-flop circuit is input.
Each time the vertical synchronizing signal is input to the clock input terminal (CK) of the flop circuit 601, the AC timing signal changes to “H level” or “L level”.

As described with reference to FIG. 8, in the AC conversion, the AC conversion switching timing is determined based on the display timing signal, the horizontal synchronization signal, and the vertical synchronization signal which are input from the main body computer. are doing.

Further, when the clock from the main body computer is stopped, the clock is not applied to the drain driver 530 and the gate driver 540.

Therefore, if part or all of the clock, display timing signal, horizontal synchronizing signal, and vertical synchronizing signal control signals from the main computer are stopped, the internal circuits of the liquid crystal display device will not operate normally, The drive voltage or the timing signal for driving the liquid crystal layer of the liquid crystal display panel (TFT-LCD) is not generated.

As a result, the liquid crystal display panel (TFT-L
The liquid crystal layer of (CD) cannot be driven by alternating current, and a direct current component is strongly applied to the liquid crystal layer. As a result, an afterimage phenomenon occurs in the liquid crystal display panel (TFT-LCD).
There is a problem that the life of the liquid crystal layer is shortened.

Further, when each control signal input from the main body computer is abnormally input, for example, when the timing is considerably shorter than the original timing, the drive timing for driving the liquid crystal layer becomes abnormal, and the liquid crystal display panel (TFT-
No image is displayed on the LCD, and the alternating cycle is different, resulting in the afterimage phenomenon in the liquid crystal layer and shortening the life of the liquid crystal layer. .

Therefore, among the conventional liquid crystal display devices,
A counter circuit is provided inside the display control device 510, and when a vertical synchronizing signal and a horizontal synchronizing signal are not input from the main body computer, a dummy vertical synchronizing signal is used by utilizing the overflow (carry up) of the counter circuit. It is also known to generate a horizontal synchronizing signal.

However, even in the conventional liquid crystal display device that generates the dummy vertical synchronizing signal and horizontal synchronizing signal, the liquid crystal display panel (TFT-LCD) is also provided.
No processing is performed on the stop of the clock, which is the core of the driving of the control signal, or the stop of other control signals.

Moreover, no processing is performed when the control signals input from the main body computer to the liquid crystal display device have an abnormal timing.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a liquid crystal display device in which a control signal input from a main body computer indicates a stop or an abnormal input. It is an object of the present invention to provide a technique capable of preventing a direct current voltage from being applied to the liquid crystal layer when the temperature becomes low.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0057]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

(1) In the liquid crystal display device comprising display control means for displaying an image on the liquid crystal display panel by controlling the voltage applied to the liquid crystal layer based on the clock input from the main body computer, the liquid crystal display control means Is an internal clock generation circuit for generating an internal clock, a clock stop detection means for detecting stop of a clock input from the main body computer, a clock input from the main body computer and an internal output from the internal clock generation circuit. The clock and the clock are input, the clock input from the main body computer is always selected and output, and the internal clock is selected and output when the clock stop detection unit detects the stop of the clock input from the main body computer. And an internal clock selecting means for performing the same.

(2) In the liquid crystal display device, including the display control means for displaying an image on the liquid crystal display panel by controlling the voltage applied to the liquid crystal layer based on the control signal input from the main body computer, the liquid crystal display control An internal control signal generation circuit for generating an internal control signal, a control signal stop / abnormal input detection means for detecting a control signal stop or an abnormal input input from the main body computer, and an input from the main body computer. Control signal and an internal control signal output from the internal control signal generation circuit are input, and the control signal input from the main body computer is always selected and output. When the control signal input from the computer is stopped or an abnormal input is detected, the internal control signal is selected and output Characterized in that it comprises an internal control signal selecting means that.

[0060]

According to the above-mentioned (1) means, in the liquid crystal display device to which the clock is inputted from the main computer, the internal clock generating circuit for generating the internal clock is provided, and the clock input from the main computer by the clock stop detecting means When the stop of is detected, the internal clock selecting means selects and outputs the internal clock.

As a result, even when the clock from the main body computer is stopped, the voltage applied to the liquid crystal layer can be controlled based on the internal clock, and the direct current is applied to the liquid crystal layer by stopping the clock input from the main body computer. It becomes possible to prevent the voltage from being applied.

According to the above-mentioned (2) means, in the liquid crystal display device to which the control signal is inputted from the main body computer, the internal control signal generating circuit for generating the internal control signal is provided, and the main body is controlled by the control signal stop / abnormality input detecting means. When the control signal input from the computer is stopped or an abnormal input is detected, the internal control signal selecting means selects and outputs the internal control signal.

Thus, even when the control signal from the main body computer is stopped or an abnormal input is made, the voltage applied to the liquid crystal layer can be controlled based on the internal control signal, and the voltage is input from the main body computer. It is possible to prevent the DC voltage from being applied to the liquid crystal layer due to the stoppage of the control signal or abnormal input.

[0064]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a TFT type liquid crystal display module will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

Further, the structure of the TFT type liquid crystal display module described in the following embodiments is the same as the structure of the conventional TFT type liquid crystal display module shown in FIG. 6, and therefore detailed description thereof will be omitted.

[Embodiment 1] In Embodiment 1, an internal clock generating circuit is provided inside the display control device 510 of the liquid crystal display module, and when the clock input from the main computer to the liquid crystal display module is stopped, the display is performed. In this embodiment, the internal clock from the internal clock generation circuit of the controller 510 is used.

FIG. 1 is a diagram showing a circuit configuration of a clock stop detection and a clock switching circuit provided in a display control device 510 in a liquid crystal display module which is an embodiment (embodiment 1) of the present invention. .

In FIG. 1, 101 and 102 are integrating circuits, 111 and 112 are inverters, and 121, 122 and 1
Reference numerals 23 and 124 are NAND circuits, 131 and 132 are Schmitt trigger type inverters, and 140 is an oscillator.

Here, the inverters (122, 123, 1
24) and the inverter 112 form a clock selection circuit.

In the clock stop detection / clock switching circuit shown in FIG. 1, the integration circuit A (101) outputs "H" from the rising edge of the clock input from the main computer.
Detect the "level" period.

When the "H level" period continues for a long time from the rising edge of the clock, the output of the integrating circuit A (101) is fixed to "H level", and this state is judged to be the clock stop state. .

Further, the integrator circuit B (102) detects the "H level" period from the rise of the clock inverted by the inverter 111, so that "L level" from the fall of the clock input from the main computer. Detect the period.

When the "L level" period continues for a long time from the falling edge of the clock, the output of the integrating circuit B (102) is fixed to "H level", and this state is judged to be the clock stop state. To do.

Here, the detection time constant for detecting the stopped state of the clock is approximately τ = CR.

Integration circuit A (101) or integration circuit B
When the output of (102) is fixed to “H level”, the output of the inverter 131 or the inverter 132 becomes “L level” and the “L level” is input to one input terminal of the NAND circuit 121. The NAND circuit 121 is fixed at "H level".

The inverter 131 or the inverter 132 is provided to prevent the influence of noise, and is not necessary when there is no influence of noise. In that case, the integrating circuit A (101) or the integrating circuit A is used. The output of B (102) may be input to the clock selection circuit via the OR circuit.

When the NAND circuit 121 is fixed at "H level", the output of the inverter 112 becomes "L level", and the "L level" is input to one input terminal of the NAND circuit 122. 122 is fixed to "H level", and the clock from the main computer is blocked.

When NAND circuit 121 and NAND circuit 122 are fixed at "H level", the internal clock from oscillator 140, which is an internal clock generation circuit, causes NAND circuit 123 and NAND circuit 124 to operate. It is output through.

If the clock from the main body computer returns to normal after the clock from the main body computer has stopped, the output of the integrating circuit A (101) or the integrating circuit B (102) becomes "L level". Thus, the clock selection circuit selects the clock from the main computer.

The clock selection circuit is not limited to the circuit configuration shown in FIG. 1, and a multiplexer or a clock selection circuit having the circuit configuration shown in FIG. 2 can be used.

In the clock selection circuit shown in FIG. 2A, the AND circuit 15 inputs the clock from the main computer and the output of the NAND circuit 121 inverted by the inverter 111.
1, the output from the oscillator 140 and the output of the NAND circuit 121 are input to the AND circuit 152, and the output of the AND circuit 151 and the output of the AND circuit 152 are input to the OR circuit 161. It is the one.

Further, the clock selection circuit shown in FIG. 2A uses the clock from the main computer and the NAND circuit 1
21 is input to the NOR circuit 171, and the output from the oscillator 140 and the output of the NAND circuit 121 inverted by the inverter 111 are input to the NOR circuit 172. Further, the output of the NOR circuit 171 and the output of the NOR circuit 171 are input. The output of the circuit 172 is input to the NOR circuit 173.

According to the first embodiment, even when the clock from the main body computer is stopped, the TFT type liquid crystal display panel (TFT-LCD) can be driven based on the internal clock, and the input from the main body computer is possible. It is possible to prevent application of a DC voltage to the liquid crystal layer by stopping the generated clock.

[Embodiment 2] In Embodiment 2, an internal horizontal synchronizing signal generating circuit is provided inside the display control device 510 of the liquid crystal display module so that the horizontal synchronizing signal input from the main body computer to the liquid crystal display module is stopped. Alternatively, it is an embodiment in which the internal horizontal synchronizing signal from the internal horizontal synchronizing signal generating circuit of the display control device 510 is used when an abnormality occurs.

FIG. 3 shows another embodiment (second embodiment) of the present invention.
Display control device 510 in the liquid crystal display module
FIG. 3 is a diagram showing a circuit configuration of a horizontal synchronization signal stop / abnormal input detection circuit and an internal horizontal synchronization signal generation circuit which are provided inside.

In FIG. 3, 201 is a delay circuit, 2
11 and 212 are counter circuits, 231 is the number of clocks in one horizontal time, 241 is a decode circuit, 251 is a comparison circuit,
261 is an OR circuit, and 271 is a multiplexer.

In the circuit shown in FIG. 3, the counter circuit 2
Reference numeral 11 counts the clocks input from the main body computer, and is cleared by the horizontal synchronizing signal delayed by the delay circuit 201.

When the horizontal synchronizing signal is not input, the counter circuit 211 is in an overflow state, cleared, and outputs a carry signal.

When the horizontal synchronizing signal is input, the register 221 holds the counter value of the counter circuit 211.

Further, the counter circuit 212 counts the clocks input from the main body computer and outputs the count value to the decoding circuit 241.

When the counter circuit 212 reaches the predetermined number of counts, the count value is cleared to zero.

The decoding circuit 241 is the counter circuit 21.
When the count value from 2 becomes equal to or larger than a predetermined count value, an "H level" signal, that is, an internal horizontal synchronizing signal is output.

First, in the second embodiment, the case where the horizontal synchronizing signal is not input from the main body computer to the liquid crystal display module will be described.

As described above, when the horizontal synchronizing signal is not input, the counter circuit 211 is in the overflow state, and when the counter circuit 211 is in the overflow state, it is determined that the horizontal synchronizing signal is stopped.

When it is judged that the horizontal synchronizing signal is stopped,
The carry signal accompanying the overflow of the counter circuit 211 is input to the OR circuit 261 and is output from the multiplexer 271 as a dummy horizontal synchronizing signal.

Next, in the second embodiment, the case where the horizontal synchronizing signal input from the main body computer to the liquid crystal display module is an abnormal input will be described.

The value (a) of the register 221 and the ROM
Number of clocks per horizontal time (b)
And are compared by the comparison circuit 251.

Here, the number of clocks per horizontal time (b) is the number of display pixels per line, for example.

When the comparison result of the comparison circuit 251 is a = b or a> b, the comparison result of the comparison circuit 251 a <
b becomes "L level", and the multiplexer 271 selects the horizontal synchronizing signal from the main body computer that has passed through the OR circuit 261.

When the comparison result of the comparison circuit 251 is a <b, the comparison result a <b of the comparison circuit 251 becomes "H level", and the multiplexer 271 blocks the horizontal synchronizing signal from the main computer and the decoding circuit The internal horizontal sync signal from 241 is selected.

When the horizontal synchronizing signal from the main body computer is restored to normal after the horizontal synchronizing signal from the main body computer is stopped or abnormally input, the comparison result a <b of the comparison circuit 251 is "L". Level ”,
As a result, the multiplexer 271 selects the horizontal synchronizing signal from the main computer.

In the circuit shown in FIG. 3, it is assumed that the internal horizontal synchronizing signal does not maintain the relationship with the input display timing signal. Therefore, the display timing signal is also generated inside the display control device 510. You may

When the carry signal accompanying the overflow of the counter circuit 211 and the output when the comparison result of the comparison circuit 251 is a <b are input to the OR circuit and the horizontal synchronizing signal is stopped. And the decoder circuit 241
The internal horizontal synchronization signal from the above may be output from the multiplexer 271.

Further, the comparison result in the comparison circuit 251 is a
Even when> b, the horizontal synchronizing signal from the main body computer may be blocked and the internal horizontal synchronizing signal from the decoding circuit 241 may be selected.

According to the second embodiment, even if the horizontal synchronizing signal from the main body computer is stopped or an abnormal input is made, the TFT type liquid crystal display panel (TFT-LCD) is operated based on the internal horizontal synchronizing signal. It becomes possible to drive, and it is possible to prevent the direct current voltage from being applied to the liquid crystal layer due to the stop or abnormal input of the horizontal synchronizing signal input from the main body computer.

[Third Embodiment] In the third embodiment, an internal vertical synchronizing signal generation circuit is provided inside the display control device 510 of the liquid crystal display module so that the vertical synchronizing signal input from the main computer to the liquid crystal display module is stopped. Alternatively, it is an embodiment in which the internal vertical synchronizing signal from the internal vertical synchronizing signal generating circuit of the display control device 510 is used when an abnormality occurs.

FIG. 4 shows another embodiment of the present invention (third embodiment).
Display control device 510 in the liquid crystal display module
FIG. 3 is a diagram showing a circuit configuration of a vertical sync signal stop / abnormal input detection circuit and an internal vertical sync signal generation circuit provided inside the circuit.

In FIG. 4, 301 is a delay circuit and 3 is a delay circuit.
11, 312 are counter circuits, 331 is the number of clocks in one vertical time, 341 is a decode circuit, 351 is a comparison circuit,
361 is an OR circuit, and 371 is a multiplexer.

In the circuit shown in FIG. 4, the counter circuit 3
Reference numeral 11 counts clocks input from the main body computer and is cleared by the vertical synchronizing signal delayed by the delay circuit 301.

When the vertical synchronizing signal is not input, the counter circuit 311 enters an overflow state, is cleared, and outputs a carry signal.

When the vertical synchronizing signal is input, the register 321 holds the counter value of the counter circuit 311.

Further, the counter circuit 312 counts clocks input from the main body computer and outputs the count value to the decoding circuit 341.

Here, when the counter circuit 312 reaches the predetermined number of counts, the count value is cleared to zero.

The decoding circuit 341 is the counter circuit 31.
When the count value from 2 becomes a predetermined count value or more, an "H level" signal, that is, an internal vertical synchronization signal is output.

First, in the third embodiment, the case where the vertical synchronizing signal is not input from the main body computer to the liquid crystal display module will be described.

As described above, when the vertical synchronizing signal is not input, the counter circuit 311 is in the overflow state, and when the counter circuit 311 is in the overflow state, it is judged that the vertical synchronizing signal is stopped.

When it is judged that the vertical synchronizing signal is stopped,
The carry signal accompanying the overflow of the counter circuit 311 is input to the OR circuit 361, and is output from the multiplexer 371 as a dummy vertical synchronization signal.

Next, in the third embodiment, the case where the vertical synchronizing signal input from the main body computer to the liquid crystal display module is an abnormal input will be described.

The value (a) of the register 321 and the ROM
The number of lines (b) per one display screen (frame) stored in, for example, is compared by the comparison circuit 351.

When the comparison result of the comparison circuit 351 is a = b or a> b, the comparison result of the comparison circuit 351 is a <
b becomes "L level", and the multiplexer 371 selects the vertical synchronizing signal from the main body computer that has passed through the OR circuit 361.

When the comparison result of the comparison circuit 351 is a <b, the comparison result a <b of the comparison circuit 351 becomes "H level", and the multiplexer 371 blocks the vertical synchronizing signal from the main computer and the decoding circuit The internal vertical sync signal from 341 is selected.

When the vertical synchronizing signal from the main body computer returns to normal after the vertical synchronizing signal from the main body computer is stopped or abnormally input, the comparison result a <b of the comparison circuit 351 is "L". Level ”,
As a result, the multiplexer 371 selects the vertical synchronizing signal from the main computer.

When the carry signal accompanying the overflow of the counter circuit 311 and the output when the comparison result in the comparison circuit 351 is a <b are input to the OR circuit and the vertical synchronizing signal is stopped. The multiplexer 37
1 may select the internal vertical synchronizing signal from the decoder circuit 341.

Further, the comparison result in the comparison circuit 351 is a
Even when> b, the horizontal synchronizing signal from the main body computer may be blocked and the internal horizontal synchronizing signal from the decoding circuit 241 may be selected.

According to the third embodiment, even if the vertical synchronizing signal from the main body computer is stopped or an abnormal input is made, the TFT type liquid crystal display panel (TFT-LCD) is operated based on the internal vertical synchronizing signal. It becomes possible to drive, and it becomes possible to prevent the DC voltage from being applied to the liquid crystal layer due to the stop or abnormal input of the vertical synchronizing signal input from the main body computer.

[Fourth Embodiment] In the fourth embodiment, an internal display timing signal generation circuit is provided inside the display control device 510 of the liquid crystal display module, and the display timing signal input from the main computer to the liquid crystal display module is stopped. Alternatively, it is an embodiment in which the internal display timing signal from the internal display timing signal generation circuit of the display control device 510 is used when an abnormality occurs.

FIG. 5 shows another embodiment (fourth embodiment) of the present invention.
Display control device 510 in the liquid crystal display module
Display timing signal stop provided inside
It is a figure which shows the circuit structure of an abnormal input detection circuit and an internal display timing signal generation circuit.

In FIG. 5, 401 and 402 are delay circuits, 411, 412, 413 and 414 are counter circuits, 431 is the number of display pixels per horizontal line, 432.
Is the number of display lines per display screen, 441 and 442 are decode circuits, 451 and 452 are comparison circuits, 461 is an OR circuit, 471 is a multiplexer, 481 and 482 are AND circuits, and 491 and 492 are inverters.

In the circuit shown in FIG. 5, the display timing signal and clock from the main computer are
The AND circuit 481 inputs the counter circuit 411,
The output of the AND circuit 481 is counted, and the delay circuit 4
It is cleared by the horizontal synchronizing signal delayed by 01.

Further, the counter circuit 412 counts the display timing signal inputted from the main body computer and is cleared by the vertical synchronizing signal delayed by the delay circuit 402.

The register 421 holds the counter value of the counter circuit 411 when the horizontal synchronizing signal is input, and the register 422 stores the counter value of the counter circuit 412 when the vertical synchronizing signal is input. Hold.

The counter circuit 413 counts clocks input from the main body computer and outputs the count value to the decoding circuit 441.

The decoding circuit 441 is the counter circuit 41.
When the count value from 3 becomes a predetermined count value or more, the "H level" signal is output.

The counter circuit 414 counts the horizontal synchronizing signal input from the main body computer and outputs the count value to the decoding circuit 442.

The decoding circuit 442 is the counter circuit 41.
When the count value from 4 becomes a predetermined count value or more, the "H level" signal is output.

The output of the decode circuit 441 and the output of the decode circuit 442 are input to the AND circuit 481, and the output of the AND circuit 481 becomes the internal display timing signal.

Here, the counter circuits 411, 412, 4
When the counts 13, 414 reach the predetermined count number, the count value is cleared to 0.

First, in the fourth embodiment, a case where the display timing signal is not input from the main body computer to the liquid crystal display module will be described.

When the display timing signal is not input from the main body computer to the liquid crystal display module, for example, the value of the counter circuit 412 becomes 0, and it is judged that the display timing signal is stopped.

In this case, the value of the register circuit 422 also becomes 0, and the value of the register 422 (A) and the number of display lines per display screen (B) stored in the ROM or the like.
Comparing and with the comparison circuit 451, the comparison result is A
<B.

Therefore, the comparison result A of the comparison circuit 452 is
= B becomes "L level", the output of the inverter 492 becomes "H level", and the multiplexer 471 selects the internal display timing signal generated by the decoding circuit 441 and the decoding circuit 442.

Next, in the fourth embodiment, the case where the display timing signal input from the main body computer to the liquid crystal display module is an abnormal input will be described.

When the length of the display timing signal (the number of display pixels in the horizontal direction) is abnormal, the register 42 is used.
When the value (a) of 1 and the number of display pixels per display line (b) stored in the ROM or the like are compared by the comparison circuit 451, the comparison result is a <b or a> b.

Therefore, the comparison result path a = b of the comparison circuit 451 is "L level", and the output of the inverter 491 is "H".
Level ”, and the multiplexer 471 selects the internal display timing signal generated by the decoding circuit 441 and the decoding circuit 442.

When the number of pulses of the display timing signal (the number of display lines in the vertical direction) is abnormal, the value (A) of the register 422 and the display lines per display screen stored in the ROM or the like. When the number (B) is compared with the comparison circuit 451, the comparison result is A <B or A
> B.

Therefore, the comparison result path A = B of the comparison circuit 452 is "L level", and the output of the inverter 492 is "H".
Level ”, and the multiplexer 471 selects the internal display timing signal generated by the decoding circuit 441 and the decoding circuit 442.

When the display timing signal from the main body computer returns to normal after the display timing signal from the main body computer stops or becomes an abnormal input, the comparison result path a = b of the comparison circuit 451, and , Comparison result path A of the comparison circuit 452 =
Both B are at "H level" and the outputs of the inverters 491 and 492 are both at "L level", whereby the multiplexer 471 selects the display timing vertical synchronization signal from the main computer.

According to the fourth embodiment, even if the display timing signal from the main body computer is stopped or an abnormal input is made, a TFT type liquid crystal display panel (TFT-
It becomes possible to drive the LCD), and to prevent a DC voltage from being applied to the liquid crystal layer due to the stop or abnormal input of the display timing signal input from the main body computer.

Each of the above-described embodiments is a quasi-recovery process in a malfunction, and this process causes an abnormal display of an image displayed on the TFT liquid crystal display panel (TFT-LCD) as compared with a normal display image. Certainly it will be an image.

However, this abnormal display image makes it possible for the user to know that the control signal from the main body computer is abnormal, and the user can promptly take corrective action.

In each of the above embodiments, the present invention is applied to the TFT.
However, the present invention is not limited to this.
It goes without saying that it can be applied to all liquid crystal display devices such as an N (Super Twisted Nematic) type liquid crystal display module.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0154]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, even if the clock, the display timing signal, the horizontal synchronizing signal, and the vertical synchronizing signal, which are input from the main computer, are stopped or abnormally input, the liquid crystal display device can be operated. Since the respective internal control signals corresponding to the respective control signals are internally generated, it is possible to always apply an alternating drive voltage to the liquid crystal layer.

As a result, it is possible to prevent the direct current voltage from being applied to the liquid crystal layer due to the stoppage or abnormal input of each control signal input from the main body computer.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a clock stop detection / clock switching circuit provided inside a display control device 510 in a liquid crystal display module which is an embodiment (Embodiment 1) of the present invention.

FIG. 2 is a diagram showing another circuit configuration of the selection circuit shown in FIG.

FIG. 3 is a horizontal sync signal stop / abnormal input detection circuit provided inside a display control device 510 in a liquid crystal display module which is another embodiment (second embodiment) of the present invention;
It is a figure which shows the circuit structure of an internal horizontal synchronizing signal generation circuit.

FIG. 4 is a vertical sync signal stop / abnormal input detection circuit provided inside a display control device 510 in a liquid crystal display module which is another embodiment (third embodiment) of the present invention;
It is a figure which shows the circuit structure of an internal vertical synchronizing signal generation circuit.

FIG. 5 illustrates a display timing signal stop / abnormality input detection circuit and an internal display timing signal generation circuit provided inside a display control device 510 in a liquid crystal display module that is another embodiment (Embodiment 4) of the present invention. It is a figure which shows a circuit structure.

FIG. 6 shows a conventional TFT (Thin Film Tran).
3 is a block diagram showing a schematic configuration of a liquid crystal display module of a system).

7 is a diagram showing a timing chart of a display control signal from the main body computer shown in FIG. 6 and a display control signal generated by the display control device 510.

FIG. 8 is a diagram showing a circuit configuration of an example of an AC alternating timing signal generating circuit of an AC system for performing AC conversion for each line time unit and for each frame time unit.

[Explanation of Codes] 101, 102 ... Integrating circuits, 111, 112, 491
492 ... Inverter, 121, 122, 123, 124
... NAND circuit, 131, 132 ... Schmitt trigger type inverter, 140 ... Oscillator, 151, 152, 48
1,482 ... AND circuit, 161,261,361,4
61 ... OR circuit, 171, 172, 173, 604 ... NOR circuit, 201, 301, 401, 402 ... Delay circuit, 211, 212, 311, 312, 411, 41
2, 413, 414 ... Counter circuit, 231, ... Number of clocks in one horizontal time, 241, 341, 441, 442 ... Decode circuit, 251, 351, 451, 452 ... Comparison circuit, 271, 371, 471, 525 ... Multiplexer, 331 ... Number of lines per frame, 431 ... Number of display pixels per horizontal line, 432 ... Number of display lines per display screen, 500 ... Interface section, 510 ... Display control device, 520 ... Power supply section, 521 ... Positive voltage Generating circuit, 522 ... Negative voltage generating circuit, 523 ... Common electrode (counter electrode) voltage generating circuit, 524 ... Gate electrode voltage generating circuit, 530 ... Drain driver, 531, 532, 5
41 ... Signal line, 533 ... Data bus, 540 ... Gate driver, 601, 602, 603 ... D-type flip-flop circuit, 605 ... Exclusive OR circuit, 606 ... RS
Type flip-flop circuit, TFT-LCD ... TFT liquid crystal display panel.

Claims (5)

[Claims] 1. A liquid crystal display device comprising display control means for controlling a voltage applied to a liquid crystal layer on the basis of a clock input from a main body computer to display an image on a liquid crystal display panel. An internal clock generating circuit for generating an internal clock, a clock stop detecting means for detecting stop of a clock input from the main body computer, a clock input from the main body computer and an internal clock output from the internal clock generating circuit Is input, the clock input from the main body computer is always selected and output, and when the clock stop detection means detects the stop of the clock input from the main body computer, the internal clock is selected and output. A liquid crystal display device comprising an internal clock selecting means. 2. A liquid crystal display device comprising display control means for displaying an image on a liquid crystal display panel by controlling a voltage applied to a liquid crystal layer based on a control signal inputted from a main body computer. , An internal control signal generation circuit for generating an internal control signal, a control signal stop / abnormal input detection means for detecting a stop or an abnormal input of a control signal input from the main body computer, and an input from the main body computer A control signal and an internal control signal output from the internal control signal generation circuit are input, and a control signal input from the main body computer is constantly selected and output, and the main body is detected by the control signal stop / abnormality input detection means. Stops the control signal input from the computer, or selects and outputs the internal control signal when an abnormal input is detected. A liquid crystal display device comprising: a unit control signal selection unit. 3. The liquid crystal display device according to claim 2, wherein the control signal is a horizontal synchronizing signal. 4. The liquid crystal display device according to claim 2, wherein the control signal is a vertical synchronization signal. 5. The liquid crystal display device according to claim 2, wherein the control signal is a display timing signal.