JP2011123163A - Signal processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that there are many factors in which circuit scale like a multiplier and a multiplexor is increased in digital operation performed by gammer correction of a digital system, and since operation by block is performed, increase in power consumption cannot be avoided. <P>SOLUTION: A signal processing circuit has a memory holding gammer correction data, an address signal, a control circuit outputting a signal switching read or write of a memory, a switching circuit switches a video signal or an address signal and inputting it to the memory, and a correction data calculating circuit calculating gammer correction data using the address signal and gammer correction parameters and outputting it to the memory; a memory is set to a read mode during a display period, a video signal is input to the memory, a signal read out from the memory is sent to a display device, the memory is set to a write mode during a display stop period, an address signal is input to the memory, and gammer correction data is written. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a signal processing device used for a display device.

  In an active matrix display device, a driver IC mounted on the display device is required to have a smaller circuit size as the size of the driver IC is reduced and the cost is reduced.

  In the display device, input image data is converted through a gamma correction circuit in order to display an optimum image. For gamma correction, a method of reading output data stored in a memory in accordance with input digital image data is often employed.

  In the case of color display, the optimum output of the gamma correction circuit varies depending on the color. The input image data is converted according to the predetermined contrast and brightness for each color for white balance adjustment to eliminate white display coloring and brightness adjustment for each color, and then gamma correction is performed. The circuit is entered and the output is read out.

  In Patent Document 1, input data is subjected to contrast processing for each RGB, and a certain level is added or subtracted according to the luminance of the entire image, and then input to a memory to read a γ correction output.

Japanese Patent Laid-Open No. 10-198307

  However, in order to convert the input video data into different video data according to the contrast and the luminance, a circuit such as a multiplier or a multiplexer is required, and a space for this must be provided. Furthermore, since the two steps of input data conversion and memory reading are executed, an increase in power consumption cannot be avoided.

  An object of the present invention is to provide a signal processing circuit including a gamma correction circuit that suppresses power consumption with a simple circuit.

  In order to solve the above-described problems, the present invention provides a signal processing circuit that performs gamma correction on a video signal and outputs the video signal to a display device, the memory storing gamma correction data, an address signal of the memory, and the memory. A control circuit that outputs a switching signal for switching between a reading mode and a writing mode; an input switching circuit that switches the video signal and the address signal according to the switching signal and inputs the signal to the memory; and holds a gamma correction parameter; A correction data calculating circuit that receives the address signal, calculates the gamma correction data using the gamma correction parameter, and outputs the calculated data to the memory, and the memory reads out during the display period of the display device Mode, the input switching circuit inputs the video signal to the memory, and the memory When the signal read from the memory is sent to the display device and the display device stops displaying, the memory is set to the write mode, and the input switching circuit inputs the address signal to the memory. The signal processing circuit is characterized in that the gamma correction data is written in the memory.

  In the signal processing circuit according to the present invention, when the display of the display device is stopped, only the process of writing the gamma correction data into the memory is performed. Only process to output to. As a result, the circuit scale can be reduced.

It is a block diagram of the driver IC of the present invention. It is an example of the gamma correction circuit of this invention. It is the figure which showed the broken line gamma characteristic. It is a timing chart which shows operation | movement of this invention.

  Examples of the present invention will be described below.

  FIG. 1 shows a data signal generation circuit of a display device including a signal processing circuit according to the present invention, which comprises a digital signal processing unit 1 and an analog signal conversion unit 2.

  In FIG. 1, the clock input to the digital signal processing unit 1 is input to all blocks in the driver IC that require the clock.

  In the RGB serial data (N), which is an N-bit color video signal input to the digital signal processing unit 1, RGB digital information is transmitted in time series. The resolution conversion circuit 3 detects RGB serial data (N) and performs conversion processing of the RGB serial data (N) in accordance with the resolution of the display device. The parallel data separation circuit 4 separates the RGB serial data (N) after the resolution conversion processing into video signals of respective colors of R data (N), G data (N), and B data (N).

  The RGB video signals are respectively input to the gamma correction circuit 5 and subjected to gamma conversion in accordance with the characteristics of the display element, and the peak luminance information for each color is superimposed on the white balance adjustment. The gamma correction circuit 5 performs gamma correction including correction by peak luminance. Details of the gamma correction circuit 5 will be described later.

  The RGB color video signals after the gamma correction are selectively stored in the register 6 by selection pulses sequentially output from the digital signal processing circuit 9. In FIG. 1, the data lines connecting the gamma correction circuit 5 and the register 6 are used for each color of RGB × column, but the configuration is such that one row of data lines supplies video signals for each color in a time division manner. It can be changed to various methods depending on the TFT circuit configuration inside the display panel.

  Output from the gamma correction circuit 5 is digital data corresponding to a voltage signal applied to each pixel of the display device. The RGB color-gamma-corrected video signals are stored in the register 6 and then input to the analog signal converter 2, converted into analog voltages by the D / A converter 7, and amplified by the AMP circuit 8. Data_r1, data_g1, data_b1,..., Data_rn, data_gn, and data_bn are output to the signal wiring on the column control side of the display area connected to the output pad.

  The digital signal processing circuit 9 receives a horizontal synchronization signal and a vertical synchronization signal, and generates a logic pulse that can drive the display screen. For example, when the row control circuit in the display area is implemented by TFTs, a reset pulse, a clock pulse, a start trigger, and the like of the shift register are generated. Various pulses output from the digital signal processing unit 1 are amplified to an amplitude signal at which the TFT operates in the AMP circuit 8 of the analog signal conversion unit 2, and s0, s1,. x is an integer).

  FIG. 2 shows a gamma correction circuit used in the signal processing circuit of this embodiment.

  In the signal processing circuit of the present invention, gamma correction including white balance adjustment is performed by a lookup table method.

  The look-up table is stored in a RAM memory (hereinafter simply referred to as “memory”) 10. The memory 10 is provided with a multiplexer 15 as an input switching circuit on the address side, and switches the video signals video_in [N] and w_address [N] to connect to the address terminals A1-AN of the memory 10. On the output side, a selector 16 is provided as an output switching circuit for switching the connection destination of the data terminals D 1 -DN of the memory 10.

  The control circuit 18 outputs an address signal w_address [N] and an access signal R / W. The access signal R / W is input to the memory 10 and sets the memory 10 to the read mode or the write mode. The access signal R / W is also input to the multiplexer 15 and the selector 16 to set these operation modes.

  When the display device performs display, the access signal R / W is output as L from the control circuit 18. At this time, the multiplexer 15 is selected so that the input data video_in [N] is input to the address terminals A 1 -AN of the memory 10. On the other hand, the data terminals D1-DN are in the output mode, and the selector 16 selects the display device and outputs data. The memory 10 enters the read mode.

  The N-bit video signal video_in [N] is input to the address terminal A1-AN of the lookup table held in the memory 10, and the data video_out [N] held at the corresponding address is read from the data terminals D1-DN. It is. As a result, the input video signal is gamma corrected and sent to the display device.

  The look-up table is rewritten within a period during which the display device stops displaying. During the display stop period, the access signal R / W is output as H from the control circuit 18 and the memory 10 enters the write mode. At the same time, the control circuit 18 outputs the address w_address [N] of the lookup table to the address terminals A 1 -AN and the correction data calculation circuit 12 of the memory 10.

  The multiplexer 15 connects the address signal w_address [N] output from the control circuit 18 to the address terminals A 1 -AN of the memory 10.

  The data buffer is in the input state at the output interface of the memory 10 in the write mode. Since the data terminals D1-DN are in the input mode, the selector 16 connects the data terminals D1-DN to the correction data calculation circuit 12.

  The correction data calculation circuit 12 calculates correction data w_data [N] corresponding to the input w_address [N], outputs the correction data w_data [N] to the memory 10, and this is written to the corresponding address in the lookup table.

  When the data writing for one address is completed, the address w_address [N] is incremented, and the correction data w_data [N] is calculated and written to the memory 10 in the same manner. Thereafter, all addresses in the lookup table are sequentially output, and writing of all data in the lookup table is completed.

  In addition, the signal processing circuit of the present invention preferably has a lookup table for each video signal of two or more different colors. Furthermore, it is preferable that at least one of the look-up tables provided for each video signal of a different color is different from the other look-up tables in the video signal output according to the input video signal. This can be realized, for example, by changing the calculation method of the gamma correction value for each color or changing the coefficient for luminance adjustment corresponding to the gamma correction value for each color.

  FIG. 4 is a timing chart showing the operation of the signal processing circuit of this embodiment.

  As shown in FIG. 4, when the display device is not displayed, the memory 10 is in a writing state and correction data can be written. Further, the memory 10 is in a read state during display on the display device.

  The correction data calculation circuit 12 includes a conversion circuit 17 and a peak luminance adjustment circuit 11.

The conversion circuit 17 is a circuit that obtains an output by linearly converting input data with a broken line as shown in FIG. The coordinate values ((x0, y0) to (x4, y4)) of the break points (1) to (5) are input in advance to the conversion circuit 17 as the gamma correction parameter param. These parameters are specific points selected from an ideal gamma correction curve and are designed to approximate the ideal gamma correction. The conversion circuit 17 calculates the corresponding y _out by the following expression, where the address signal w_address [N] is x _in , and outputs the calculated value to the peak luminance adjustment circuit 11.

In a specific procedure, first, it is determined in which region between the break points (1) to (5) the value of x _in is, and the value of n is determined. Based on the value of n, x _n−1 , y _n−1 , x _n , and y _n are selected from the parameter param, and the difference x _in −x _n−1 and the slope (y _n −y _n−1 ) / (x _n − x _n-1 ) is obtained. After multiplying the difference and the slope, yn _-1 is added and the result is taken as _yout .

The peak luminance adjustment circuit 11 performs multiplication of the peak brightness parameter brightness prepared in advance for each input value y _out and color, and outputs it as correction data w_data [N]. The peak luminance parameter is determined by the ratio of the maximum luminance of each color of R, G, and B in order to achieve white balance.

  The obtained correction data w_data [N] and the corresponding address signal w_address [N] are input to the memory 10 at the timing when the R / W signal becomes H (write mode), and the data is written to the corresponding address. .

Next, the address signal w_address [N] output from the control circuit 18 is updated, and the address increased by one is input to the conversion circuit 17. The conversion circuit 17 sets this as x _in and calculates y _out by the same procedure. Further, the peak luminance adjustment circuit 11 multiplies the peak luminance parameter as a coefficient to obtain correction data w_data [N]. This result is written to a new address in the memory 10.

  Thereafter, this operation is repeated, and the address signal w_address [N] changes over all gradation levels, and the corresponding correction data w_data [N] is written into the memory 10.

  For gamma correction, various functions such as a broken line with five points (x0, y0) to (x4, y4) as shown in FIG. 3 and a curve using a spline function may be used. Any function can be realized by storing the result obtained by multiplying the gamma correction value calculated by each algorithm by the coefficient for peak luminance adjustment in the memory 10.

  In the above description, the gamma correction multiplied by the coefficient for peak luminance adjustment has been described. However, an addition / subtraction function may be added such as performing a gamma correction operation and then adjusting the brightness by adding an offset value.

  In the present invention, the result of brightness adjustment performed by the peak brightness adjustment circuit 11 to the value calculated by the conversion circuit 17 is held in the memory 10. Therefore, the input video data video_in [N] does not need to be subjected to contrast processing or luminance processing before being input to the memory 10, and is input to the memory 10 as it is and converted to output video data.

  If the gamma correction data is formed including the peak luminance information for each color, the gamma-corrected video signal has a white balance. These features simplify the circuit scale and reduce power consumption.

  10: Memory, 11: Peak luminance adjustment circuit, 12: Correction data calculation circuit, 15: Input switching circuit, 16: Output switching circuit, 17: Conversion circuit, 18: Control circuit

Claims (4)

A signal processing circuit for gamma-correcting a video signal and outputting it to a display device,
A memory for holding gamma correction data;
A control circuit for outputting an address signal of the memory and a switching signal for switching the memory between a read mode and a write mode;
In accordance with the switching signal, an input switching circuit that switches the video signal and the address signal to input to the memory;
A correction data calculation circuit that holds a gamma correction parameter, receives the address signal, calculates the gamma correction data using the gamma correction parameter, and outputs the gamma correction data to the memory;
During the display period of the display device, the memory is set to a read mode, the input switching circuit inputs the video signal to the memory, and the signal read from the memory is sent to the display device. ,
The memory is set to a write mode during a period when the display device stops displaying, the input switching circuit inputs the address signal to the memory, and the gamma correction data is written to the memory. Signal processing circuit.   The signal processing circuit according to claim 1, wherein the correction data calculation circuit holds a peak luminance parameter, and calculates the gamma correction data using the peak luminance parameter together with the gamma correction parameter.   The signal processing circuit according to claim 1, wherein the control circuit sequentially changes and outputs the address signals. The memory for each video signal of two or more different colors;
4. The signal processing circuit according to claim 1, wherein at least one of the memories outputs a signal different from that of the other memory in accordance with an input video signal. 5.

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