JP3172450B2 - Image information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information processing apparatus for simulating the display of a predetermined number of gradations or more on a display device for displaying with predetermined bits of image data. The present invention relates to an image information processing apparatus that diffuses an error between frames by alternately performing addition processing or non-addition processing on the least significant bit of each frame.

[0002]

2. Description of the Related Art In recent years, a high-definition color LCD display device for multimedia office automation has been developed. Some color LCDs have a built-in 3-, 4-, 5-, or 6-bit digital driver for each of R, G, and B colors. For example, an LCD with a built-in 3-bit digital driver can display eight gradations of each color, and can display 512 colors in total. However, this is sufficient when used simply as a monitor for OA, but is insufficient for displaying video such as moving images and still images for multimedia, and further increase in gradation is desired. Was rare.

Therefore, a method has been proposed in which the number of gray levels is artificially increased by diffusing image data components that cannot be displayed by one pixel to the same pixel in the next frame (error diffusion between frames). That is, the lower bits of the image data that could not be displayed in the previous frame are stored in the frame memory as error data, and the error data stored in the image data of the same pixel in the next frame is added to obtain the error data. Is spread between frames to obtain a pseudo gradation.

Here, in a still image, the image data of the same pixel is the same in each frame.
When captured in an adjacent frame, it can be captured as a still image, and the image data of the same pixel in the adjacent frame is almost the same. Paying attention to this point, if the above-described inter-frame error diffusion processing is performed when the error data is 1 bit, a carry occurs once every two frames in the image data with the error data of “1”. For example, when processing 4-bit image data into 3-bit display data, the following is performed.

[0005]

[Table 1]

Therefore, in such a case, the operation of alternately adding the least significant bit of the image data to the one upper bit of the image data without holding the error data during one frame is alternately performed. What is necessary is just to perform the operation of addition processing. Thereby, the frame memory can be omitted. FIG. 2 is a block diagram of an image information processing apparatus that processes and outputs 7-bit image data SD into 6-bit display data DG. Of the 7-bit image data SD0 to SD6, the upper 6 bits SD1 to SD6 are applied to one addition input of the adder circuit 1, and the least significant bit SD0 is set to AN.
Applied to one input of D gate 2. The output of the AND gate 2 is applied to the other addition input of the addition circuit 1,
Further, a timing control signal ST is applied to the other input of the AND gate 2. The output of the adding circuit 1 is output to the display device as display data DG0 to DG5.

Therefore, when the timing signal ST is "0", the least significant bit SD0 is not added, and
The addition process is performed at the timing when the timing signal ST is “1”. At this time, if the addition process and the non-addition process are repeated for all the pixels in the same frame, light and dark are generated for each frame, and as a result, flicker occurs. Therefore, in FIG. 2, in the same frame, the addition process and the non-addition process are performed alternately for each pixel in the horizontal direction, and the addition process and the non-addition process are performed alternately for each line. Is inverted for each frame to realize a uniform image display. For this purpose, the timing signal generating circuit 3 for generating the timing signal ST includes a vertical synchronizing signal VSYNC and a horizontal synchronizing signal H.
Dot clock D synchronized with SYNC and image data SD
CLK is applied, and a timing signal ST is created by these signals.

In the example shown in FIG. 2, the image data SD is 7 bits and the display data is 6 bits. However, in the liquid crystal display device, 3 bits, 4 bits, 5 bits and 6 bits are used.
Some have built-in digital drivers such as bits.
In order to support all of these liquid crystal display devices, a circuit corresponding to each case is required as shown in FIG. FIG.
, An adder circuit 4 for processing 4-bit image data into 3-bit display data;
An addition circuit 5 for processing bit display data, an addition circuit 6 for processing 6-bit image data to 5-bit display data, and an addition circuit 7 for processing 7-bit image data to 6-bit display data. Provided, each adding circuit 4,
The outputs 5, 6, and 7 are selected and output by the switching circuit 8.

The image data SD4 to SD6 is applied to one of the addition inputs A0 to A2 of the addition circuit 4, and the output of the AND gate 9 to which the image data SD3 is applied is applied to the other addition input B0. “0” is applied to B1 and B2. The image data SD3 to SD6 is applied to one of the addition inputs A0 to A3 of the addition circuit 5, the output of the AND gate 10 to which the image data SD2 is applied is applied to the other addition input B0, and the addition inputs B1 to B3 are added. Is "0"
Is applied. One of the addition inputs A0 to A4 of the addition circuit 6
, The output of the AND gate 11 to which the image data SD1 is applied is applied to the other addition input B0, and "0" is applied to the addition inputs B1 to B4. One addition input A0 of the addition circuit 7
A5 to which the image data SD1 to SD6 are applied, and the other addition input B0 to which the image data SD0 is applied
The output of the D gate 12 is applied, and "0" is applied to the addition inputs B1 to B5. Also, AND gates 9, 10,
The other input of each of the timing control signals S and
T is applied.

As described above, a plurality of adder circuits are provided to correspond to each of the number of input bits of the liquid crystal display device.
Selected by L1.

[0011]

However, in an image information processing apparatus as shown in FIG.
Even when processing the image input of bits and outputting the display data of 6 bits, the other adders 4, 5, and 6 are also operated, so that the power consumption increases. Also,
When such a device is integrated into a circuit, the number of elements constituting the circuit increases and the chip area increases, resulting in an increase in cost.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned points, and has been developed in order to provide a display with a larger number of gradations than the number of gradations displayed on a display pixel. In the pixel, N is selected by alternately selecting whether to add or non-addition the least significant bit of the (N + 1) -bit image data applied to each frame to the upper N bits of the image data. In the image information processing apparatus for outputting bit display data, the N + 1
An adder circuit to which bit image data is applied to one addition input; and a plurality of gate circuits to which the predetermined lower-order bit of the (N + 1) bits are applied and whose output is applied to the other addition input of the addition circuit. Applying a timing signal for controlling selection between the addition processing and non-addition processing to the plurality of gate circuits, and applying a selection signal for selecting the gate circuit according to the value of N to the gate circuit. It corresponds to a display device having a different number of input bits only by the operation of one adder circuit.

According to the second aspect of the present invention, the (N + 1) -bit image data whose number of bits changes according to the value of N is applied in order from the most significant bit of one of the addition inputs of the addition circuit. By using N bits from the most significant bit of the addition output of the addition circuit as display data, it is possible to make the output of the addition circuit common to display devices having different numbers of bits.

[0014]

FIG. 1 is a block diagram showing an embodiment of the present invention. The mode for processing 7-bit image data into 6-bit display data (7-6 mode) and the mode for processing 6-bit image data in 5 bits are shown in FIG. Mode for processing bit display data (6
-5 mode), a mode in which 5-bit image data is processed into 4-bit display data (5-4 mode), and a mode in which 4-bit image data is processed into 3-bit display data (4-mode).
3 mode), which are switchable image information processing apparatuses.

In FIG. 1, an adder circuit 13 includes 6-bit addition inputs A0 to A5, the other 6-bit addition inputs B0 to B5, and 6-bit addition outputs DG0 to DG5.
It has. Input of image data is 7-bit SD0
To SD6. Of the image data input, the upper 6 bits SD1 to SD6 are applied to one of the addition inputs A0 to A5, respectively, and the least significant bit SD0 of the image data input is
Applied to AND gate 14. The image data input SD1 is applied to an AND gate 15, the image data input SD2 is applied to an AND gate 16, and the image data input SD3 is applied to an AND gate 17. A timing signal ST for alternately switching between addition processing and non-addition processing is commonly applied to the AND gates 14, 15, 16, and 17, and selection signals SEL6, SEL5, and SEL4 for selecting each mode are provided. , SEL3
Is applied to each. Further, AND gates 14, 15,
The outputs 16 and 17 are applied to the other addition inputs B0, B1, B2 and B3 of the addition circuit 13, and "0" is applied to the addition inputs B4 and B5.

In FIG. 1, when the 7-6 mode is used, the selection signal SEL6 is set to "1", the other selection signals SEL5, SEL4 and SEL3 are set to "0", and the 7-bit image data is Image data input SD0-S
Apply to D6. As a result, only the AND gate 14 operates, and the timing control signal ST
The signal of the image data input SD0 is alternately switched to AN for each frame.
It is output from the D gate 14 and applied to the addition input B0. Accordingly, in the adder circuit 13, the least significant bit SD0 of the image data is replaced with the upper 6 bits (SD1 to SD1) of the image data.
The data is alternately added to the data of 5). And
Six bits of the addition outputs DG0 to DG5 are used as display data.

When the 6-5 mode is used, the selection signal SEL5 is set to "1" and the other selection signals SEL6,
SEL4 and SEL3 are all set to "0", and 6-bit image data is applied to the image data inputs SD1 to SD6. As a result, only the AND gate 15 operates,
The signal SD1 of the least significant bit of the 6-bit image data is
The signal is alternately applied to the addition input B1 from the AND gate for each frame. Therefore, in the addition circuit 13, the signal SD1 of the least significant bit of the image data is alternately added to the data of the upper 5 bits (SD2 to SD5) of the image data. In this case, the five bits DG1 to DG5 of the addition output are used as display data.

When the 5-4 mode is used, the selection signal SEL4 is set to "1" and the other selection signals SEL6,
SEL5 and SEL3 are set to “0”, and 5-bit image data is applied to the image data inputs SD2 to SD6. As a result, only the AND gate 16 operates, and the least significant bit SD2 of the image data is alternately applied from the AND gate 16 to the addition input B2 for each frame. Therefore,
In the adder circuit 13, the least significant bit signal SD2 of the image data is converted into the upper 4 bits (SD3 to SD3) of the image data.
6) are alternately added to the data for each frame. In this case, the four bits DG2 to DG5 of the addition output are used as display data.

When the 4-3 mode is used, the selection signal SEL3 is set to "1" and the other selection signals SEL6,
SEL5 and SEL4 are set to "0", and 4-bit image data is applied to the image data inputs SD3 to SD6. As a result, only the AND gate 17 operates, and the least significant bit SD3 of the image data is alternately applied from the AND gate 17 to the addition input B3 for each frame. Therefore,
In the adder circuit 13, the signal SD3 of the least significant bit of the image data is converted to the upper bits (SD4 to SD) of the image data.
6) are alternately added to the data for each frame. In this case, the three bits DG3 to DG6 of the addition output are used as display data.

The operation of the AND gates 14, 15, 16, 17 to which the control signal ST and the least significant bit of the image data in each mode are applied is selected by the selection signal SEL.
6, SEL5, SEL4, and SEL3, the least significant bit position of the image data inputs SD0 to SD6 can be selected. Therefore, even if the number of input bits of the image data is different even in the case of one adder circuit 13, Can be handled.

In FIG. 1, the control signal ST uses the same circuit as the timing control circuit shown in FIG. 2 to alternately perform addition processing and non-addition processing for each dot and each line. Further, in the same pixel, addition processing and non-addition processing are performed alternately for each frame.

[0022]

As described above, according to the present invention, it is possible to cope with various liquid crystal display devices incorporating digital drivers having different input bits with only one adder circuit without providing a plurality of adder circuits. It is possible to further reduce the number of gates, reduce the chip area, and realize low power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Addition circuit 2 AND gate 3 Timing control circuit 4, 5, 6, 7 Addition circuit 8 Switching circuit 9, 10, 11, 12 AND gate 13 Addition circuit 14, 15, 16, 17 AND gate

Claims (2)

(57) [Claims] In order to perform display with a larger number of gradations than the number of gradations displayed on a display pixel, each display pixel includes:
By alternately selecting, for each frame, whether the least significant bit of the (N + 1) -bit image data applied to each frame is to be added to or not added to the upper N bits of the image data, the N-bit display data is obtained. In the image information processing apparatus for outputting, an adder circuit for applying the (N + 1) -bit image data to one addition input;
A plurality of gate circuits to which a least significant bit of +1 bit is applied and an output of which is applied to the other addition input of the addition circuit, wherein the plurality of gate circuits control selection between the addition processing and the non-addition processing And a selection signal for selecting the gate circuit according to the value of N is applied to the gate circuit. 2. The image data of N + 1 bits, the number of bits of which changes according to the value of N, is applied in order from the most significant bit of one of the addition inputs of the addition circuit, and from the most significant bit of the addition output of the addition circuit. 2. The image information processing apparatus according to claim 1, wherein N bits are used as display data.