JPH06161391A - Liquid crystal driving circuit - Google Patents

Abstract

PURPOSE:To provide the liquid crystal driving circuit which has diverse easy-to- handle display functions. CONSTITUTION:This liquid crystal driving circuit forms (N+1) gradation voltages and can make an N-gradation display by using N from among the (N+1) gradation voltages and also make a 2N-gradation display including intermediate gradations by FRC which uses the (N+1) gradation voltages and outputs two adjacent gradation voltages alternately in the unit of frame. The gradation display corresponding to gradation voltages and the gradation display including an intermediate gradation display which suppresses a flicker and has good linearly since the FRC can use close gradation voltages are both made to correspond to binary display data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive circuit, and more particularly to a technique effective for use in a liquid crystal display panel having a TFT (thin film transistor) active matrix structure for multi-gradation display.

[0002]

2. Description of the Related Art As one of gradation display technologies using liquid crystal,
There is FRC (Frame Rate Control). This technique is to perform gradation display by controlling display data between frames and changing the effective value of the liquid crystal drive voltage. Regarding this FRC, for example, 199
Published in 1 year, "Flat Panel Display '91", pages 173 to 180, edited by Nikkei Electronics and Nikkei Microdevices.

[0003]

When gradation display by FRC is performed using a binary display driver, three gradation display is obtained. When gradation display by FRC is performed using a driver for 8-gradation display, 15 gradations are obtained. Although the number of gradations can be increased by using the FRC in this way, it becomes difficult to use such as 3 gradations and 15 gradations. That is, since the display data is binary data, the gradation number formed by decoding the display data is a factorial of 2 such as 4 or 16, but one gradation number is insufficient. Because.

An object of the present invention is to provide a liquid crystal drive circuit which realizes various and easy-to-use display functions. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, N + 1 gray scale voltages are formed and N gray scales of the N + 1 gray scale voltages are used to generate N
The gradation display is also performed, and the FRC that alternately outputs two adjacent gradation voltages in frame units by using the N + 1 gradation voltage enables 2N gradation display including the intermediate gradation.

[0006]

According to the above-mentioned means, the gradation display corresponding to the gradation voltage and the gradation voltages close to each other can be used in the FRC to suppress the flicker and include the intermediate gradation display with good linearity. Both multi-gradation display can be associated with binary display data.

[0007]

1 is a block diagram showing an embodiment of a liquid crystal drive circuit according to the present invention. In this example,
N + 1 gradation voltages are formed in the gradation voltage generating circuit. Here, N is a number such as 2, 4, 8, ... the like corresponding to the 2 ^n.

The input data is composed of binary digital signals. This input data is serially input in synchronization with the clock pulse and taken into the data latch circuit. The input data serially fetched by the data latch is fetched in parallel by the line data latch circuit when the display data for one line is fetched.

The data fetched by the line data latch circuit is decoded by the decoder circuit to obtain N or N.
One of the +1 gradation voltages is selected and output to the data line of the TFT display panel. As will be described later, in the TFT display panel, since the scanning line selecting operation is sequentially performed at a fixed timing, the grayscale voltages output in parallel are
Writing is performed on the pixel electrode coupled to the selected scan line.

The display driving circuit of this embodiment performs an operation of performing N gradation display by using N gradation voltage from N + 1 gradation voltage, and N gradation from N + 1 gradation voltage for each frame. An FRC display operation is performed in which adjacent grayscale voltages are alternately output to perform halftone display.

FIG. 2 is an operation explanatory view for explaining an example of the operation of the liquid crystal drive circuit according to the present invention. In this embodiment, an example is shown in which 2-gradation (white / black) display and 4-gradation display by FRC are performed with 3-gradation voltage. In the same figure (A), the normal display for displaying white / black using gradations 0 and 2 and 1.3 between 0 and 2 are used, and 0 and 1.3 are displayed alternately, which are equivalent. It produces 0.7 gradation. As a result, in the display operation by FRC,
It is possible to create four gradations such as 0-0.7-1.3-2.

In this case, when the binary display data is 00, the gradation voltage 0 is output, when it is 01, the gradation voltages 0 and 1.3 are alternately output by the FRC operation, and when it is 10, the gradation voltage is 0. Adjusting voltage 1.3 is output, and 11
In the case of, the gradation voltage 2 is output. The processing of such display data is most easily performed by the input data input to the data latch circuit, but may be performed by a decoder circuit that decodes the output of the line data latch. For example, by inputting information of odd frames and even frames into the decoder circuit, when the display data is 01, the gradation voltage 0 is selected in the even frames, and the gradation voltage 1.3 is selected in the odd frames. Good. When binary display is performed using the same decoder as described above, 00 is changed to black 11 in the input data.
The data may be processed so as to correspond to white.

FIG. 2B shows 0 gradation, 1 gradation and 2 gradations.
A case is shown in which equal gradation voltages are used like gradation. In normal gradation display, white / black binary display is performed using gradation 0 and gradation 2 as described above. On the other hand, in FRC display, gradation 0 and gradations 0 and 1 are alternately used to perform 0.5 gradation display, and gradation 1, gradation 1 and gradation 2 are displayed. It is possible to display four gradations by alternately displaying 1.5 gradations. Of course, gradation 2 can also be displayed, but since the display data must be 3 bits, in this case 1.5 gradation is not used and 5
Four gradations are selected and used.

FIG. 3 is an operation explanatory view for explaining another example of the operation of the liquid crystal drive circuit according to the present invention. FIG. 9A shows an example in which 9 gradation voltages are used to display 8 gradations by using 8 gradation voltages and 16 gradations are displayed by FRC using 9 gradation voltages.
(B) shows a display example using a conventional 8-gradation driver for the purpose of comparison with the present invention.

According to the present invention, when an intermediate gradation is formed by FRC, two adjacent gradation voltages are always selected. That is, the gradation 0 and the gradation 1 are alternately output by the FRC to make 0.5 gradation equivalently. Similarly, by combining each of the gradation 1 and the gradation 2 or the gradation 7 and the gradation 8, seven intermediate gradations such as 1.5 to 7.5 are obtained. As a result, it is possible to set 17 in every 0 to 0.5 gradation.
The same gradation display is possible. However, since gradation display is performed by 4-bit display data, either gradation 8 or 7.5 is not used, and gradation from 0 to 7.5 in steps of 0.5 or from 0 16 kinds of gradation display up to 7 gradations and 8 gradations are performed.

As described above, since two adjacent gray levels are combined and the intermediate gray level is obtained by FRC, the difference between the two gray levels can be minimized. As a result, flicker can be suppressed to the minimum, and an intermediate gradation display with good linearity can be obtained.

On the other hand, in the case of the 8-gradation driver as shown in (B), the FRC provides 7 in steps of 0 to 0.5.
Only 15 different gradations can be displayed. As a result, for example, when a display operation is performed with 4-bit display data, it is necessary to process the data so that 0000 and 00001 correspond to gradation 0 or 1111 and 1110 correspond to gradation 7. In addition, gradation display is compressed on the white side or the black side. In particular, when multicolor display is performed by the gradation display, color reproducibility becomes poor.

FIG. 4 shows a display pattern diagram for explaining an example of the display operation by the dither method. In the figure, the numbers attached to the pixels represent gradations. In this embodiment, an example in which 8 gradations are realized by using a 3 gradation driver of gradation 0, gradation 1 and gradation 2 is shown.

4 adjacent to the top, bottom, left and right on the TFT display screen
For each pixel, the first gradation display is set to 0 for all four pixels. In the second gradation display, for example, one of the upper left pixels of the four pixels is set to 1, and the remaining three are set to 0. 3rd gradation display is 4
Of the pixels, for example, the upper right and lower left two are set to 1, and the remaining two are set to 0. For the fourth gradation, for example, the upper left one is set to 0, and the remaining three are set to 1. For the fifth gradation, all pixels are set to 1. Sixth
As for the gradation, for example, the upper left one is set to 2, and the remaining three are set to 1. For the seventh gradation, for example, the upper right and lower left two are set to 2, and the remaining two are set to 1. For the eighth gradation, for example, the upper left one is 1.
Then, set the remaining 3 to 2. When the input data is 4 bits, it is meaningless, but if all the pixels are set to 2, the 9th gradation can be obtained.

FIG. 5 is a block diagram showing an embodiment of a liquid crystal display device using the liquid crystal drive circuit according to the present invention. The liquid crystal display panel is large in size and is capable of color multicolor display by using RGB three primary color pixels. The signal lines of the color liquid crystal panel are divided into upper and lower odd-numbered ones and even-numbered ones, and the signal line drive circuits DDV1 to DD are arranged on the upper side.
V10 is provided, and the signal line drive circuit DDV11 is provided on the lower side.
~ DDV20 is provided.

First-stage signal line drive circuits DDV1 and DDV1
In 1, the low power consumption mode is started immediately when the data acquisition is completed by the clock pulse CL2 for serial input. Then, the output signal is set to the low level, the signal line drive circuits DDV2 and DDV12 in the next stage start their respective operations, and the data is taken in by the subsequent clock pulse. Thereafter, in the same manner, the signal line drive circuit DD at the final stage
When the capture of the input data is completed by V10 and DDV20, the clock pulse CL1 is generated to transfer the latch data fetched to the line data latch circuit,
Starts capturing serial data corresponding to the next line.

The scan line electrodes are provided by the scan line drive circuits CDV1 to
It is driven by CDV4. This scanning line drive circuit CDV
Each of 1 to CDV4 has a plurality of output terminals and receives a line synchronization signal to sequentially switch the scanning lines to be selected.

An image memory for storing at least one screen of display data is provided between the controller or the controller and the computer CPU, and the host computer (microcomputer) CPU inputs the display data to the image memory. The controller sequentially reads the data in the image memory in synchronization with the scanning timing of the liquid crystal display panel to generate serial data and control signals. At this time, in the case of the FRC, which corresponds to the intermediate gradation for each frame in the FRC, the display data is processed so that the adjacent gradations are alternately selected. As a result, 2N gradation display is possible with N + 1 gradation voltage.

The operational effects obtained from the above embodiment are as follows. That is, (1) N + 1 gradation voltage is formed, and the above N + 1
N gray scale display can be performed using N gray scales of the gray scale voltages, or the intermediate gray scale can be displayed by FRC that alternately outputs two adjacent gray scale voltages in frame units using the N + 1 gray scale voltage. Including 2N gradation display is performed. With this configuration, since a close gradation voltage can be used in FRC, flicker can be suppressed, and gradation display including intermediate gradation display with good linearity can be performed corresponding to binary display data. The effect is obtained.

(2) An N + 1 gradation voltage is formed, and N gradation display using N gradations of the N + 1 gradation voltage and four vertically and horizontally adjacent N + 1 gradation voltages are provided. 4 by dithering method combining pixel gradation display
N gradation display is performed. With this configuration, it is possible to use a similar gray scale voltage in dither, so it is smooth.
Moreover, it is possible to obtain the effect that gradation display including intermediate gradation display with good linearity can be performed in correspondence with binary display data.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG.
When using the 4 + 1 5-gradation driver,
Basic 4 gradation display by 4 gradation voltage, and F
8 gradation display may be performed by RC. If the dither method is used, the number of gradations can be further increased to 16 gradations. Furthermore, it is possible to express more gradations by using the dither method and FRC at the same time. The present invention can be widely used as a drive circuit for a TFT liquid crystal display panel.

[0027]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, N + 1 gray scale voltages are formed and N gray scales of the N + 1 gray scale voltages are used to generate N
Gradation display is also performed. In the FRC in which two adjacent gradation voltages are alternately output in frame units using the N + 1 gradation voltage, flicker is suppressed, and gradation including intermediate gradation display with good linearity is also provided. Both displays can be made to correspond to binary display data.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a liquid crystal drive circuit according to the present invention.

FIG. 2 is an operation explanatory diagram for explaining an example of the operation of the liquid crystal drive circuit according to the present invention.

FIG. 3 is an operation explanatory diagram for explaining another example of the operation of the liquid crystal drive circuit according to the present invention.

FIG. 4 is a display pattern diagram for explaining an example of a display operation by a dither method of the liquid crystal drive circuit according to the present invention.

FIG. 5 is a block diagram showing an embodiment of a liquid crystal display device using the liquid crystal drive circuit according to the present invention.

[Explanation of symbols]

CPU ... Host computer, DDV1-DDV20 ...
Signal line drive circuit, CVD1 to CVD4 ... Scan line drive circuit.

Claims (2)

[Claims] 1. A gradation voltage generating circuit for generating an N + 1 gradation voltage is provided, and an N gradation display using N gradations of the N + 1 gradation voltages and an N gradation display using the N + 1 gradation voltages are adjacent to each other. A liquid crystal drive circuit characterized in that two gradation voltages are alternately output in frame units to enable 2N gradation display including the intermediate gradation. 2. A gradation voltage generating circuit for generating an N + 1 gradation voltage is provided, and an N gradation display using N gradations of the N + 1 gradation voltages is adjacent to the upper, lower, left and right sides by the N + 1 gradation voltage. A liquid crystal drive circuit, which enables 4N gray scale display including an intermediate gray scale of the gray scale voltage by a combination of gray scale display of four pixels.