JPH09244602A - Picture processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the capacity of a processor by parallel performing the error diffusing processing of picture data to be supplied by being synchronized with a dot clock in pixels of an odd numbered column and an even numbered column. SOLUTION: Output of a latch circuit 5 are impressed on an adder circuit 7 to be added with the erroneous data of the pixel immediately proceeding held in a latch circuit 9. Then, the error diffusing to the picture data of the pixel of an impressed odd numbered column is performed and corrected data are formed. Then, upper 4 bits and lower 4 bits are respectively impressed on OR gates 10, 11. Picture data SDE of the pixel of an even numbered column held in a latch circuit 6 are added with the erroneous data EO of the pixel of the odd numbered column immadiately proceeding in an adder circuit 8 and the upper 4 bits and the lower 4 bits of the added result are impressed on OR gates 13, 14. The upper 4 bits of the corrected picture data subjected to the error diffusing processing by the adder circuit 8 are held in a latch circuit 15 as picture display data HE and the lower 4 bits are held in the latch circuit 9 as the erroneous data EE of the pixel of the even numbered column.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to image processing of multi-gradation processing for pseudo display of a gradation number of a predetermined bit or more on a digital input display device for displaying by image display data of a predetermined bit. Regarding the device. In particular, the present invention relates to an image processing device capable of high-speed processing corresponding to a display device having a large number of pixels.

[0002]

2. Description of the Related Art In recent years, a high-definition color liquid crystal display device for OA for multimedia has been developed. This color liquid crystal incorporates a 3-bit or 4-bit digital driver for each of R, G, and B colors. For example, a color LCD with a 3-bit digital driver has 8
It is possible to display gradations and display 512 colors in total.
However, this is sufficient when used simply as a monitor for OA, but is insufficient for displaying video such as moving images and still images for multimedia, and further increase in gradation is desired. Was rare.

Therefore, a method of artificially increasing the number of gradations by diffusing a component that cannot be displayed by one pixel to adjacent pixels around the same screen frame (intra-frame error diffusion), and displaying by one pixel A method of diffusing an incapable component into the same pixel over a plurality of screen frames (interframe error diffusion) has been proposed. In the present specification, the term error data means data of lower bits of the constituent bits of image data that cannot be displayed by the digital driver of the display device.

FIG. 4 shows a multi-gradation processing circuit using intra-frame error diffusion, showing one color for R, G, and B. In FIG. 4, the latch circuit 1 has a dot clock D
The 8-bit original image data SD sequentially applied in synchronization with CLK is latched and output to the adder circuit 2. Addition circuit 2
Generates the 8-bit corrected image data HD by adding the original image data SD and the 4-bit error data EI output from the error data holding circuit 3. Error data holding circuit 3
Is the dot clock D with the lower 4 bits of the corrected image data HD as error data EI for intra-frame error diffusion.
The original image data SD of the next pixel is held by CLK, and when the latch circuit 1 latches the original image data SD, the error data EI is output to the adder circuit 2. The upper 4 bits of the corrected image data HD are held in the output latch circuit 4 as a result of intra-frame error diffusion, and are output to the display device as image display data DG. That is, the intra-frame error diffusion circuit is composed of the addition circuit 2 and the error data holding circuit 3, and since the error data EI of the pixel one dot before is added to the original image data SD applied to the addition circuit 2, The lower 4-bit error data is sequentially diffused to adjacent pixels.

Therefore, by supplying the error diffusion processed 4-bit image display data DG of each color of R, G and B to a liquid crystal display device having a built-in 4-bit digital driver, the 256 × 256 × 256 floors are simulated. The key can be displayed. The multi-gradation image processing apparatus for intra-frame error diffusion has been briefly described above with reference to FIG. 4, but the details are described in Japanese Patent Application No. 4-307210 by the applicant of the present application.

[0006]

When the multi-gradation image processing device shown in FIG. 4 is used in a general VGA liquid crystal display device having a number of pixels of 640 × 480, image data SD is used. The frequency of the dot clock DCLK synchronized with is approximately 25 MHz. However, as liquid crystal display devices such as personal computers have become more and more high-definition, a device with a pixel size of 1024 × 768 called XGA or 1280 × 102.
4 have come to be used. When the multi-gradation image processing device of FIG. 4 is used for such a high definition liquid crystal display device, the dot clock is 70 MHz to 90 M
At a very high frequency of Hz, the circuit of FIG. 4 may not operate as an integrated circuit.

[0007]

The present invention has been made in view of the above-mentioned points. The invention described in claim 1 is a plurality of P-bit image data of consecutive pixels in the horizontal direction. A plurality of adder circuits which are provided corresponding to the plurality of image data and to which the plurality of image data are applied at the same time; and a means for applying a predetermined lower bit of each of the adder circuits to an adjacent next adder circuit as error data. Error data holding circuit for holding a predetermined lower bit of the addition circuit corresponding to the last pixel of the pixel data, and applying the same to the addition circuit corresponding to the first pixel of the applied image data. Thus, image data of a plurality of pixels are processed at the same time.

According to a second aspect of the present invention, the first and second adder circuits to which the image data of consecutive pixels before and after in the horizontal direction are simultaneously applied, and the output of the first adder circuit are provided. Means for applying the predetermined lower-order bit of the above as error data to the second adder circuit, and the predetermined lower-order bit of the output of the second adder circuit as error data,
By including an error data holding circuit to be applied to the adder circuit, the image data of two consecutive pixels in the horizontal direction is processed at the same time.

Further, in the invention described in claim 3, the image data of consecutive pixels before and after in the horizontal direction are simultaneously supplied, and the error data of the immediately preceding pixel is added to a predetermined lower bit of the image data in the preceding column. An error data creation circuit that creates error data of the front row, adds the error data of the front row and predetermined lower bits of the image data of the back row, and creates error data to be added to the image data of the next pixel; An error data creating circuit and an adding circuit for adding image data of the rear row to output image display data of the rear row. is there.

According to a fourth aspect of the present invention, the image data of consecutive pixels before and after in the horizontal direction are simultaneously supplied, and the predetermined lower bit and the error data of the image data of the preceding column are added. An adder circuit, a second adder circuit for adding the carry signal of the first adder circuit and a predetermined upper bit of the image data of the front row, and outputting image display data of the front row, and a predetermined of the image data of the back row. A third adder circuit for adding the lower bit and the error data output of the first adder circuit, and holding the output of the third adder circuit for a predetermined period and outputting the error data to be applied to the first adder circuit. A second holding circuit that holds the error data output of the first adding circuit for a predetermined period, and the error data held by the second holding circuit and the image data of the rear row are added. And above the prescribed A fourth adder circuit that outputs bits as image display data in the rear row is provided, and error data for two pixels is calculated at the previous timing, and at subsequent timings, the image data of the pixels in the rear row and the error data from the pixels in the front row Is added to increase the processing speed.

According to a fifth aspect of the invention, there is provided the first aspect of the invention.
Of the carry signal of the adder circuit and the predetermined upper bit of the image data of the pixels in the preceding column, a carry signal having the same content as the carry signal output from the second adder circuit is added to the second adder. By providing the carry signal generation circuit that outputs the carry signal faster than the circuit generates the carry signal, the generation of the carry signal due to the addition of the error data is accelerated and the processing speed is increased.

Further, the invention according to claim 6 is the third aspect.
A second carry signal generating circuit for generating a carry signal when the error data of the preceding column is added to the image data of the latter column by a logical product of the carry signal of the adding circuit of FIG. By providing the error signal, the generation of the carry signal by the addition of the error data from the pixels in the front row and the image data of the pixels in the back row is accelerated, and the processing speed is increased.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention described in claims 1 and 2. The latch circuits 5 and 6 are both 8-bit latch circuits and hold image data of two adjacent pixels according to the clock CLK. Image data SDO of pixels in odd columns in the horizontal scanning line direction is applied to the latch circuit 5, and image data SDE of even columns is applied to the latch circuit 6. Normally, the image data and the dot clock are synchronously provided serially, but this is serial-parallel converted so that the image data of the odd and even columns are simultaneously applied to the latch circuits 5 and 6. ing. This serial-parallel conversion uses a two-stage 8-bit parallel shift register that is shift-controlled by a dot clock, and when two dot clocks are applied, the outputs of the first and second stages of the shift register are output. This can be realized by making the latch circuits 5 and 6 latch. Therefore, the clock CLK that controls the operation of the circuit shown in FIG. 1 is a clock having a frequency half that of the dot clock.

The output of the latch circuit 5 is applied to the adder circuit 7 corresponding to the first adder circuit described in claim 2,
The error data EE of the immediately preceding pixel held in the latch circuit 9 is added. As a result, error diffusion is performed on the image data of the odd-numbered pixels applied, and corrected image data is created. Of this corrected image data, the upper 4 bits are applied to the OR gate 10, and the lower 4 bits are applied to the OR gate 11. The OR gates 10 and 11 are circuits for fixing the output to the maximum value, that is, "11111111" when a carry occurs as a result of the addition, and the carry signal C of the adder circuit 7 is applied to each. The output of the OR gate 10 of the upper 4 bits is held in the latch circuit 12 as the image display data HO of the odd-numbered column pixels.

On the other hand, the second adder circuit according to claim 2, wherein the output of the OR gate 11 of the lower 4 bits is added as the error data EO of the pixels in the odd columns to the image data SDE of the pixels in the even columns. Is applied to the adding circuit 8 corresponding to. The image data SDE of the even-numbered column pixel held in the latch circuit 6 is added to the error data EO of the immediately preceding pixel, that is, the odd-numbered column pixel in the second addition circuit 8, and the upper 4 bits of the addition result are ORed. It is applied to the gate 13 and the lower 4 bits are applied to the OR gate 14. Similarly to the above, the OR gates 13 and 14 also fix the output to the maximum value when a carry occurs, and the carry signal C of the adder circuit 8 is applied to each. The upper 4 bits of the corrected image data subjected to the error diffusion processing by the adding circuit 8 are held in the latch circuit 15 as the image display data HE, and the lower 4 bits are held in the latch circuit 9 as the error data EE of the even column pixels. . The error data EE becomes the error data EE to be added to the image data of the odd-numbered column pixel held in the latch circuit 5 at the next timing, that is, the pixel next to the even-numbered column pixel processed at this timing.

The image display data DGO and DGE held in the latch circuits 12 and 15 are parallel-serial converted and supplied to the liquid crystal display device in synchronization with the dot clock. According to the embodiment shown in FIG. 1, the image data supplied in synchronization with the dot clock can be subjected to error diffusion processing in parallel with pixels in odd columns and pixels in even columns. Becomes half the frequency of the dot clock, and the processing capacity can be improved. As a result, it is possible to realize an image processing device that can be applied to a display device having a very large number of pixels.

FIG. 2 is a block diagram showing another embodiment of the present invention, in which the processing speed of the image processing apparatus shown in FIG. 1 is improved. In the circuit of FIG. 1, the adder circuit 7 and the adder circuit 8 are operatively connected in series. That is, as a result of the addition of the lower 4 bits of the adder circuit 7, the carry propagates to the upper bits, the carry signal C is confirmed, and the addition output is confirmed. Then, the addition process of the adder circuit 8 is performed, and the adder circuit 8 is added. Since the final output is obtained in the state where the carry signal C and the addition output are confirmed, the processing becomes equivalent to that of the 16-bit addition circuit, and the processing time is the time until the output of the addition circuit 7 is confirmed and the output of the addition circuit 8 is confirmed. It will be the sum of time.
Therefore, in the circuit of FIG. 1, the clock CLK has a frequency half that of the dot clock, but the frequency cannot be so high. Therefore, in the embodiment shown in FIG. 2, the circuit for calculating the error data is separated from the circuit for calculating the image display data.

In FIG. 2, image data S of odd-numbered column pixels
DO is held by the latch circuit 16, and image data SDE of even-numbered column pixels is held by the latch circuit 17. The lower 4-bit SDOL of the image data SDO held in the latch circuit 16 is applied to the adder circuit 18 corresponding to the first adder circuit described in claim 4, and the higher 4-bit SDOU is applied.
Is applied to the adder circuit 19 corresponding to the second adder circuit described in claim 4, and is also applied to the AND gate 20. Further, the lower 4 bits SDEL of the image data SDE of the even column pixels held in the latch circuit 17 is the adder circuit 2 corresponding to the third adder circuit described in claim 4.
1 and the upper 4 bits SDEU are AND gate 2
2 is applied. In addition, the image data SDE of the even-row pixels
Is further held in the latch circuit 23, delayed by one clock of the clock CLK, and applied to the adder circuit 24. The adder circuit 24 corresponds to the fourth adder circuit described in claim 4.

The adder circuit 18 is a 4-bit adder circuit for calculating the error data EO of odd-numbered column pixels, and the addition output is applied to the OR gate 25. The carry signal C of the adder circuit 18 is applied to the carry input of the adder circuit 19 and also to the AND gate 20. That is, the carry signal C of the adder circuit 18 is the adder circuit 19
Since it takes a long time to wait for the carry signal C of the adder circuit 19 to be generated, the AND gate 20
In the AND circuit 2, the carry signal C of the adder circuit 18 is ANDed with the carry signal C of the upper 4 bits to obtain the carry signal prior to the carry signal C of the adder circuit 19.
The output of 0 fixes the maximum value in the OR gate 25. Therefore, the error data EO of the odd-row pixels output from the OR gate 25 can be obtained in the processing time of the 4-bit addition processing. The error data EO output from the OR gate 25 is applied to the adder circuit 21 so as to be added to the lower 4 bits SDEL of the image data SDE of the even-numbered column pixels, and the image of the even-numbered column pixels is imaged at the timing of the next clock CLK. In order to add to the data SDE, it is held in the latch circuit 27 corresponding to the second holding circuit described in claim 4.

On the other hand, the adder circuit 19 calculates the corrected image data by adding the carry signal C of the adder circuit 18 and the image data SDOU of the upper 4 bits.
The addition output and the carry signal C are applied to the OR gate 26 to fix the maximum value when the carry occurs. Therefore,
The image data HO output from the OR gate 26 is obtained by the sum of the addition processing time of the addition circuit 18 and the addition processing time of the addition circuit 19, that is, the addition processing time of 8 bits. The corrected image data HO is sent to the latch circuit 2
8 and 29 are sequentially held and output as image display data DGO.

Further, the adder circuit 21 adds the error data EO from the odd-numbered column pixel to the lower 4-bit image data SDEL of the even-numbered column pixel, and adds the error data EO from the odd-numbered column pixel at the next timing. The data EE is calculated. Similarly to the carry signal C of the adder circuit 21, the carry signal C is set to AN in order to eliminate the delay due to the propagation of the carry signal.
Image data S of upper 4 bits applied to the D gate 22
A carry signal is generated without performing addition processing by the logical product with DEU. Addition output of addition circuit 21 and A
The output of the ND gate 22 is applied to the OR gate 30,
The maximum value is fixed when a carry signal is generated. Therefore,
The image difference data EE output from the OR gate 30 is obtained by the sum of the addition processing time of the addition circuit 18 and the addition processing time of the addition circuit 21, that is, the addition processing time of 8 bits. The error data EE is held in the latch circuit 31 corresponding to the first holding circuit described in claim 4, and is added to the image data of the next odd-numbered column pixel applied at the timing of the next clock CLK. .

The above-mentioned adder circuit 18, AND gate 20,
The OR gate 25, the adder circuit 21, the AND gate 22, and the OR gate 30 are circuits that create error data EO of odd-numbered column pixels and error data EE of even-numbered column pixels, and the error data generation according to claim 3. It corresponds to a circuit. The adder circuit 24 adds the error data EO delayed by one clock by the latch circuit 27 and the latch circuit 23 and the image data SDE of even-numbered column pixels to create corrected image data of even-numbered column pixels. Of the addition output, the higher 4 bits are applied to the OR gate 32 together with the carry signal C as the corrected image data. Here, the lower 4 bits are added by the adder circuit 21 at the timing before the clock CLK.
It has already been calculated by and will be truncated.
Corrected image data HEU output from the OR gate 32
Is held in the latch circuit 33, and the image display data DGE
Is output as

The image display data DGO of the odd-row pixels and the image display data DGE of the even-row pixels held in the latch circuits 29 and 33 are parallel-serial converted and serially converted into a liquid crystal display device in synchronization with the dot clock. Supplied. Next, the operation timing of the embodiment of FIG. 2 will be described based on FIG. The timing diagram of FIG. 3 shows the clock CL
It is described that the latch circuit operates at the falling edge of K.

First, in the nth cycle of the clock CLK, the image data SD of the nth odd column pixel is stored in the latch circuits 16 and 17 due to the fall of the clock CLK.
On and the image data SDEn of the even column pixels are held. At this time, the error data E of the (n-1) th even column pixel calculated in the previous clock cycle is stored in the latch circuit 31.
En-1 is held. Therefore, n of the clock CLK
In the second period, the adder circuit 18 determines that the image data SDOL
The error data EOn is calculated by adding n and the error data EEn-1, and the addition circuit 19 calculates the corrected image data HOUn. Further, in the adder circuit 21, the error data EOn calculated by the adder circuit 18 and the image data SDELn
The error data EEn is calculated by adding. That is,
At the n-th timing of the clock CLK, the error data of each of the image data of the n-th odd column pixel and the image data of the n-th even column pixel is created.

Next, when the clock CLK becomes the (n + 1) th cycle, the calculated error data EOn is transferred to the latch circuit 2.
7 and the error data EEn is held in the latch circuit 31. In addition, the correction image data HOU
Are held in the latch circuit 28, and the image data SDEn of the even-numbered column pixels are held in the latch circuit 23. On the other hand, the latch circuits 16 and 17 hold the image data SDOn + 1 of the next odd-numbered column pixel and the image data SDEn + 1 of the even-numbered column pixel, and the error data is calculated similarly to the nth cycle of the clock CLK. Be seen. In addition, in the adder circuit 24, the error data EOn held in the latch circuit 27 and the image data SDEn held in the latch circuit 23 are added, and as a result, the corrected image data HEUn of the even-row pixels is calculated. .

At the cycle of the (n + 2) th clock CLK, the corrected image data HOUn of the pixels in the odd-numbered columns held in the latch circuit 28 is held in the latch circuit 29.
The image display data DGOn is output, and the corrected image data HEUN of the even-row pixels calculated by the adder circuit 24 is held in the latch circuit 33 and output as the image display data DGEn.

As described above, according to the image processing circuit of FIG.
The image data SDO of the odd-numbered column pixels and the image data SDE of the even-numbered column pixels are simultaneously input, and the processing is divided into two clock timings. In particular, the error data EO and EE of the odd-numbered column pixels and the even-numbered column pixels are calculated. And the image display data DGO of the odd column pixels are calculated at the previous timing, and the image display data DGE of the even column pixels are calculated at the next timing. With such a configuration, the addition processing time performed in one clock cycle period is the maximum of the 8-bit addition processing, so that the processing speed is higher than that of the circuit that requires substantially 16-bit addition processing time as shown in FIG. Will be able to

[0028]

As described above, according to the present invention, since the error diffusion processing capability is increased, the image data applied in synchronization with the high speed dot clock can be processed according to the speed. become. As a result, it becomes possible to deal with a display device having a large number of pixels, particularly a high-definition display device called XGA. Then, the number of gray scales of a personal computer or the like adopting the XGA display device can be pseudo-multi-scaled,
It has the effect of significantly improving its commercial value.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a timing diagram illustrating the operation of the block diagram shown in FIG.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 5, 6, 9, 12, 15 Latch circuit 7, 8 Adder circuit 10, 11, 13, 14 OR gate 16, 17 Latch circuit 18, 19, 21, 24 Adder circuit 20, 22 AND gate 25, 26, 30, 32 OR gate 23, 27, 28, 29, 31, 33 Latch circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G09G 5/36 520 G09G 5/36 520A H04N 9/64 H04N 9/64 Z

Claims (6)

[Claims] 1. A floor which is applied to a display device in which image display data of each pixel is composed of L bits, and which is displayed by the image display data of L bits, and which is displayed by image data of P bits larger than L bits. In an image processing device for displaying tones on the display device in a pseudo manner, a plurality of image data are provided corresponding to a plurality of P-bit image data of consecutive pixels in the horizontal direction, and the plurality of image data are simultaneously applied. Adder circuit, means for applying predetermined lower order bits of each adder circuit to the next adjacent adder circuit as error data, and predetermined lower order bit of the adder circuit corresponding to the last pixel of the applied pixel data. An image processing apparatus comprising: an error data holding circuit that holds a bit and applies the bit to an adder circuit corresponding to a first pixel in the applied image data. 2. A floor which is applied to a display device in which image display data of each pixel is composed of L bits, and which is displayed by the image display data of L bits, and which is displayed by image data of P bits larger than L bits. In an image processing device for pseudo-displaying a key on the display device, first and second adder circuits to which image data of consecutive pixels in the horizontal direction before and after are applied simultaneously, and the first addition circuit. Means for applying a predetermined low-order bit of the output of the circuit as error data to the second adder circuit, and holding a predetermined low-order bit of the output of the second adder circuit as the error data,
And an error data holding circuit applied to the adding circuit of the image processing apparatus. 3. A floor which is applied to a display device in which image display data of each pixel is composed of L bits, and which is displayed by the image display data of L bits, and which is displayed by image data of P bits larger than L bits. In the image processing device for displaying the tones on the display device in a pseudo manner, image data of consecutive pixels in the horizontal direction are supplied at the same time, and error data of the immediately preceding pixel is supplied to a predetermined lower bit of the image data in the preceding column. And an error data creation circuit that creates error data in the front row, adds the error data in the front row and predetermined lower bits of the image data in the back row, and creates error data to be added to the image data of the next pixel. , An addition circuit for adding the error data of the front row to the image data of the back row and outputting image display data of the back row, the error data creation circuit and the addition An image processing device in which the circuit performs addition operations at different timings. 4. A floor which is applied to a display device in which image display data of each pixel is composed of L bits, and which is displayed by the image display data of L bits, and which is displayed by image data of P bits larger than L bits. In an image processing device for displaying a key on the display device in a pseudo manner, image data of consecutive pixels before and after in the horizontal direction are simultaneously supplied, and a predetermined lower bit and error data of the image data in the preceding column are added. A first adder circuit, a second adder circuit for adding a carry signal of the first adder circuit and a predetermined high-order bit of the image data of the front row, and outputting image display data of the front row, and an image of the rear row A third adder circuit for adding the predetermined lower bit of the data and the error data output of the first adder circuit, and the output of the third adder circuit is held for a predetermined period of time, and is output to the first adder circuit. A first holding circuit that outputs error data to be added; a second holding circuit that holds the error data output of the first adding circuit for a predetermined period; and error data held by the second holding circuit An image processing apparatus comprising a fourth addition circuit for adding image data of a rear row and outputting a predetermined upper bit as image display data of the rear row. 5. A carry having the same content as that of the carry signal output from the second adder circuit by logical product of a carry signal of the first adder circuit and a predetermined high-order bit of image data of pixels in the preceding column. The image processing apparatus according to claim 4, further comprising a carry signal generation circuit that outputs a carry signal earlier than the generation of the carry signal of the second adder circuit. 6. A carry signal is generated when the error signal of the preceding column is added to the image data of the succeeding column by a logical product of the carry signal of the third adder circuit and a predetermined high-order bit of the succeeding column. The image processing apparatus according to claim 5, further comprising two carry signal generation circuits.