JP2003131627A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image display device in which EMI is further reduced by providing a unique arrangement relationship to a plurality of transmission lines located on a substrate used to transmit digital image data in a vertical difference system. SOLUTION: The device receives difference digital data outputted from a difference modulating circuit, adds data being held to the received data so as to generate digital image data, converts the data into analog image data and displays the image. The difference digital data have sign data having at least one bit to represent the sign of the differences and difference absolute value data having a plurality of bits to represent the absolute values of the differences. These data are a plurality of transmission lines corresponding to respective bits constituting of the difference digital data and are transmitted through a plurality of transmission lines which are arranged in parallel with the order that is different from the bit order of the difference absolute value data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, and more particularly, to an EM generated by the transmission of digital data.
The present invention relates to an image display device that can reduce I (electro-magnetic interference).

[0002]

2. Description of the Related Art Liquid crystal displays
play: LCD), LED display, plasma display panel (PDP), field emission display (FED), EL
An image display device such as an (electroluminescent) display includes pixels arranged in a matrix, a signal line drive circuit for supplying image signals to these pixels, and a circuit for transmitting image data to the signal line drive circuit. It has a base. The digitized image data is transmitted on this circuit board and input to the signal line drive circuit.

Generally, digital image data input to a signal line drive circuit is data supplied to each pixel corresponding to color elements such as red (R), green (G) and blue (B),
These data are transmitted in parallel. That is, if the gradation of each color element is 8 bits, 8 bits × 3 = 24
Bit digital image data is transmitted.

In recent years, image display devices have become larger in screen size and higher in definition, and along with this, the frequency of image data transmitted through a transmission line on the circuit board of the image display device as described above is also extremely high. It has become to. When digital data with a high frequency is transmitted, electromagnetic noise called "EMI" may occur, and it is necessary to reduce EMI.

As a method of reducing EMI, for example,
LVDS (Low Voltage Differential Signaling) and T
MDS (Transition Minimized Differential Signalin)
Methods such as g) have been proposed.

FIG. 17 is a conceptual diagram illustrating the overall configuration of an image display system that employs LDVS.

For example, in the case of a notebook computer, as shown in FIG. 17, an LVDS (or TMDS) is provided in an image data output section 110 called a "graphic controller".
Of the liquid crystal display device 100B.
On the side of, the gate array 1 on the circuit board of the signal line
A LVDS (or TMDS) demodulation circuit 130 is provided in front of 40. The modulation circuit 120 modulates the digital signal into a differential signal. Therefore, the modulation circuit 120
In the section from to the demodulation circuit 130, EMI due to transmission of image data can be reduced.

[0008]

However, in the case of the configuration illustrated in FIG. 17, the demodulation circuit 130 to the gate array 14 are used.
In the section up to 0 and the section from the gate array 140 to the signal line drive circuit 150, parallel digital image data is transmitted, so that EMI may occur.
The section from the demodulation circuit 130 to the gate array 140 is
Since the transmission distance is extremely short, it is easy to set EMI to a level that can be ignored, but in the section from the gate array 140 to the signal line drive circuit 150, the transmission distance is long and E
It is difficult to eliminate the occurrence of MI.

On the other hand, a method of adding the LVDS or TMDS demodulation circuit 130 to the inside of the signal line drive circuit 150 may be considered, but these demodulation circuits have a relatively large circuit scale and the circuit configuration of the signal line drive circuit. Has to be changed significantly, which is also difficult to achieve.

On the other hand, there is a "vertical differential transmission method" (disclosed in Japanese Patent Laid-Open No. 2000-20031) as one of transmission methods for reducing EMI with a relatively low-scale circuit configuration.
This method is a method that generally utilizes the property that the vertical correlation of images is high, and the image data of the nth line is the difference data between the image data of the nth line and the image data of the (n-1) th line. Is transmitted. Since the image data of the nth line and the image data of the (n-1) th line have a high correlation, that is, the difference is small, the transition of the data is significantly reduced, which reduces the EMI. In this vertical difference method, the demodulation circuit can be composed of only a line memory and an adder. Therefore, it is possible to reduce the EMI in the section from the gate array 140 to the signal line drive circuit 150 only by changing the configuration of the signal line drive circuit 150 to a very small scale.

As described above, if the vertical differential transmission system is adopted, it is possible to reduce the EMI in the transmission line input to the signal line drive circuit by adding a relatively small scale circuit.

However, when the transmission frequency is increased in order to cope with the future increase in screen size and high definition, further reduction of EMI is required.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a plurality of transmission paths on a base for transmitting digital image data in the vertical difference method with a unique arrangement relationship. Another object is to provide an image display device that reduces EMI. It is another object of the present invention to provide an image display device that further reduces EMI by adding a circuit on a relatively small scale based on the arrangement of transmission lines on the above-mentioned board.

In order to achieve the above object, an image display device of the present invention comprises a differential modulation circuit for inputting digital image data and outputting a difference with respect to the held data as differential digital data. Differential transmission for transmitting the differential digital data output from the differential modulation circuit, and differential demodulation for inputting the differential digital data via the transmission path and adding the held data to output digital image data A circuit, a conversion circuit that converts the digital image data output from the differential demodulation circuit into analog image data, and an image display unit that inputs the analog image data output from the conversion circuit and displays an image. The difference digital data includes at least 1-bit code data representing a sign of the difference and a duplicate data representing an absolute value of the difference. It includes a difference absolute value data bits, wherein the transmission channel is a plurality of transmission lines corresponding to the respective bits constituting the differential digital data,
It is characterized by having a plurality of transmission lines arranged in parallel in an order different from the bit order of the difference absolute value data.

According to the above configuration, it is possible to suppress the occurrence of EMI due to the transmission lines having high frequency components being adjacent to each other.

Here, between the transmission line for transmitting the code data and the transmission line for transmitting the least significant bit data of the difference absolute value data, the higher side of the difference absolute value data is provided. If a transmission line for transmitting data of any one of the above is provided, a transmission line having a low frequency component can be provided between transmission lines having a high frequency component, and electromagnetic wave interference can be suppressed. EMI can be reduced.

Here, in the present specification, the "upper side" means the upper half of the total number of bits of data. For example, when the data is 8 bits, "upper side" means the most significant bit to the 4th bit.

Similarly, in the present specification, the "lower side" means the lower half of the total number of bits of data. For example, when the data is 8 bits, "lower side" means from the 5th bit to the least significant bit.

On the other hand, a transmission line for transmitting the data of the higher-order bit of the difference absolute value data and a transmission line for transmitting the data of the lower-order bit of the difference absolute value data alternate. If the transmission line having the low frequency component is provided between the transmission lines having the high frequency components, the interference of electromagnetic waves can be suppressed and the EMI can be reduced.

Further, the differential modulation circuit includes a signal determination section for determining whether or not the data of any one of the upper bits of the differential absolute value data has a constant value for a predetermined period, and the data thereof. If the signal determination unit determines that is a constant value over a predetermined period, the data transmitted on the transmission line adjacent to the transmission line transmitting the data is inverted, and the inverted data is transmitted to the transmission line of the data. And a data inverting section, and the differential demodulation circuit has a changeover switch section for replacing the inverted data with the constant value data when the inverted data is transmitted to a transmission line, By flowing the inversion signal, it is possible to cancel the interference of electromagnetic waves and eliminate the occurrence of EMI.

If the result of the determination by the signal determination unit is transmitted to the changeover switch unit via the transmission line during the blanking period of the differential absolute value data, the determination signal is It is not necessary to provide a dedicated transmission line for transmission, and a compact structure is possible.

Further, the predetermined period may be one horizontal scanning period or a period obtained by dividing one horizontal scanning period, and the inverted signal can be transmitted over the horizontal blanking period or the period further divided. It is possible to judge whether or not there is.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. (First Embodiment) First, as a first embodiment of the present invention, an image display device in which a plurality of transmission lines for supplying vertical difference data to a signal line drive circuit have a unique arrangement relationship will be described.

In the following description, a specific example in which the present invention is applied to a liquid crystal display device will be given as an example of the image display device of the present invention, but the present invention is not limited to this specific example. It also includes those applied to other various types of image display devices.

FIG. 1 is a conceptual diagram showing a part of a liquid crystal display device according to the first embodiment of the present invention.

In the display device shown in the same figure, the input video signal VS is input to the gate array 10 on the signal line side circuit board of the liquid crystal module, and by the vertical difference processing modulation circuit provided inside the gate array 10. , Modulated to digital vertical difference data. In addition, in FIG. 1, the difference digital data has 1-bit “sign bit” and 4 bits.
The case where data is transmitted as "difference absolute value digital data" has been illustrated. The differential digital data is input to the signal line drive circuit 30 together with the horizontal clock signal and the control signal.

Here, the transmission line 2 for transmitting the differential digital data from the gate array 10 to the signal line drive circuit 30.
The order of the 0A to 20G arrays is as follows.

20A horizontal clock signal HC 20B sign bit SB 20C most significant bit difference data MSB 20D least significant bit difference data LSB 20E Difference data 2B of 2nd bit from upper 20F Difference data 3B from the upper 3rd bit 20G control signal CS

That is, the difference data lines are not arranged in the bit order from the most significant bit to the least significant bit but are arranged alternately. By arranging the transmission paths for the differential data in this way, EMI can be further reduced. This point will be described later in detail with reference to FIGS. 4 and 5.

Now, further explaining the overall configuration of the liquid crystal display device of FIG. 1, the signal line drive circuit 30 includes a vertical difference processing demodulation circuit inside, and the input difference digital data is converted into image data. Demodulate. The demodulated image data is latched by the latch circuit inside the signal line drive circuit 30 to the horizontal synchronizing signal included in the control signal CS, and then becomes analog image data by the D / A converter inside the signal line drive circuit 30. It is output to the panel 60.

On the other hand, the scanning line driving circuit 50 has a shift register, and the shift register controls the control signal CS.
After the vertical synchronization signal included in the vertical synchronization signal is latched, the scanning line selection signal having the same pulse width as the vertical synchronization signal is sequentially shifted in synchronization with the vertical clock signal VC.

The liquid crystal panel 60 has pixels arranged in a matrix, and each pixel has a switching element (for example, TF) which is opened / closed by a voltage of a scanning line selection signal.
T: Thin Film Transistor). When a predetermined voltage is applied to the scanning line selection signal, the switching element connected to the corresponding scanning line opens, the signal line voltage is applied to the corresponding pixel electrode, and an image is displayed on the liquid crystal panel 60.

FIG. 2 is a schematic diagram illustrating the configuration of the vertical difference processing modulation circuit provided inside the gate array 10. The input image data is input to the line memory 10A and the difference circuit 10B. The line memory 10A temporarily holds the input image data, delays it for a predetermined period, and then outputs the image data (hereinafter, referred to as “previous image data”) PVS held in the difference circuit 10B.

In this embodiment, the line memory 10
The previous image data PVS is delayed by one horizontal scanning period by A.
Is output. The difference circuit 10B performs an exclusive OR operation on the image data VS and the previous image data PVS and outputs difference data DD. When the image data VS is represented by n bits, the sign bit is 1 in the difference data DD.
Since bits are required, the data becomes (n + 1) bits.

FIG. 3 is a schematic diagram illustrating the configuration of the vertical difference processing demodulation unit provided inside the signal line drive circuit 30. Input difference data DD and line memory 30A
The previous image data PVS held in is input to the addition circuit 30B. The adder circuit 30B performs an exclusive OR operation on the difference data DD and the previous image data PVS, and outputs the image data VS. The output image data VS is input to the line memory 30A and held for one horizontal scanning period, and then input to the adder circuit 30B as the previous image data PVS as described above.

FIGS. 4A and 4B are graphs showing a histogram of image data of one frame and a histogram of difference absolute value data thereof. The histogram of the image data and the absolute difference value data illustrated here is X
This is a case of GA (1024 × 768 × 3 pixels) size and the number of gradations is 8 bits (256 gradations).

It can be seen that the image data before the vertical difference processing has a distribution over a wide gradation range as shown in FIG. 9A and contains high frequency components. On the other hand, the difference absolute value data obtained by performing the vertical difference processing has less high-gradation data, and is 0.
The data has a distribution that is concentrated in, and high frequency components almost disappear.

FIGS. 5 (a) and 5 (b) are tables summarizing the number of bit fluctuations of the 8-bit red, green, and blue data for the image data and the difference absolute value data. Also, FIG.
(C) is a table summarizing the ratio of the difference absolute value data to the number of bit changes of the image data. Here, “the number of bit fluctuations” is the number of times each of the 8 bits of image data transits from L (0) to H (1) or from H (1) to L (0).

As can be seen from FIG. 5, by performing the vertical difference processing, the number of bit fluctuations of the image data on the upper bit side is reduced. Further, the ratio increases as the number of higher bits increases. That is, the frequency of the difference absolute value data on the high-order bit side is smaller than that of the image data and also smaller than that of the difference absolute-value data on the lower bit side. Therefore, when the transmission paths 20 for transmitting the differential data from the gate array 10 to the signal line drive circuit 30 are alternately arranged in the bit order as illustrated in FIG. 1, a relatively high frequency signal is transmitted between the transmission paths. Since the transmission path for transmitting the low-frequency signal is arranged, it becomes possible to widen the interval between the transmission paths for transmitting the high-frequency signal with the same transmission path interval as the conventional one. As a result, it is possible to suppress EMI that occurs due to interference between high frequency signals.

FIG. 6 is a schematic diagram showing a concrete example in which transmission paths for differential digital data when an 8-bit video signal is subjected to vertical differential are arranged according to the present invention.

As shown in the figure, the sign bit SB is assigned to the transmission line 20A and the most significant bit MSB of the difference absolute value data is assigned to the transmission line 20B.
4 transmission lines of bits MSB to 4B and lower 4 bits 5
The four transmission lines B to LSB are alternately arranged.

By arranging the transmission lines in this way, a transmission line for transmitting a signal of a relatively low frequency is arranged between transmission lines for transmitting a signal of a high frequency, which is the same as the conventional one. With the transmission line spacing, it is possible to widen the spacing between the transmission paths through which high frequency signals are transmitted. Further, when the vertical correlation of the input image data is higher, the upper bits of the difference data become almost 0, and the transmission line thereof becomes in a state substantially similar to the ground line. Therefore, the shielding effect is obtained, and the generation of EMI can be suppressed more effectively.

In the specific example shown in FIG. 6, all the transmission lines of the high-order bit and the low-order bit are arranged alternately as a method having a relatively high EMI reduction effect, but as another arrangement method, Even if the transmission paths for each bit of the differential digital data are arranged in an array other than ascending or descending order with respect to the number of bits, the effect of reducing EMI can be obtained.

For example, as shown in FIG. 7A, when 8-bit differential digital data are arranged in ascending order with respect to the number of bits, a transmission line for transmitting the differential digital data of the third bit is used. The transmission lines for transmitting the differential digital data of the 7th bit may be exchanged and arranged as shown in FIG. 7B.

In this case, in the arrangement of FIG. 7 (a), a 7-bit line in which a relatively high-frequency signal is similarly transmitted is adjacent to the transmission line of the least significant bit in which a relatively high-frequency signal is transmitted. Although the eye transmission lines are arranged, in the arrangement of FIG. 7B, at least 7 lines are provided adjacent to the transmission line of the least significant bit.
The transmission line of the 3rd bit having a frequency lower than that of the differential digital data of the bit is arranged.

Also, regarding the transmission line arranged adjacent to the 7th bit transmission line through which a relatively high-frequency signal is transmitted, as compared with the arrangement of FIG. b)
The arrangement of is a transmission line having a relatively low frequency.

As described above, by arranging the transmission lines of each bit of the differential digital data in an array other than the ascending order or the descending order with respect to the number of bits, the EMI reducing effect can be obtained.

As a more specific arrangement method, the lower bit transmission line for transmitting a relatively high frequency signal may be arranged so as to be sandwiched by the upper bit transmission lines.

FIG. 8 is a schematic diagram showing another specific example in which transmission lines for 8-bit differential digital data are arranged according to the present invention.

That is, in the case of the specific example of FIG. 7A, the transmission lines of the code bit SB and the least significant bit LSB are distributed to both ends of the nine transmission lines. Sign bit S
B generally has the largest number of transitions among the difference data and has the highest frequency component. Therefore, by separating the transmission line of the code bit SB having the highest frequency component from the transmission line of the least significant bit LSB having the next highest frequency component, the generation of EMI due to these interferences can be more effectively performed. Can be suppressed.

Furthermore, in the case of this example, the difference data 7B of the 7th bit is assigned to the central transmission line of the nine transmission lines. The 7th bit difference data is
Since it often has the third highest frequency component, by separating this from the code bit SB and the least significant bit LSB, it is possible to more effectively suppress the occurrence of EMI.

That is, this example illustrates an arrangement in which transmission lines for signals having high frequency components are separated as much as possible, and transmission lines for low frequency components are provided between them.

On the other hand, in the case of the concrete example shown in FIG.
Sign bit SB, least significant bit LSB and 7th bit 7
The position of the transmission line B is the same as that of the specific example of FIG. 9A, but the arrangement of 6 bits 6B to the most significant bit MS is different.
That is, the most significant bit MSB is provided adjacent to the sign bit SB, and the second bit 2B is provided adjacent to the least significant bit LSB. By doing so, the most significant bit MSB having the lowest frequency component is adjacent to the code bit SB having the highest frequency component, and the second bit 2B having the second lowest frequency component has the second highest frequency component. It can be adjacent to the least significant bit LSB having a component, and the shield effect can be improved.

In this example, for the same reason, the fifth bit 5B is provided between the sign bit and the seventh bit 7B, and the sixth bit 6B is the least significant bit LSB and the seventh bit 7B. It is provided between.

That is, it is possible to further effectively suppress EMI by separating transmission lines having high frequency components as much as possible and by adjoining transmission lines having frequency components as low as possible.

Although FIG. 8 exemplifies the case where the image data is 8 bits, the present invention can be similarly applied to the case of handling image data other than 8 bits.

If the image data has an odd number of bits,
Assuming that the number of bits of image data is n, for example, a code bit and an upper (n-1) / 2-bit transmission line and a lower (n)
The same effect can be obtained by alternately arranging +1) / 2-bit transmission lines.

As described above, by arranging the differential data transmission lines on the board in an order different from the bit order according to the contained frequency, despite the same transmission line spacing as in the conventional case, If the spacing between the transmission lines that transmit high-frequency signals is widened, and if the vertical correlation of the image data is very high, the ground line should be placed between the transmission lines that transmit high-frequency signals. Since the same effect can be obtained, EMI generated by transmitting image data
Can be reduced.

On the other hand, in the present invention, it is possible to further reduce the EMI by appropriately inserting a ground line between the transmission lines of the differential data and adjusting the interval between the transmission lines. Is.

FIG. 9A is a schematic diagram showing a specific example in which a ground line is inserted between transmission lines for differential data. In this specific example, the ground line G is provided adjacent to the code bit SB having the highest frequency component. Also, the least significant bit LS having the next highest frequency component
The ground line G is also provided adjacent to the B transmission line. In this way, although the entire width of the transmission line 20 is slightly widened, it is possible to reduce the EMI due to the shield effect.

On the other hand, FIG. 9B is a schematic diagram showing a concrete example in which the distance between the transmission lines of the differential data is adjusted. In the case of this example, the sign bit SB having the highest frequency component
However, it is provided a little away from the adjacent transmission line. Also, the least significant bit LS having the next highest frequency component
The B transmission line is also provided slightly away from the adjacent transmission line. Even with this configuration, the width of the entire transmission line 20 is slightly widened, but interference between the transmission lines can be reduced and EMI can be reduced.

In the above description, the transmission line 20 between the gate array 10 of the liquid crystal module and the signal line drive circuit 30 is taken as an example. For example, in a notebook computer, image data inside the computer main body is used. Similar effects can be obtained also in a transmission path through which image data subjected to vertical difference processing is transmitted, such as a graphic controller of an output unit and a gate array of a liquid crystal module.

Regarding the display system of the image display device, the present invention is applicable to various displays such as plasma display (PDP), field effect display (FED), LED display, EL display, etc., which transmit digital image data. The same effects can be obtained by applying the invention.

(Second Embodiment) Next, as a second embodiment of the present invention, one of the differential data transmission lines,
An image display device that cancels interference and suppresses EMI by causing an inversion signal of an adjacent transmission line to flow will be described.

FIG. 10 is a schematic view showing the structure of the main part of the liquid crystal display device according to this embodiment. The overall configuration is the same as that described above with respect to the first embodiment, but in this embodiment, the determination signal DS is transmitted together with the difference data DD.

FIG. 10 shows that when the image data is 3 bits,
That is, the case where the difference data is transmitted as the 1-bit code bit and the 3-bit difference absolute value data is illustrated. Also in this embodiment, as in the first embodiment, a vertical difference processing modulation circuit is provided inside the gate array 10, and a vertical difference processing demodulation circuit is provided inside the signal line drive circuit 30.

However, in the present embodiment, the vertical difference processing modulation circuit corresponding to the upper bit side portion of the difference absolute value data has the difference absolute value data and the lower order of the difference absolute value data transmitted through the adjacent transmission paths. It is provided with a selection switch for outputting the inverted bit of the half bit side or the inverted bit of the sign bit. That is, assuming that the image data has n bits, when n is an odd number, the higher bit side (n + 1)
/ 2 bits, when n is an even number, it outputs the difference absolute value data as it is to the upper bit side n / 2 bits, or when n is an odd number, it is the lower bit side (n-1) / 2 bits. If the sign bit, n, is an even number, a selection switch for outputting n / 2 bits and an inverted bit of the sign bit is provided.

FIG. 11 is a schematic diagram showing the output side of the vertical difference processing modulation circuit in this embodiment when the image data is 3 bits. The input image data is processed by the same processing as that of FIG.
B and 3-bit difference absolute value data MSB, 2B, SL
Converted to B.

Next, the upper 2 bits of the absolute difference data,
That is, the difference absolute value data M of the most significant bit and the second bit
With respect to SB and 2B, the signal determination circuit 10C determines whether the bit in a predetermined period is L (0). In this embodiment, all the bits in one horizontal scanning period are L.
It is determined whether it is (0). The input most significant bit and the second-bit difference absolute value data MSB, 2B are held in the line memory inside the signal determination circuit 10C until the determination of one horizontal scanning period is completed, and are output after the determination is completed. It

The most significant bit and the second bit signal decision circuit 10C are connected to each other by a decision synchronization signal,
When it is determined that the input bit is not L (0) in either one, the determination result is reflected in the other. That is, in the present embodiment, it is determined whether or not the most significant bit and the second bit of the first horizontal scanning period are all L (0). The determination result is input to the changeover switch 10F as a determination signal.

In the changeover switch 10F, the (n + 1) / 2-bit differential absolute value data on the high-order bit side is directly transmitted to the (n + 1) / 2-bit transmission line on the high-order bit side, or these transmission lines are transmitted. Then, it is switched whether to transmit (n-1) / 2 bits on the lower bit side or an inverted bit of the sign bit. In the present embodiment, when the most significant bit and the second most significant bit are all L (0) in one horizontal scanning period, the sign bit and the inverted bit of the third most significant bit are transmitted.

The sign bit and the signal of the third bit are temporarily held in the line memory 10D, and the most significant bit and the signal of the second bit output after the determination of one horizontal scanning period is completed by the signal determination circuit. It is output in synchronization. The output sign bit and the least significant bit and the output of 2 bits selected by the changeover switch 10F are input to the phase adjustment circuit together with the control signal and the determination signal.

In the phase adjusting circuit 10G, each bit data is latched by the synchronizing signal included in the control signal CS,
It is output, and this is input to the signal line drive circuit 30. Transmission line 20 between the gate array 10 and the signal line drive circuit 30
Is arranged on the substrate such that the transmission line for transmitting the half bit or the sign bit on the lower bit side and the transmission line for transmitting the inverted bit thereof are adjacent to each other. That is,
In the case of this example, the transmission line of the most significant bit MSB or an inverted bit of the code bit is adjacent to the transmission line of the code bit SB, and the transmission line of the least significant bit LSB is adjacent to the transmission line of the second bit 2B or the least significant bit. An inverted bit transmission line is arranged.

FIG. 12 is a schematic view illustrating the configuration of the input section of the signal line drive circuit 30 in this embodiment. Among the transmitted difference data, the transmission line that transmits either the inverted data of the data transmitted on the adjacent transmission line or the difference data is input to the changeover switch 30C. The changeover switch 30C switches between the transmitted data and L (0) based on the determination signal DS.

In this specific example, either the most significant bit MSB of the differential absolute value data or the inverted bit of the sign bit SB is transmitted on the transmission line adjacent to the transmission line of the sign bit SB. Therefore, the changeover switch 3
When 0C causes the most significant bit to be transmitted, it remains unchanged. When the inverted bit is transmitted, 1
In the horizontal scanning period, the most significant bit is originally L
Since it should have been (0), it is connected to the L (0) signal,
It is input to the vertical difference processing demodulation circuit 30D. In the vertical difference processing circuit 30D, image data (3 bits in this example) is demodulated by the same processing as that described above with reference to FIG. 3, and output to the latch circuit inside the signal line driving circuit 30.

By transmitting the image data as described above, the differential signal is transmitted to the adjacent transmission lines, the electromagnetic wave interference is canceled and the E generated from the transmission line is generated.
It is possible to reduce MI.

Normal color image data is red,
The signals corresponding to green and blue are respectively transmitted, but in this case as well, the same processing as described above may be performed for each of red, green and blue. Further, in the above-described specific example, all the bits on the upper half side (most significant bit and second bit) are determined by one determination signal, but determination may be performed by using a plurality of determination signals. .

For example, when the image data is 8 bits,
The upper 4 bits may be individually determined, or the 2 bits may be combined and the determination may be performed using two determination signals.

(Third Embodiment) Next, as a third embodiment of the present invention, in the configuration of the above-described second embodiment, the determination signal is transmitted during the blanking period of the differential data. The image display device will be described. That is, also in the present embodiment, the input image data is modulated into difference data by the same processing as in the first and second embodiments. However, in the second embodiment, the differential data and the determination signal are transmitted to the signal line drive circuit 30, but in the present embodiment, the determination signal is transmitted during the horizontal blanking period of the differential data.

FIG. 13 is a schematic view illustrating the configuration of the output unit of the gate array in the image display device of this embodiment. As shown in the figure, the determination signal DS output from the signal determination circuit 10C is input to the phase adjustment circuit 10H. Then, the phase adjustment circuit 10H has half the bits on the upper bit side (in FIG. 13, the most significant bit and the second bit).
The determination signal DS is transmitted to the signal line driving circuit 30 by using each of the transmission lines.

Here, the determination signal DS can be transmitted by utilizing the horizontal blanking period of the image data. For example, when the image data is 3 bits, the horizontal blanking period of the data of the inverted bit of the most significant bit or the sign bit and the horizontal blanking period of the data of the inverted bit of the second bit or the least significant bit from the most significant bit. Can be transmitted by setting H (1) or L (0) respectively.

FIG. 14 is a schematic view illustrating the configuration of the input section of the signal line drive circuit in the image display device of this embodiment. The basic configuration thereof is the same as that described above with respect to the second embodiment, but in the present embodiment, the determination signal separation circuit 30E detects H (1) and L (0) in the horizontal blanking period of the difference data. The switching is performed by making a determination and outputting the determination signal to the changeover switch 30C.

By transmitting the image data as described above, it is possible to obtain the same EMI reducing effect as that of the second embodiment without separately providing a transmission line for the determination signal DS.

(Fourth Embodiment) Next, as a fourth embodiment of the present invention, one horizontal period is divided into a plurality of regions,
An image display device that determines whether to transmit the difference data of the upper-half bit side in each area as it is or to transmit an inverted signal of a signal transmitted through an adjacent transmission path will be described.

FIG. 15 is a schematic view illustrating the configuration of the output unit of the gate array in the image display device according to this embodiment. The basic configuration is the same as that described above with respect to the third embodiment, and in this embodiment as well, the determination signal DS of the signal determination circuit 10I is the phase adjustment circuit 30J.
Will be input to.

In the case of the above-described third embodiment, the signal determination circuit 10C makes a determination on the data of one horizontal scanning period, but in the case of the present embodiment, the signal determination circuit 10I.
Then, one horizontal scanning period is divided into a plurality of areas, and the determination is performed for each area.

For example, in the case of transmitting image data to an SVGA liquid crystal panel, one horizontal scanning period is divided into 400 dots in the first half and 400 dots in the second half, and the difference absolute value data to be transmitted is divided into respective areas. It is determined whether or not all are L (0).

This determination signal DS is output to the changeover switch 1
0F is input to switch transmission data, and is also input to the phase adjustment circuit 10J. Phase adjustment circuit 1
At 0J, the determination signal DS is input during the horizontal blanking period of the transmission data based on the input determination signal DS.

For example, when one horizontal scanning period is divided into 400 dots in the first half and 400 dots in the second half as described above, the determination signal of the most significant bit is the horizontal block of the code bit transmitted through the adjacent transmission line. 40 in the first half of the ranking period
In the horizontal blanking period of the 0-dot determination signal and the most significant bit or the inversion bit of the sign bit, the latter 400-dot determination signal can be transmitted. The determination signal of the second bit from the most significant bit is similarly processed.

Normally, the liquid crystal panel has a signal line driving circuit 3
A plurality of driver ICs are connected as 0. For example, as the signal line drive circuit 30, a driver I having 300 outputs
When driving an SVGA liquid crystal panel using C, the number of signal lines of the liquid crystal panel is 800 × 3 (RGB) = 240.
It becomes 0, and eight driver ICs as a signal line drive circuit are required.

That is, in this example, the first four
Each of the signal line drive circuits (driver ICs) uses the horizontal blanking period of the sign bit and the half bit on the upper bit side of the difference absolute value data as the determination signal DS, and the latter four 4
Each signal line drive circuit (driver IC) uses the horizontal blanking period of the lower half bit of the bit as the determination signal DS. In this case, the configuration of the latter four signal line drive circuits can be the same as that described above with reference to FIG.

FIG. 16 is a schematic diagram illustrating the configuration of the first four signal line drive circuits. That is, in the case of this specific example, the determination signals of the first four signal line driving circuits are H level during the horizontal blanking period of the sign bit and the least significant bit.
Since it is transmitted by giving (1) or L (0), the determination signal DS separates the sign bit and the least significant bit from the determination signal separation circuit 30F and inputs the determination signal DS to the changeover switch 30G. Other operations are shown in Figure 1.
It is similar to that illustrated in FIG.

According to the present embodiment, by transmitting the image data in this way, it is possible to obtain the same EMI reduction effect as in the second embodiment without increasing the number of transmission lines for the determination signal.

Furthermore, in this embodiment, since one horizontal period is divided into a plurality of pieces to determine whether or not to transmit inverted data, the chances of transmitting inverted data are increased, and EMI due to electromagnetic wave interference is further increased. It becomes possible to suppress.

In the above specific example, one horizontal scanning period is divided into two periods for determination, but it may be divided into three or more periods. In this case, the horizontal blanking period is divided into a plurality of periods, and the respective determination signals are input. For example, when the determination is performed by dividing one horizontal scanning period into four periods, the horizontal blanking period is divided into two periods and the determination signal is input.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to the above specific examples.

For example, as the image display device to which the present invention can be applied, various types other than the liquid crystal display device can be cited as mentioned above.

Further, the arrangement relationship of the pixels, the number of pixels, or the type and number of color elements are not limited to the above-mentioned specific examples.

That is, the present invention is not limited to each specific example, and various modifications can be carried out without departing from the scope of the invention, and all of them are included in the scope of the present invention. .

[0099]

As described in detail above, according to the present invention,
It is possible to reduce the EMI generated by the transmission of digital image data in the vertical difference method. Further, by adding a relatively small-scale circuit, it is possible to appropriately transmit the inverted signal and further reduce the EMI.

As a result, according to the present invention, EMI
It is possible to realize a compact image display device with extremely high pixel density while suppressing the above, and the industrial advantage is great.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a part of a liquid crystal display device according to a first embodiment of the present invention.

2 is a schematic diagram illustrating the configuration of a vertical difference processing modulation circuit provided inside the gate array 10. FIG.

3 is a schematic diagram illustrating the configuration of a vertical difference processing demodulation unit provided inside the signal line drive circuit 30. FIG.

FIG. 4A and FIG. 4B are graphs showing a histogram of image data of one frame and a histogram of difference absolute value data thereof.

5 (a) and 5 (b) are tables summarizing the number of bit changes of 8-bit red, green, and blue data for image data and absolute difference data, and FIG. 5 (c) is a bit change of image data. It is the table which summarized the ratio of the difference absolute value data to the number of times.

FIG. 6 is a schematic diagram showing a specific example in which transmission paths of differential digital data when an 8-bit video signal is subjected to vertical differential are arranged according to the present invention.

FIG. 7A illustrates a case where transmission lines of 8-bit differential digital data are arranged in ascending order of the number of bits, and FIG.
FIG. 6 is a schematic view illustrating a specific example in which the bits are arranged in an order different from the bit order according to the present invention.

FIG. 8 is a schematic diagram showing another specific example in which 8-bit differential digital data transmission lines are arranged according to the present invention.

FIG. 9A is a schematic diagram showing a specific example in which a ground line is inserted between transmission lines for differential data, and FIG. 9B shows a specific example in which the interval between transmission lines for differential data is adjusted. It is a schematic diagram.

FIG. 10 is a schematic diagram showing a main configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 11 is a schematic diagram showing an output unit of the gate array 10 in the present embodiment when the image data is 3 bits.

FIG. 12 is a schematic diagram illustrating the configuration of an input unit of the signal line drive circuit 30 according to the second embodiment of the present invention.

FIG. 13 is a schematic view illustrating the configuration of an output unit of a gate array in the image display device according to the third embodiment of the present invention.

FIG. 14 is a schematic view illustrating the configuration of an input unit of a signal line drive circuit in the image display device according to the third embodiment of the present invention.

FIG. 15 is a schematic view illustrating the configuration of an output unit of a gate array in the image display device according to the fourth embodiment of the present invention.

FIG. 16 is a schematic diagram illustrating the configuration of the first four signal line drive circuits.

FIG. 17 is a conceptual diagram illustrating the overall configuration of an image display system that employs LDVS.

[Explanation of symbols]

10 gate array 10A, 10D line memory 10B difference circuit 10C signal judgment circuit 10E, 10F switch 10G, 10H, 10J Phase adjustment circuit 10I signal determination circuit 20 transmission lines 20A to 20I transmission line 30 signal line drive circuit 30A line memory 30B adder circuit 30C switch 30D vertical difference processing demodulation circuit 30E, 30F Judgment signal separation circuit 30G switch 30J Phase adjustment circuit 50 scanning line drive circuit 60 LCD panel 100B liquid crystal display device 110 Image data output section 120 modulation circuit 130 demodulation circuit 140 gate array 150 signal line drive circuit CS control signal DD difference data DS judgment signal DSS judgment synchronization signal G ground line HC horizontal clock signal LSB least significant bit MSB most significant bit Image data before PVS SB sign bit VC vertical clock signal VS input video signal VS image data

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 621 G09G 3/20 621M 633 633P (72) Inventor Kobayashi, etc. Komukai, Kawasaki City, Kanagawa Prefecture Toshiba Town No. 1 In stock company Toshiba R & D Center (72) Inventor Haruhiko Okumura Komukai, Kouki-ku, Kawasaki City, Kanagawa No. 1 Toshiba Town R & D Center F term (reference) 2H093 NC15 NC23 NC24 NC29 ND40 5B056 BB11 BB28 HH03 5C006 AA22 AF73 BB16 BC02 BF05 BF24 BF49 FA32 5C080 AA10 BB05 CC03 DD12 FF11 GG12 JJ02 JJ05

Claims (6)

[Claims] 1. A differential modulation circuit for inputting digital image data and outputting a difference with respect to held data as differential digital data; a transmission line for transmitting the differential digital data output from the differential modulation circuit; A differential demodulation circuit that inputs the differential digital data via the transmission path, adds the held data and outputs digital image data, and the digital image data output from the differential demodulation circuit is analog image data. A conversion circuit for converting the analog image data output from the conversion circuit, and an image display unit for displaying an image by inputting the analog image data output from the conversion circuit. Data and a plurality of bits of difference absolute value data representing an absolute value of the difference, wherein the transmission path includes the difference An image display device having a plurality of transmission lines corresponding to respective bits constituting digital data, the transmission lines being arranged in parallel in an order different from the bit order of the difference absolute value data. 2. Between the transmission line for transmitting the code data and the transmission line for transmitting the least significant bit data of the difference absolute value data, an upper side of the difference absolute value data is provided. The image display device according to claim 1, further comprising a transmission line for transmitting data of any bit. 3. A transmission line for transmitting upper bit data of the difference absolute value data and a transmission line for transmitting lower bit data of the difference absolute value data are alternately arranged. The image display device according to claim 1, wherein the image display device is provided. 4. The differential modulation circuit includes a signal determination unit that determines whether or not the data of any one of the upper bits of the differential absolute value data has a constant value for a predetermined period, and the data determination unit. If the signal determination unit determines that is a constant value over a predetermined period, the data transmitted on the transmission line adjacent to the transmission line transmitting the data is inverted, and the inverted data is transmitted to the transmission line of the data. A data inverting unit, wherein the differential demodulation circuit has a changeover switch unit that replaces the inverted data with the constant value data when the inverted data is transmitted to the transmission line. The image display device according to claim 1. 5. The result of the determination by the signal determination unit is
The image display device according to claim 4, wherein the differential absolute value data is transmitted to the changeover switch unit via a transmission line thereof during a blanking period. 6. The image display device according to claim 4, wherein the predetermined period is one horizontal scanning period or a period obtained by dividing one horizontal scanning period.