KR100848093B1 - A dithering apparatus and dithering method of liquid crystal display - Google Patents

Abstract

The dithering apparatus of the present invention includes a random number generator, a register, a counter, a beta or gate, an operator and an adder. The random number generator generates random number data of 1 or 0. The register receives a load signal LOAD from the pixel counter and stores random number data. The counter counts a pixel number (C) indicating pixel coordinates for displaying image data, a line number (L) indicating horizontal lines for displaying image data, and a frame number (F) indicating frame information, respectively. And a pixel counter, a line counter, and a frame counter that output a value of 0 or 1 depending on the value. An exclusive OR gate performs an exclusive OR operation on the line number (L) and frame number (F) values. The operator performs a logic operation according to the dithering method described above on the 2-bit sub data LSB of the 8-bit input image data and the data output from the register, the pixel counter, and the beta or gate, thereby correcting the correction factor (P). Or P +). The adder generates the corrected image data by adding the data MSB except the lower 2 bits from 8 bits and the output P or P + of the calculator to provide the corrected image data to the data driver of the liquid crystal display.

Description

Dithering apparatus and dithering method of liquid crystal display device {A DITHERING APPARATUS AND DITHERING METHOD OF LIQUID CRYSTAL DISPLAY}

1 is a diagram illustrating an example of mosaic pattern data in which data of adjacent pixels differs from each other.

FIG. 2 is a diagram illustrating a result of performing dithering on the data shown in FIG.

3 is a diagram illustrating an operation algorithm for each pixel number and a lower two bits according to a corresponding frame and a corresponding line number.

4 is an example showing the calculation result of FIG. 3.

5 is an exemplary diagram illustrating a display result of 4 × 4 space for each lower 2 bits according to the dithering algorithm of the present invention.

6 is a diagram showing a liquid crystal display device according to an embodiment of the present invention showing image data using the dithering method described above.

7 illustrates a timing controller for performing a dithering method according to an embodiment of the present invention.

8 is a diagram illustrating an example of the random number generator of FIG. 7.

The present invention relates to a dithering device and a dithering method of a liquid crystal display device, and more particularly, to a dithering device and a dithering method of a liquid crystal display device in which temporal regularity and spatial regularity are excluded.

) 컬러수가 구현될 수 있다. In a display device such as an active matrix liquid crystal display device, a display operation is performed according to a color signal provided from a graphic data generator. Such a data generating device provides digital data as a color signal. Usually, 6 bits of digital data are allocated to one pixel in the liquid crystal display. That is, each color of red (R), green (G), and blue (B) has {2} ^ {6} = 64 display (gradation) levels, and 262144 (=

Color number can be implemented.

However, with the recent development of a multimedia environment, display devices of personal computers or similar devices are required to display a greater number of colors. Accordingly, a graphic generating device providing color signal data of 6 bits or more has emerged. However, in order to display a larger number of colors, the performance of the display device such as the liquid crystal display device as well as the graphic data generating device must also be improved. For example, the number of terminals of the source driver integrated circuit used as the data driver of the liquid crystal display device must increase, and the data bus line of the internal circuit must also increase. However, if this is the case, there is a problem that the manufacturing cost of the display device increases.

In order to overcome this problem, a conventional method of expressing full color with a 6-bit driver integrated circuit (IC), for example, by dithering the lower 2 bits of the 8-bit data input by the user (LSB) is performed. It was. Specifically, a frame dithering method has been used such that the upper six bits inputted during four frames and the value obtained by adding "1" to the upper six bits are output from the timing controller at a predetermined ratio.

For example, when '10011011' 8-bit data is input, the timing controller converts the data into 10011100 in the first frame time, 10011100 in the second frame time, 10011000 in the third frame time, and 10011100 in the fourth frame time. Since the lower 2 bits are 00, only the upper 6 bits are output to the 6-bit driver IC. When converted into decimal number, the input value is 155, and it displays the LCD with luminance corresponding to 156, 156, 152, and 156 for 4 frames, so the afterimage effect in human eyes is (156 + 156 + 152 + 156) / 4 = 155 so that the user can feel the same gray level as the input.

When the above description is made more general, when 8 bits of data having the lower 2 bits of 11 are input to the timing controller, the timing controller inputs the input 8 bits of data in the first frame to DATA [7: 0] -11+. 100, DATA [7: 0] -11 + 100 for the second frame, DATA [7: 0] -11 + 000 for the third frame, DATA [7: 0] -11 + 100 for the fourth frame Change it.

At this time, DATA [7: 0] -LSB [1: 0] +000 → P, DATA [7: 0] -LSB [1: 0] +100 → P '(where DATA [7: 0] is entered 8 bits of data, LSB [1: 0] means lower 2 bits of data.) According to the lower 2 bits of the input data, the timing controller can process data as shown in Table 1.

LSB [1: 0] First frame Second frame Third frame Fourth frame                                                  00 P P P P                                                  01 P P  P ' P                                                  10  P ' P  P ' P                                                  11  P '  P ' P  P '                                                 

By doing this, it is possible to make a display device which performs data processing of 8 bits using a 6 bit data driver IC.

However, when driving a display device such as a liquid crystal display by the dithering algorithm, the following problem occurs.

FIG. 1 is a diagram illustrating an example of mosaic pattern data in which adjacent pixels have different data from each other, and FIG. 2 is a diagram illustrating a result of performing dithering on the data shown in FIG. 1 by a conventional method.

For example, as illustrated in FIG. 1, when mosaic-type data having different data between adjacent pixels is supplied, when the conventional dither algorithm shown in Table 1 is used, the data as shown in FIG. Is output. In this case, there is a problem in that image quality is deteriorated due to shaking of hatched portions for each frame (time).

This phenomenon is a problem that occurs because the dithering algorithm has regularity of a certain period in time.

 SUMMARY OF THE INVENTION The present invention has been made in an effort to solve such a problem, and to provide a dithering device and a dithering method of a liquid crystal display device for dithering image data that excludes temporal and spatial regularity.

According to an aspect of the present invention, there is provided a dithering device for dithering n-bit input image data, comprising: a random number generator for generating random number data; A pixel counter for counting pixel coordinates for displaying the image data and outputting corresponding pixel numbers; A line counter for counting horizontal lines for displaying the image data and outputting corresponding line numbers; A frame counter for counting frames for displaying the image data and outputting corresponding frame numbers; A register which stores the random number data at a specific pixel position according to the control of the pixel counter; An exclusive logical operator for performing an exclusive OR operation on the line number and the frame number; Logical operation is performed on the random number data and the pixel number output from the register and the data output from the beta logic operator according to the m-bit sub-data among the n bits of image data to generate image data in time, space, and probability. A calculator for generating a correction factor to be dithered with; An adder for adding first data, which is nm bits of data, or second data, which is one greater than the first data, by adding data other than the m bits and the correction factor of the operator among the n bits of image data; Is done.

The dithering method according to an aspect of the present invention is a dithering method for dithering n-bit input image data, the first data being upper data of (nm) bits according to the lower m bits of the n-bit input image data or Outputs second data one greater than first data, and a probability that the first data or the second data is displayed temporally and spatially is determined according to the m bits, and according to the pixel number, the frame number, and the random number. The location and time at which the first data or the second data are displayed are determined.

On the other hand, the liquid crystal display device of the present invention which performs dithering on n bits of input image data is formed in a region surrounded by a plurality of gate lines, a plurality of data lines crossing the gate lines, the gate lines and the data lines. A liquid crystal panel comprising a plurality of pixels arranged in a matrix form each having a thin film transistor connected to the gate line and the data line; Receive the n-bit input image data and the synchronization signal and perform an operation having a predetermined probability based on the frame number, the line number, and the pixel number according to the lower m-bit data among the input image data to be the higher (nm) bits. A timing controller for outputting one data or second data one larger than the first data as a corrected data value; A gate driver sequentially supplying scan signals to the gate lines; And a data driver for supplying a data voltage corresponding to the corrected data output from the timing controller to the data line.

Here, the timing controller includes a random number generator for generating random number data; A pixel counter for counting pixel coordinates for displaying the image data and outputting corresponding pixel numbers; A line counter for counting horizontal lines for displaying the image data and outputting corresponding line numbers; A frame counter for counting frames for displaying the image data and outputting corresponding frame numbers; A register which stores the random number data at a specific pixel position according to the control of the pixel counter; An exclusive logical operator for performing an exclusive OR operation on the line number and the frame number; Logical operation is performed on the random number data or the pixel number output from the register and the data output from the beta logic operator according to the m-bit sub-data among the n bits of image data, so that the image data can be time, space and stochastic. An operator for generating a correction factor to be dithered; An adder for adding first data, which is nm bits of data, or second data, which is one greater than the first data, by adding data other than the m bits and the correction factor of the operator among the n bits of image data; Is done.

Hereinafter, embodiments of the present invention will be described in detail.

In the present invention, when dithering and displaying n bits of input image data DATA [n-1: 0], the data P composed of the upper bits of (nm) bits or higher bits according to the lower m bits of the input image data. The data P + = P + 1, which is one greater than the data, is displayed. In this case, the data display of P or P + is not determined by a constant temporal and spatial regularity, but is a planar position corresponding to the time and line number L according to the frame number F, the pixel number C, and a random number. Probably determined according to (R).

Hereinafter, a method of dithering 8-bit input image data using lower 2 bits of data according to an embodiment of the present invention will be described as an example with reference to FIGS. 3 and 4.

3 is a diagram illustrating an operation algorithm for each pixel number and a lower two bits according to a corresponding frame and a corresponding line number, and FIG. 4 is an example of an operation result of FIG. 3.

The embodiment of the present invention generates a random number R in four pixel units based on the lower two bits of the input image data, calculates a current frame number F, and a line number L, and The random number R is logically operated as shown in FIG. 3 to display data of P or P +.

Here, the random number R is a value from the random generator mentioned later and has a value of 1 or 0. The frame number (F) is a number indicating the currently displayed frame and has a value of 1 or 0. When one frame number (F) is 1, two consecutive frame numbers are complementary so that the next frame number (F) is 0. . The line number L is a horizontal line number of the frame. For example, the line number L has a value of 1 for odd lines and 0 for even lines, and vice versa.

As shown in Fig. 3, when the lower two bits of the image data are '01', each of pixel numbers C, 0, 1, 2, and 3, in order, X'∧R ', X'∧R, X∧R', Each operation of X∧R is performed to display the result value. When the lower two bits are '10', X ', X, X', and X are sequentially performed. When the lower two bits are '11', operations of X'R, X'R ', X'∨R, and X'∨R' are performed in order.

Here, X is the result of the exclusive OR of the frame number F and the line number L, X 'is -X, and R' is -R.                     

For example, if the frame number F is '1', the line number L is '1', and the random number R is '0', the exclusive logical sum of the frame number F and the line number L is assumed. Since X, which is a result of, becomes '1', when the lower two bits are '01', '10', or '11', the result as shown in FIG. 4 can be obtained. As a result, when the value is '1', P + is applied as '0' to P as the corresponding pixel data.

As shown in the example of FIG. 4, P + is one when the lower two bits are '01' for every four pixel units in the horizontal direction, P + is two when the lower two bits are '10', and the lower two bits are '11'. ', Three P + are displayed.

Next, the dithering method described above with reference to FIG. 5 will be described in an enlarged manner in 4 x 4 space.

5 is an exemplary diagram illustrating a display result of 4 × 4 space for each lower 2 bits according to the dithering algorithm of the present invention.

The line number (L) is' 1, 0, 1, 0 'for each line, the frame number (F) is' 0', and the random number (R) generation result for each line is' 0, 1, 1, The case of 0 'will be described as an example.

As shown in FIG. 5, P + is displayed at 25% when the lower 2 bits are '01', P + is displayed at 50% when the lower 2 bits are '10', and when the lower 2 bits are '11'. You can see that P + is displayed at 75%.

This ratio is always maintained no matter how the random number R occurs.

As described above, the dithering method according to an embodiment of the present invention dithers image data in a planar manner and probably dithers the frame dithering in time, thereby simultaneously applying three dithering elements of time, space, and probability. .

That is, according to the embodiment of the present invention, regardless of occurrence of the random number R, only the probability that P or P + comes out according to the lower 2 bits is fixed and the frame number F, the line number L, and the random number ( According to R), the planar display position and the temporal occurrence probability were randomized.

Therefore, by removing temporal regularity and planar regularity, it is possible to eliminate the dithering defect display phenomenon in a specific pattern which has been a problem in the past.

6 is a diagram showing a liquid crystal display device according to an embodiment of the present invention showing image data using the dithering method described above.

As shown in FIG. 6, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel 100, a gate driver 200, a data driver 300, and a timing controller 400.

In the liquid crystal panel 100, a plurality of gate lines G1, G2, G3,..., Gn are formed to transmit the gate-on signal, and the data lines D1, which transmit a data voltage representing an image signal, are formed. D2, ..., Dm) are formed. Each region surrounded by the gate line and the data line constitutes a pixel, and each pixel is connected to the thin film transistor T and the drain electrode of the thin film transistor T, the gate electrode and the source electrode of which are connected to the gate line and the data line, respectively. (Cl).

The timing controller 400 receives an 8-bit image data signal DATA [7: 0] and a synchronization signal from a graphic controller (not shown). The lower two bits of data LSB [1: 0] of the image data signal DATA [7: 0] are processed according to the dithering method according to the embodiment of the present invention, so that the upper six bits of the value P or higher A value P + plus 6 bits is output as the corrected data value DATA '[5; 0].

The gate driver 200 sequentially applies a gate-on voltage to the gate line, thereby turning on the thin film transistor having the gate electrode connected to the gate line to which the gate-on voltage is applied.

The data driver 300 receives the corrected data values DATA ′ [5: 0] output from the timing controller 400, and then applies data voltages corresponding to the corrected data values to the data lines, respectively.

7 illustrates a timing controller for performing a dithering method according to an embodiment of the present invention.

As shown in FIG. 7, the timing controller 400 according to an embodiment of the present invention includes a random number generator 410, a register 420, a counter 430, a beta or gate 440, and an operator 450. And an adder 460.

The random number generator 410 generates random number data of one or zero.

The register 420 receives the load signal LOAD from the pixel counter 431 described later and stores the random number data.

The counter 430 counts pixel numbers C representing pixel coordinates for displaying image data, line numbers L representing horizontal lines for displaying image data, and frame numbers F representing frame information. And a pixel counter 431, a line counter 432, and a frame counter 433 for outputting a value of 0 or 1 according to the counted value.

The exclusive OR gate 440 performs an exclusive OR operation on the line number L and frame number F values.

The operator 450 divides the two-bit sub data LSB of the eight-bit input image data and the data output from the register 420, the pixel counter 431, and the beta or gate 440 as described above. By performing a logic operation according to the correction factor (P or P +) is generated.

The adder 460 generates the corrected image data by adding the data MSB excluding the lower 2 bits from 8 bits and the output P or P + of the calculator 450 to provide the corrected image data to the data driver 300.

As described above, according to the exemplary embodiment of the present invention, the arbitrary data according to the lower data LSB of the input image data, the frame number F, the line number L, the pixel number C, and the random number R are obtained. Since P or P + is output, the probability that P or P + is output is determined by the lower data LSB of the input image data, and the number of cases where P or P + is output is without spatial regularity and temporal regularity. It is output randomly.

8 is a diagram illustrating an example of the random number generator of FIG. 7.

As shown in FIG. 8, the random number generator according to the embodiment of the present invention includes a plurality of shift registers SR1, SR2,... SRi and exclusive or gates 411, 412 connected in series.

The shift registers SR1, SR2, ..., SRi are synchronized with the pixel clock PCLK and shift the value input from the exclusive OR gate 411.

The exclusive OR gate 411 performs an exclusive OR operation on the output values of the two arbitrary shift registers SR6 and SRi, and outputs the operation result to the shift register SR1.

The exclusive OR gate 412 performs an exclusive OR operation on the output value of any shift register, and outputs the calculated result as random number data R. FIG.

In general, since the probability that the output value of the exclusive OR gate becomes 0 or 1 is 50%, it is impossible to predict the output value at any time after a predetermined time elapses.

As a result, it is almost impossible to predict the information stored in each shift register, and the value obtained by performing the exclusive OR operation on the values of any two shift registers becomes more difficult to predict. In other words, the random number R can be generated.

As mentioned above, although embodiment of this invention was described, this invention is not limited only to the above-mentioned embodiment, Of course, various other deformation | transformation and change are possible.

For example, in the exemplary embodiment of the present invention, the liquid crystal display device is described as an example, but of course, it can be used in other display devices. In addition, the embodiment of the present invention has been described an example in which the dithering algorithm according to the embodiment of the present invention is applied to the timing controller. However, the dithering algorithm described above may be implemented through an independent dithering device.

Also, in the embodiment of the present invention, the dithering algorithm is performed by using the lower 2 bits of the 8-bit input image data, but the dithering algorithm may be performed by using the lower m bits of the n-bit image data. Since the above description is easily understood by those skilled in the art to which the present invention pertains, the detailed description thereof will be omitted.

As described above, according to the present invention, since a dithering algorithm having a predetermined probability is applied according to the lower bits, the frame number, the line number, the pixel number, and the random number of the input image data, dithering with temporal and spatial regularity is applied. The abnormal display characteristic caused by the algorithm can be solved.

Claims (4)

A dithering device that performs dithering on n bits of input image data, A random number generator for generating random number data; A pixel counter for counting pixel coordinates for displaying the image data and outputting corresponding pixel numbers; A line counter for counting horizontal lines for displaying the image data and outputting corresponding line numbers; A frame counter for counting frames for displaying the image data and outputting corresponding frame numbers; A register which stores the random number data at a specific pixel position according to the control of the pixel counter; An exclusive logical operator for performing an exclusive OR operation on the line number and the frame number; Logical operation is performed on the random number data and the pixel number output from the register and the data output from the beta logic operator according to the m-bit sub-data among the n bits of image data to generate image data in time, space, and probability. A calculator for generating a correction factor to be dithered with; An adder which adds data other than the m bits among the n bits of image data and a correction factor of the operator to output first data that is n-m bits of data or second data that is one greater than the first data. Dithering device comprising a. A dithering method for dithering n-bit input image data, Outputting first data that is upper data of (n-m) bits or second data that is one greater than the first data according to a lower m bit among the n bits of input image data; Determining a probability that the first data or the second data will be displayed in time and space based on the m bits; Determining a position and time at which the first data or the second data is displayed according to a pixel number, a frame number, and a random number; Dithering method comprising a. A liquid crystal display device for dithering n-bit input image data, A plurality of gate lines, a plurality of data lines intersecting the gate lines, a plurality of thin film transistors formed in a region surrounded by the gate lines and the data lines and connected to the gate lines and the data lines, respectively; A liquid crystal panel including pixels; Receiving the n-bit input image data and the synchronization signal, and performs a calculation having a predetermined probability based on the frame number, line number, pixel number according to the lower m bits of the input image data is a high (nm) bit A timing controller for outputting first data or second data having a value greater than the first data as a corrected data value; A gate driver sequentially supplying scan signals to the gate lines; And And a data driver for supplying a data voltage corresponding to the corrected data output from the timing controller to the data line. The method of claim 3, The timing controller A random number generator for generating random number data; A pixel counter for counting pixel coordinates for displaying the image data and outputting corresponding pixel numbers; A line counter for counting horizontal lines for displaying the image data and outputting corresponding line numbers; A frame counter for counting frames for displaying the image data and outputting corresponding frame numbers; A register which stores the random number data at a specific pixel position according to the control of the pixel counter; An exclusive logical operator for performing an exclusive OR operation on the line number and the frame number; Logical operation is performed on the random number data or the pixel number output from the register and the data output from the beta logic operator according to the m-bit sub-data among the n bits of image data, so that the image data can be time, space and stochastic. An operator for generating a correction factor to be dithered; An adder which adds data other than the m bits among the n bits of image data and a correction factor of the operator to output first data that is n-m bits of data or second data that is one greater than the first data. Liquid crystal display comprising a.

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