JP3222907B2 - Image data converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data conversion apparatus for converting image data into a signal that can be displayed on a display device, and more particularly to a case where the number of bits of image data representing each pixel differs from image to image. The present invention relates to a suitable image data conversion device.

[0002]

2. Description of the Related Art For example, VGA (Video Graphics Array)
2. Description of the Related Art In an image processing system that processes an image or image data including an XGA (Extended Gaphics Array) using an image processing device such as a computer, an image processing system that converts image data into various gradations or colors and displays the image data on a display device. Are known. In this case, the processing device expresses the number of bits representing the gradation or the number of colors of one pixel by the number of bits of 2 n, and changes the number of bits to, for example, 1, 2, 4, or 8 bits. Expand to memory.

In this processing system, a computer having a special function, such as a drawing function, writes a colored figure or the like as a code of a desired color into a memory developed into a bitmap. In this case, 8
If a color look-up table capable of expressing color information up to bits, that is, a so-called color packet, is used, 1 to 8
Pixel bits up to bits can be represented. For example, when one pixel is represented by one bit, black and white display, 2
4-color display when represented by bits, 16-color display when represented by 4 bits, 256 when represented by 8 bits
Color display can be performed simultaneously. These are selected according to the function of the display or the image required. In this case, the access speed from the computer changes depending on the number of bits of one pixel. For example, if a 32-bit personal computer is used, a single CP
U access makes it possible to draw 32 pixels, and in the case of 256-color display, one access makes it possible to draw 4 pixels.
The number of bits for the pixel is selected.

Conventionally, in order to change the number of bits of a pixel in such a processing system, for example, in the case of 2 bits / pixel, the data is allocated as data for four pixels from the most significant bit side and synchronized with the pixel clock. The data is transferred to the look-up table while being sequentially expanded to 8 bits. In the color lookup table, this data is converted into predetermined color data based on this data, and this data is converted into an analog signal by a DA converter. Also, other bits are converted into analog signals using the same process and displayed. More specifically, this processing system converts 8-bit image data read from the image memory into, for example, 1 bit.
A parallel-serial converter for converting the data into two bits, two bits, and four bits is provided. Each converter is connected to a bit extender that converts 1-bit, 2-bit, and 4-bit data into 8-bit extended data. 8 read from these dilators and image memory
Bit data is selected by a multiplexer, the output of the multiplexer is converted into predetermined color data or gradation data by a look-up table, converted into an analog signal by a DA converter, and displayed on a display or the like.

[0005]

However, in the above-mentioned prior art, a plurality of converters for performing parallel-to-serial conversion of the image data stored in the image memory in accordance with the number of bits are required. A plurality of extenders for converting data into extended 8 bits are required, and there has been a problem that the circuit becomes complicated. In particular,
A multiplexer for selecting these or 8-bit data from the image memory and outputting the selected data to the look-up table is required.
Since one type of 8-bit data is selected from the bit parallel data, a large and expensive circuit having a 32-bit input and an 8-bit output is required. There was a problem.

The present invention overcomes the drawbacks of the prior art and can supply image data having different bit numbers to a look-up table without using a large-sized multiplexer. It is an object of the present invention to provide an image data conversion device that can be reduced in size and cost.

[0007]

According to the present invention, in order to solve the above-mentioned problems, image data in which each pixel is represented by a predetermined number of bits is developed and stored in an image memory as a bit map. In an image data conversion device that converts image data read in parallel for each specific number of bits from an image memory into a signal that can be displayed on a display device and outputs the signal, the device reads out in parallel a specific number of bits. Input means for inputting the image data for each bit,
A timing control means for supplying a timing signal for each pixel represented by a predetermined number of bits to these input means and outputting the data for each pixel data, and a timing signal outputted from the input means by the timing signal of the timing control means. Data conversion means for outputting predetermined data that can be displayed on the display device based on the data for each pixel, and the timing control means shifts the timing signal for each predetermined bit to thereby input the pixel to the input means. It is characterized by outputting a timing signal for each.

In this case, the input means is constituted by two-input AND circuits, each bit of the image data is input to one input terminal of these AND circuits, and the timing from the timing control means is input to the other input terminal. The data may be output by inputting a signal.

The timing control means shifts the timing signal from the first shift register, which is formed by a plurality of shift registers and generates the timing signal of the most significant bit, to the lower-bit shift register. Preferably, each shift register outputs a timing signal to the input means based on the shifted timing signal.

In this case, the first shift register is provided with a blanking signal indicating transition from the blanking period to the image display period in the display device, a dot clock indicating pixel display timing, or a timing from the least significant bit shift register. The first timing signal may be generated based on the signal.

The data conversion means latches pixel data of a predetermined number of bits from the input means and outputs the data with a specific number of bits. The data conversion means is supplied with a specific number of bits from these latches. A look-up table for inputting data as a code and outputting predetermined color data or gradation data, and a digital-to-analog converting means for converting the data output from the look-up table into analog data and outputting the data.

In this case, the look-up table has a plurality of tables according to the number of bits for each pixel, and the table is selected according to the number of bits for each pixel.

[0013]

According to the image data conversion device of the present invention,
Image data read in parallel with a specific number of bits from the image memory is input to the input means for each bit, and the pixel data is supplied to the input means in response to a timing signal from the timing control means. Output every time.
In this case, the timing control means shifts the timing signal in accordance with the number of bits of each pixel and sequentially supplies the shifted timing signals to the input means. Thus, the image data is supplied to the data conversion means for each pixel, and the data conversion means can convert a signal displayable on the display device for each pixel based on the input data and output the converted signal.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an image data conversion apparatus according to the present invention. As shown in FIG. 1, the image data converter in this embodiment reads image data PID0 to PID7 supplied every 8 bits into one input terminal of each of AND circuits 100 to 114 for each bit. Data converter 20 for image data for each pixel
The data converter 200 supplies the data to the data converter 200 as a signal that can be displayed on a display such as a display by the data converter 200. In particular, in the image data converter of this embodiment, the number of bits representing one pixel is represented by, for example, 1, 2, 4, 8 bits and a plurality of bits, and the other one of the AND circuits 100 to 114 is correspondingly provided. A timing control circuit 300 is provided to supply timing data to each of the terminals and control the timing by supplying timing data to each pixel.

More specifically, the image data PID0 to PID7 supplied to the AND circuits 100 to 114 represent one pixel as 1, 2, 4, or 8 bits in a frame memory (not shown) by an image processing device. When the data is displayed on a display or the like, the data is read out from the frame memory in units of 8 bits and supplied to the AND circuits 100 to 114 for each bit. At the same time, a blanking signal
HBLK and dot clock DCLK are used in timing control circuit 30
Supplied to 0.

The timing control circuit 30 in this embodiment
0 indicates eight shift registers 310 to 380 connected in cascade.
It has. The first shift register 310 receives a blanking signal HBLK and a dot clock DCLK, and receives a blanking signal HBLK and a dot clock DCLK, and sends a control signal S0 to S6 of the second to eighth shift registers to a control circuit (not shown). This is a circuit that generates SCLK and a timing data of the most significant bit PID7 and a first timing signal T1 serving as timing data of a subsequent shift register. The first shift register 310 has an input terminal I to which a blanking signal HBLK is supplied, an input terminal C to which a dot clock DCLK is supplied, and an input terminal which receives a timing signal T8 fed back from the eighth shift register 380. R
And a system for controlling timing control means (not shown)
An output terminal O1 for transmitting a serial clock SCLK to a control circuit (hereinafter, referred to as a system control circuit) and an output terminal O2 for transmitting the generated first timing data are provided.

The first shift register 310 is realized by a circuit configuration as shown in FIG. 2, for example. In this figure, the first shift register 310 has three delay circuits 40
0 to 420, two AND circuits 430 and 440, and an OR circuit 45
0. The delay circuit 400 has a blanking signal
This is a D-latch circuit which receives HBLK and a dot clock DCLK from terminals I and C, and sends out a delayed output of a blanking signal HBLK from a Q output at the rise of the dot clock DCLK. The delay circuit 410 is a D-latch circuit which receives the Q output of the delay circuit 400 and sends out an inverted output of the blanking signal HBLK further delayed by the next dot clock DCLK from the Q bar output. The delay circuit 420 is a D-latch circuit which receives a timing signal T7 fed back from the eighth shift register 280 from a terminal R, and sends out a delayed output of the timing signal from a Q output at the rise of the dot clock DCLK. AND circuit 430, the logic outputs receiving Q output and the dot clock DCLK delay circuit 410 and the Q output of the delay circuit 400, a serial clock SCLK as shown in FIG. 4 to be supplied to the system controller from the terminal 02 Circuit. The AND circuit 430 is a logic circuit which receives the Q output of the delay circuit 400 and the Q bar output of the delay circuit 410 and outputs a first timing signal T1 as shown in FIG. The first timing signal T1 is output to the AND circuit 100 and the next register 320 via the OR circuit 450. OR circuit
A logic circuit 450 receives the output of the delay circuit 420 or the AND circuit 440 and outputs either one from the terminal O1.

Returning to FIG. 1, the second to eighth shift registers 320 to 380 are respectively provided with the preceding shift registers 310 to 380.
A timing circuit which receives the timing signal supplied from the control circuit 370 and the control signals S0 to S6 supplied from the system control circuit and sends the timing signals T2 to T8 to the AND circuits 102 to 114, respectively. As shown in FIG. 3, these second to eighth shift registers 320 to 370
And two AND circuits 510 and 520, a nut circuit 530,
OR circuit 540. The delay circuit 500 receives the timing data T1 (T7) from the preceding shift register 310 (〜370) via the input terminal D, and receives the next dot clock DC
This is a D latch circuit that delays and outputs the timing signal T2 (2T8) at the rise of LK. AND circuit 510 is
In response to the timing signal T1 (T7) supplied from the previous shift register 310 (前 370), when the control signal S (S6 (〜S0)) from the control circuit is “High” at this time, This is a logic circuit that outputs a timing signal T2 (to T8) at the same timing as the shift register 310 (to 370). Nut circuit
A logic circuit 530 inverts a control signal S (S6 (〜S0)) from the control circuit and outputs the inverted signal to the AND circuit 520. The AND circuit 520 is a logic circuit that receives the Q output of the delay circuit 500 and outputs its timing output as an inverted signal of the control signal S (S6 (〜S0)) supplied via the nut circuit 530.
In this case, a timing signal is output when the control signal S is "Low". The OR circuit 540 is a logic circuit that outputs one of the signals of the AND circuits 510 and 520 as a timing signal T2 (to T8).

The second to eighth shift registers 320 to 320
380 are, for example, control signals S0 to
When both S6 are "Low", each AND circuit 520
4, a delayed output rising at the next dot clock C2 is output as a timing signal T2 from the shift register 320 to which the timing signal T1 of the register 310 is input as shown in FIG. A timing signal that rises at the next dot clock C3 from the shift register 330 that receives the signal T2
T3 is output, and the timing signals T4, T5, T6, T7, and T8, which are delayed in response to the registers 340, 350, 360, 370, and 380 and the timings T3, T4, T5, T6, and T7 in the preceding stage, are sequentially output.

The second to eighth shift registers
320 to 380, the control signal S6 is "High", the control signal S5 is "Low", and the control signal S4 is "H" in the case of 2 bits / pixel shown in FIG.
igh "control signal S3 is" Low ", control signal S2 is" High ", control signal
S1 is set to "Low", and the control signal S0 is set to "High". At the same time as the timing signal T1 of the shift register 310, the timing signal T2 is output from the shift register 320 via the AND circuit 510 and the OR circuit 540. 320
From the shift register 330 receiving the timing signal T2, a delayed timing signal T3 rising at the next dot clock DCLK is output via the delay circuit 500, the AND circuit 520, and the OR circuit 540, and at the same time, the shift register
The timing signal T4 is output from the shift register 340, the timing signal T5 delayed from the shift register 350 and the timing signal T6 having the same timing as the shift register 350 are output from the shift register 360,
From 0,380, the timing signal T of the shift register 350,360
Timing signals T7 and T8 delayed from T5 and T6 are output.

Further, in the case of 4 bits / pixel shown in FIG. 6, the control signals S6 to S4 and S2 to S0 of the second to eighth shift registers 320 to 380 are "High" and the control signal S3 is "High". Low "
And shift register 320-340 to register 310
At the same time as the timing signal T1, the timing signals T2 to T4 are output via the AND circuit 510 and the OR circuit 540, and the timing signal T5 from the shift register 350 is output with a delay from the timing signal T4 of the shift register 340.
Shift registers from the subsequent shift registers 360 to 380
Timing signals T6 to T8 simultaneously with 350 timing signals T5
Is output. Further, when the control signals S6 to S0 are all "High", the second to eighth shift registers 320 to 380 output the timing signals T1 from the respective shift registers 320 to 380 at the same time as the timing signal T1 from the shift register 310. T2 to T8 are output via the AND circuit 510 and the OR circuit 540, respectively.

Returning again to FIG. 1, the data converter 200
It includes eight D latches 600 to 670, a color look-up table 700, and a digital-to-analog converter 800. Each of the D latches 600 to 670 has an AND circuit 10
These latch circuits receive the outputs 0 to 114 and output them in synchronization with the dot clock DCLK. The color look-up table 700 is composed of a RAM (Randam Access Memory) that stores color data in a rewritable manner at any time. In this embodiment, four types of tables TB are used as shown in FIG.
1 to TB4 are written in advance. These tables TB1 to TB4 are selected by a data switching control signal SD supplied from the system control circuit . This switching signal
SD means that pixel data is 1 bit, 2 bits, 4 bits, 8 bits
When switching bits, that is, shift registers 320 to 38
It is supplied simultaneously with the control signals S0 to S7 to 0. For example,
When the pixel data is 1 bit, a signal SD for selecting the table TB1 is supplied. In this case, there are two types of data 0 and 1, where data 0 represents black display and data 1 represents white display. . In the case of data 1, there are seven types of address designations "01" to "80", but all of those addresses are output as white data. If the pixel data is 2 bits, the table TB2 is selected. In this case, there are four types of color data of data 0 to 3, and there are four types of addresses for each color data. If the pixel data is 4 bits, the table TB3 is selected. In this case, there are 16 types of color data 0 to F, and two types of addresses are specified for each color data. In the case of 8 bits, the table TB4 is selected, and 256 kinds of color data are designated by 256 kinds of addresses.

The digital-to-analog converter 800 is a converter for converting the color data designated by the color look-up table 700 into an analog signal and outputting the analog signal.

The operation of the image data conversion apparatus according to the present embodiment having such a configuration will be described below. When displaying image data processed by the image processing apparatus in black and white on a display, the image processing apparatus develops each pixel in a frame memory as 1-bit bitmap data. Data read from the frame memory for each byte (8 bits) is supplied to one input terminal of each of the AND circuits 100 to 114 for each bit. At the same time, the timing control circuit 300 supplies the blanking signal HB
The dot clock DCLK is supplied together with the LK.

The blanking signal BCLK is used during the blanking period.
It becomes "Low" in between and becomes "High" in the display period. this
After the blanking signal BCLK becomes "High",
The register 310 receives the first dot clock DCLK (C1).
And the serial clock SCLK as shown in FIG.system
Control circuitAnd the first timing signal T1 is
Output to the shift circuit 100 and the next-stage shift register 320.
You. Received serial clock SCLKSystem control circuit
Supplies control signals S0-S7 to each shift register 320-380.
Supply to the color lookup table 700
Supply. In this case, since the display is monochrome, the control signal
S0 to S7 are all supplied as "Low". Also switch
Table in color lookup table 700 by signal SD
Is selected.

Since the control signals S0 to S7 are all "Low", the shift registers 320 to 380 output a timing signal T2 which is sequentially delayed by one clock from the timing signal T1 of the first shift register 310 as shown in FIG. ~ T8 is output. When the timing signal T1 of the shift register 310 is supplied to the AND circuit 100, first, the dot data PID7 input to the AND circuit 100 is output to the data converter 200. This data PID is latched by the latch circuit 600,
At the next dot clock DCLK, all the latch circuits 600 to
680 outputs 8-bit data to the lookup table 700 as address data. In this case, the latch circuits 610 to 680 output "0" data, that is, "Don't car".
e "is output.
Receives an 8-bit input represented by dot data PID7 as data, and selects and processes an 8-bit output from the table TB1. In this case, since the look-up table is the table TB1 for monochrome display, an output corresponding to data 0 or data 1 is performed. With this output, the first pixel data is analog-converted by the analog converter 800 and output to the display.

Next, the timing signal T2 from the second shift register 320 is supplied to the AND circuit 110, the data including the dot data PID6 is supplied to the data converter 200, and the color of the pixel is looked up. The data is specified in the table 700, and the data is D / A converted and output. Similarly, timing signals are sequentially sent from shift registers 330 to 380.
T3 to T8 are supplied to AND circuits 130 to 170, and the dot data PID5 to PID0 input thereto are supplied to the data converter 200, and are sequentially color-designated and analog-converted and output.

The timing signal T8 output from the shift register 380 is fed back to the shift register 310, so that the next timing signal is transmitted to the shift register 31.
In the same manner as described above, the 8-bit data is sequentially converted by the data converter 200 and output. This operation is repeated every 8 bits, and data of one horizontal scan is displayed on the display.

Next, when a blanking signal is supplied during the blanking period, the timing signal T1 is generated again by the shift register 310, and the shift registers 320 to 38 are generated.
The data is shifted to 0 and the image data of one horizontal scanning line is output. By repeating this, one screen of a black and white image is displayed on the display.

Next, a case where an image developed into a bit map is represented by 2 bits for each pixel will be described. First, the serial clock SC is output from the first shift register 310.
When LK is supplied to the system controller, the system control times
The control signals S0 to S6 are supplied to the shift registers 320 to 380 from the path . In this case, the control signals S0, S2, S4, S6 become "High" and the control signals S1, S3, S5 become "Low" and are supplied.
As a result, as shown in FIG.
And the timing signals T1 and T2
Respectively, and then shift registers 330, 340
And the timing signals T3 and T4 from the AND circuits 120 and 130 at the same time.
Then, shift registers 350 and 360, shift registers 360 and 370, and timing signals T5 to T8 are sequentially output. Look-up table 700 is system-based.
Since the control signal SD is sent from the control circuit to select the table TB2 for displaying four colors, one of the four colors is designated by the 8-bit data input through the latch circuits 600 to 670, and the DA signal is output. Output to converter 800. As a result, the 8-bit data read from the frame memory is output to the display as color data for four pixels.

Similarly, in the case of 4 bits / pixel, only the control signal S3 becomes "Low", so that the shift register 350
, The timing data is shifted, the color is designated by the look-up table 700 as data for every two pixels, DA-converted and displayed. In the case of 8 bits, control signals S0 to
All the signals S7 become "High", and the timing signals T1 to T8 are simultaneously supplied to the AND circuits 100 to 114, and are simultaneously supplied to the look-up table 700 for 8 bits and displayed on the display as 256-color data.

As described above, the image data converter according to the present embodiment reads image data for each bit into the AND circuits 100 to 114, and sets one pixel to any one of 1, 2, 4, and 8 bits. The timing data is supplied from the timing control circuit 300 to the respective AND circuits 100 to 114, and the data converter 20 is provided for each pixel.
Output to 0 for conversion. In this case, the timing control circuit 300 can sequentially read the higher-order bits from the lower-order bits for each pixel by shifting the timing signals T1 (to T7) from the previous-stage shift registers 310 to 380. Further, the serial clock SCLK is transmitted from the shift register 310 to the control circuit every blanking, and the control signals S0 to S7 to the shift registers 320 to 380 and the switching signal SD to the lookup table 700 are output. The number of bits can be changed for each line, and an image can be displayed by changing its color expression.

Although the above embodiment has been described with reference to the case where data is read out from the frame memory every 8 bits, the data is read out every 16 bits or 32 bits or in correspondence with the transfer function of the processing device and the conversion function of the lookup table. Data may be read out for each other specific bit, and the data may be converted for each pixel.

[0034]

As described above, according to the image data conversion apparatus of the present invention, the image data input to the input means for each bit is supplied with the timing data for each pixel and supplied to the data conversion means. Is done. Therefore, by switching the timing data according to the number of bits indicated for each pixel, it is possible to handle any number of bits. As a result, there is an excellent effect that it is not necessary to provide a converter and an expander according to the number of bits, and it is possible to configure the device with a small and inexpensive circuit without requiring a multiplexer.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an image data conversion device according to the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of a first shift register 310 in the embodiment.

FIG. 3 shows second to eighth shift registers in the embodiment.
FIG. 3 is a circuit diagram showing an internal configuration of 320 (to 380).

FIG. 4 is a time chart showing a timing signal output when one pixel is represented by one bit in the embodiment.

FIG. 5 is a time chart showing a timing signal output when the same pixel is represented by 2 bits.

FIG. 6 is a timing chart showing timing signals output when the same pixel is represented by 4 bits.

FIG. 7 is a diagram showing an example of a data table of a lookup table 700 in the embodiment.

[Explanation of symbols]

 100 to 114 AND circuit (input means) 200 Data converter 300 Timing control circuit 310 to 380 Shift register 400 to 420,500 Delay circuit 430,440,510,520 AND circuit 450,540 OR circuit 530 Nut circuit 610 to 670 Latch circuit 700 Color look-up table 800 Digital Analog converter DCLK Dot clock HBLK Blanking signal PID0 to PID7 Dot data SCLK Serial clock T1 to T7 Timing signal TB1 to TB4 Color table

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ identification symbol FI H04N 7/01 G06F 15/68 310 (58) Investigated field (Int.Cl. ⁷ , DB name) G09G 5/02 G09G 5 / 06 G09G 5/36 G06F 3/153 336 G06T 5/00 H04N 7/01

Claims (4)

(57) [Claims] 1. Each pixelExpression of gradation or color tone for
FirstPredetermined number of bitsA bit ofRepresented byYouImage data
The bitmap is developed and stored in the image memory, and the image
From memorySecond placeConstant number of bitsIn units ofparallel
Image data read out to the display deviceThe maximum floor that is displayed
Output containing tones or tonesImage data to be converted to a signal and output
Data conversion device,conversionThe equipment isSaid Image data read in parallelButEach bee
Enter for each unitIsInput means, and the input meansThe image data input toFor each pixelSaid entry
From power meansOutputGenerate timing signalsTaimi
Control means; and the input meansOutput fromFor each pixelimagedataBefore
Convert to output signalData conversion means, wherein the timing control means comprises:The first predetermined number of bits
Shift registers connected in cascade corresponding to each bit of
And a first register of the plurality of shift registers.
Of the first predetermined number of bits generated by the shift register
The timing signal of the most significant bit is sequentially shifted to the lower bits
Side shift registerShift, The plurality of shift registers
The timing signal output from each of the
Giving power means The first shift register includes a blanking line in the display device.
Blanking signal indicating transition from last period to image display period
Dot clock indicating signal and pixel display timing
Is the timing signal from the least significant bit shift register
Generates the timing signal of the most significant bit based on You
An image data conversion apparatus characterized in that: 2. The image data conversion device according to claim 1, wherein said input means comprises two-input AND circuits, and inputs each bit of image data to one input terminal of said AND circuit. An image data conversion apparatus for outputting bit data by inputting a timing signal from the timing control means to the other input terminal. 3. The image data conversion device according to claim 1, wherein said data conversion means latches pixel data of a predetermined number of bits from said input means and outputs the data with a specific number of bits. A look-up table for inputting data supplied with a specific number of bits as a code from the latch means and outputting predetermined color data or gradation data; and converting the data output from the look-up table into analog data. An image data conversion device, comprising: a digital-to-analog conversion unit for outputting. 4. The image data conversion device according to claim 3 , wherein the look-up table has a plurality of tables according to the number of bits for each pixel, and the table is selected according to the number of bits for each pixel. An image data conversion device characterized by being performed.