JP2001169311A - Image comparator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image comparator by which an evaluation value and an evaluated reproduced image can be viewed without any movement of a viewpoint and the image and its evaluation value can intuitionally be recognized. SOLUTION: An evaluation value arithmetic circuit 4 receives digital data of an original image via a frame delay memory 3 and receives digital data of a reproduced image as they are. The evaluation value arithmetic circuit 4 compares the digital data of the two images and provides an output of resulting evaluation data to a CPU 5, which converts the evaluation data into information data for screen display. The digital data of the reproduced image is given to an evaluation value synthesis circuit 7 via an arithmetic delay memory 6, and the evaluation value synthesis circuit 7 synthesizes the information data from the CPU 5 with the digital data of the reproduced image. Thus, a delay caused in the digital processing circuit system and a delay caused in the arithmetic circuit are corrected and the evaluated image frame and its evaluation value can be displayed on a screen of one display device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital signal processing by comparing a reproduced image via an image codec device and a digital network (hereinafter collectively referred to as a digital processing circuit system) with an input original image. The present invention relates to an image comparison device that measures and evaluates image deterioration and noise generation in a system.

[0002]

2. Description of the Related Art An image comparison apparatus is connected to a personal computer (hereinafter referred to as a PC) for controlling and evaluating a digital processing circuit system. The image comparison device normally compares the original image input in image frame units with the reproduced image in order to evaluate the deterioration of the reproduced image and the noise included therein in real time. Then, data of the comparison result (hereinafter referred to as evaluation value data) is output for each image frame. By the way, in the image comparison device,
About 30 evaluation value data are generated in about one second. The evaluation value data is sent to a PC, processed by the PC, and displayed on a display attached to the PC. At this time, for example, graphs of characters (numeric characters) and evaluation value data corresponding to the evaluation value data appear on the display, and are updated every predetermined time.

In an image evaluation operation using a conventional image comparison device, first, a display for displaying an original image, a display for displaying a reproduced image passed through a digital processing circuit system, and an evaluation value obtained from the image comparison device. PC that displays
Prepare three displays. Then, the observer observes each display and observes the state and evaluation value of the projected image. At this time, the observer compares the reproduced image with the evaluation value, and alternately checks how much the evaluation value is in which scene. Then, by synchronizing the image with the evaluation value in the head, the degradation of the image and the state of the noise are recognized.

[0004]

However, in this work procedure, it is necessary to alternately look at the display of the reproduced image and the display of the PC, and the trouble of moving the viewpoint is involved. This movement of the viewpoint and the fact that the image and the evaluation value must be synchronized and recognized in the head have placed a heavy burden on the observer, especially when the evaluation work takes a long time. Therefore, the present invention displays the evaluated reproduced image and the evaluation result on the same display. This makes it possible to view the playback image evaluated as the evaluation value without moving the viewpoint,
It is an object of the present invention to provide an image comparison device in which an image and its evaluation value can be intuitively recognized.

[0005]

According to the present invention, there is provided an image comparison apparatus, comprising: a delay memory for delaying the generation timing of first image data for each frame;
An evaluation value calculating circuit for comparing the second image data with the first image data from the delay memory and generating evaluation value data; and information data for displaying a character or a figure corresponding to the evaluation value data on a screen. , An arithmetic delay memory that causes a time delay in the generation timing of the second image data, and the second image data from the arithmetic delay memory and information data from the arithmetic processing device are combined. And an evaluation value synthesizing circuit.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first input terminal to which original image data is input is connected to one input terminal of an evaluation value calculation circuit via an A / D converter and a frame delay memory. On the other hand, the second input terminal to which the reproduced image data is input is connected to the other input terminal of the evaluation value calculation circuit via the A / D converter. The output side of the evaluation value calculation circuit is connected to a calculation processing device. The second input terminal to which the reproduced image is input is A /
It is connected to one input terminal of the evaluation value synthesis circuit via a D converter and an operation delay memory. The other input terminal of the evaluation value synthesis circuit is connected to the arithmetic processing unit, and the output terminal of the evaluation value synthesis circuit is connected to the output terminal via a D / A converter. Thus, the delay occurring in the digital processing circuit system and the delay occurring in the arithmetic circuit are corrected, and the evaluated image frame and its evaluation value can be displayed together.

[0007]

FIG. 1 is a block diagram showing the structure of an image comparison apparatus according to the present invention. In the image comparison device of FIG. 1, the first input terminal IN1 is connected to one input terminal of the evaluation value calculation circuit 4 via the first A / D converter 1 and the frame delay memory 3. The second input terminal IN2 is connected to the second A / D converter 2
To the other input terminal of the evaluation value calculation circuit 4 via
The output side of the evaluation value calculation circuit 4 is a calculation processing device (hereinafter referred to as CP).
Connect to 5). Also, the second A / D converter 2
Is output via an operation delay memory 6 to an evaluation value synthesizing circuit 7.
To one of the input terminals. The other input terminal of the evaluation value synthesizing circuit 7 is connected to the CPU 5 and the output terminal is connected to the second output terminal OUT2 via the D / A converter 8. The output side of the CPU 5 is connected to the first output terminal OUT1.

In the image comparison apparatus shown in FIG. 1, an original image is input via a first input terminal IN1, and a second input terminal I
A reproduced image is input from the digital processing circuit system via N2. The original image and the reproduced image are A / D converters 1 and 2, respectively.
Is converted to digital data. Then, the digital data of the reproduced image (hereinafter, reproduced image data) is directly input to the evaluation value calculation circuit 4, and the digital data of the original image (hereinafter, referred to as reproduced image data).
The original image data) is input via the frame delay memory 3. By the way, since a codec device provided in a circuit system for handling digital signals compresses and expands data in space and on a time axis, image data is buffered over several frames. Therefore, when the original image is input to the codec device and compressed and decompressed, a delay of several frames occurs between the reproduction image of the codec device and the generation timing of the data of the original image.

However, the original image data and the reproduced image data must be input to the evaluation value calculation circuit 4 in a state where the generation timing of each data is synchronized. Therefore, the frame delay memory 3 is added in order to correct the difference between the timings at which the reproduced image data and the original image data are generated. Then, the evaluation value calculation circuit 4 generates evaluation value data according to the comparison result of the two input image data. The CPU 5 converts the evaluation value data generated by the evaluation value calculation circuit 4 into a data format necessary for displaying on the screen, and transmits the data to the PC via the first output terminal OUT1. Also C
The PU 5 processes the evaluation value data into character information or graphic information, and sends out the information data obtained thereby to the evaluation value combining circuit 7.

In the evaluation value synthesizing circuit 7, the operation delay memory 6
Then, the reproduced image data received via the CPU 5 and the information data sent from the CPU 5 are combined to generate combined image data. The operation delay memory 6 corrects a deviation between the generation timings of the information data and the reproduced image data caused by the data processing in the evaluation value operation circuit 4 and the CPU 5. The synthesized image data generated by the evaluation value synthesizing circuit 7 is converted into analog data by the D / A converter 8, and is supplied to the display via the second output terminal OUT2. As a result, the image and the evaluation value are displayed on the same display screen, the image and the evaluation value can be viewed without moving the viewpoint, and the image and the evaluation value can be intuitively recognized.

FIG. 2 is a block diagram showing a specific configuration of the evaluation value synthesizing circuit 7. As shown in FIG. The evaluation value synthesis circuit of FIG. 2 connects the input terminal of the signal separation circuit 11 to the operation delay memory 6. One output terminal of the signal separation circuit 11 is connected to the address counter 12, and the other output terminal is connected to a first input terminal of the selector 16. The output terminal 12 of the address counter is connected to one input terminal of the bit map memory 13, and the other input terminal of the bit map memory is connected to the CPU 5.
Connect to The output terminal of the bitmap memory 13 is P /
An input terminal of the S (parallel / serial) converter 14 is connected, and an output terminal of the P / S converter 14 is connected to a selection signal input terminal of the selector 16. Then, the second selector 16
The luminance register 15 is connected to the input terminal of
The output terminal 6 is connected to the D / A converter 8.

In the evaluation value synthesizing circuit 7 having such a configuration, data processing is performed in the following flow.
The reproduced image data input via the operation delay memory 6 is first input to the signal separation circuit 11. The signal separation circuit 11 inputs the reproduced image data itself to the selector 16 and simultaneously outputs synchronization signals (a clock signal per pixel, a vertical synchronization signal,
(A horizontal synchronizing signal or the like) is input to the address counter 12. The address counter 12 generates address data corresponding to the display position on the display from the synchronization signals.
The bitmap memory 13 stores the information data provided from the CPU 5 in the memory at the address specified by the address counter 12.

Here, the bit map memory 13 is a memory allocated as one bit per pixel. For example, when the byte (8-bit) access memory system is adopted for the bit map memory 13, the first lower bit is the first pixel of the image and the second bit is the second pixel. Thus, the ninth pixel becomes the first bit of the second byte. P / S
The (parallel / serial) converter 14 reads out the data for eight pixels stored in the bitmap memory 13 as needed, and converts it into serial data of one pixel. The serial data of one pixel is input to the selector 6 as a selection signal. At this time, the serial data is input to the selector 6 in synchronization with the digital data of the reproduced image.

The selector 6 selectively outputs one of the luminance data of the luminance register and the data of the reproduced image in accordance with the selection signal from the P / S converter 14. For example, when character font data is sent from the CPU 5 to the bitmap memory 13, the memory at the address corresponding to the position where the dot of the character font should be displayed in the bitmap memory 13 is 1. The P / S converter 14 generates a selection signal according to the recorded contents of the memory and inputs the selection signal to the selector 16. When a selection signal indicating that the content of the memory is 1 is supplied, the selector 16
Outputs data from the luminance register 15. Conversely, in the case of a selection signal indicating that the memory is 0, the selector 16 outputs reproduced image data. As a result, on the display screen, the character font and the reproduced image are displayed in a combined state.

The brightness register 15 outputs data for setting the display brightness of characters and graphics according to the evaluation value.
The luminance register 15 can be accessed from the CPU 5, and the luminance level can be adjusted by changing the numerical value of the data. When an image and an evaluation value are simultaneously displayed on the display, a part of the image may be hidden by the evaluation value. Generally, the evaluation value is displayed at the corner of the image, but it is desirable that the position and size of the display of the evaluation value can be easily changed. It is also desirable that the method of expressing the evaluation value (character display, graphic display) be diversified. Therefore, the recorded contents of each memory in the bit map memory 13 can be freely rewritten by the CPU 5 so that characters and figures can be freely expressed in pixel units.

FIGS. 3 and 4 show examples of display states appearing on the screen of the display when the image comparison apparatus having the structure shown in FIGS. 1 and 2 is used. Here, FIG. 3 shows a display state when the evaluation value data is expressed by a character and a bar graph, and FIG. 4 shows a display state when the evaluation value data is expressed by a line graph. The evaluation value synthesis circuit 7 in FIG. 2 has a configuration assuming a case where the display of the evaluation value is displayed in a single color. Here, a type that allocates two or more bits per pixel to the bitmap memory 13 is used, and several types of luminance registers are prepared according to the number of bits per pixel. In this way, a background color can be added around the characters or figures indicating the evaluation values, so that the display can be easily viewed as shown in FIG. In addition, it is also possible to change the display color of the character and figure displayed simultaneously by the same means.

[0017]

According to the image comparison apparatus of the present invention, the digital data of the original image is input to the evaluation value calculation circuit via the frame delay memory, and the digital data of the reproduced image is input to the evaluation value calculation circuit as it is. The evaluation value data generated by the evaluation value calculation circuit is input to an arithmetic processing device and converted into information data for screen display. Digital data of a reproduced image is input to an evaluation value synthesizing circuit via an operation delay memory, and the evaluation value synthesizing circuit synthesizes information data from the arithmetic processing unit and reproduced image data. It features a configuration. According to such a configuration, the image and the evaluation value are displayed on the same display screen. As a result, an image and an evaluation value can be viewed without moving the viewpoint, and an image comparison device capable of intuitively recognizing an image and its evaluation value can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image comparison device according to the present invention.

FIG. 2 is a block diagram of a specific evaluation value synthesis circuit.

FIG. 3 is a display state (1) when the image comparison device of the present invention is used.

FIG. 4 is a display state (2) when the image comparison device of the present invention is used.

FIG. 5 shows a display state when a plurality of luminance registers are provided in the image comparison device of the present invention.

[Explanation of symbols]

3: Frame delay memory 4: Evaluation value calculation circuit
5: arithmetic processing unit 6: arithmetic delay memory 7: evaluation value synthesis circuit

Claims (3)

[Claims] 1. An evaluation for comparing a delay memory for delaying the generation timing of first image data in frame units with a second image data and the first image data from the delay memory to generate evaluation value data. A value calculation circuit, a calculation processing device for generating information data for displaying a character or a graphic corresponding to the evaluation value data on a screen, and causing a time delay in the generation timing of the second image data An image comparison device comprising: an operation delay memory; and an evaluation value synthesizing circuit that synthesizes second image data from the operation delay memory and information data from the operation processing device. 2. The operation delay memory according to claim 1, wherein a timing of generating a predetermined frame of the second image data is synchronized with a timing of generating the information data for the predetermined frame. The image comparison device described in 1. 3. The evaluation value synthesizing circuit includes: a signal separating circuit that detects synchronization signals of the second image data; an address counter that generates address data from the synchronization signals; A bitmap memory for storing information data from the arithmetic processing unit in a memory at the specified address; a parallel-serial converter for converting data stored in a plurality of memories of the bitmap memory into one serial data; A brightness register for outputting brightness setting data, the second image data and the display brightness setting data being input, and any one of the second image data and the display brightness setting data according to the serial data. The image comparison device according to claim 1, further comprising a selector that outputs one of the signals.