CN113496665A - Display device - Google Patents
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- CN113496665A CN113496665A CN202010199426.XA CN202010199426A CN113496665A CN 113496665 A CN113496665 A CN 113496665A CN 202010199426 A CN202010199426 A CN 202010199426A CN 113496665 A CN113496665 A CN 113496665A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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Abstract
A display device receives image data generated by an image generator and comprises a first memory, a second memory, a selection circuit, a time schedule controller and a display panel. The first memory is used for storing first display data. The second memory is used for storing second display data. The first and second memories are independently configured. The selection circuit selects one of the first and second display data as a specific data according to a selection signal. The time schedule controller generates a selection signal according to the voltage level of a specific pin and provides specific data to the image generator. The image generator generates image data based on the specific data. The display panel presents a picture according to the image data.
Description
Technical Field
The present invention relates to a display apparatus, and more particularly, to a display apparatus having different operation modes.
Background
At present, electronic pen competition is popular, in order to improve the smoothness of the picture, different synchronization technologies are proposed by display adapter manufacturers, and the panel manufacturers also improve the response time of the display and the refresh rate (frame rate) of the display data. However, each display is compatible with only a single particular synchronization technique. When a user changes a new display adapter, the display will most likely not be able to support the new display adapter.
Disclosure of Invention
It is an object of the present invention to provide a display device to solve at least one of the above problems.
The invention provides a display device which receives image data generated by an image generator and comprises a first memory, a second memory, a selection circuit, a time schedule controller and a display panel. The first memory is used for storing first display data. The second memory is used for storing second display data. The first and second memories are independently configured. The selection circuit selects one of the first and second display data as a specific data according to a selection signal. The time schedule controller generates a selection signal according to the voltage level of a specific pin and provides specific data to the image generator. The image generator generates image data based on the specific data. The display panel presents a picture according to the image data.
The invention has the advantages that the invention generates the selection signal according to the voltage level of a specific pin through the time sequence controller and provides specific data to the image generator, the image generator generates image data according to the specific data, and the display panel presents a picture according to the image data.
Drawings
Fig. 1 is a schematic view of an electronic device according to the present invention.
Fig. 2 is another schematic diagram of the display device of the present invention.
Fig. 3A is a schematic view of a display panel according to the present invention.
Fig. 3B shows a light emitting sequence of the hollow areas according to the present invention.
Fig. 4 is a schematic diagram of a timing controller according to an embodiment of the invention.
The reference numbers are as follows:
100 electronic device
110 host computer
111 control circuit
112 image generator
113,121 connection interface
114 power supply generator
115 transmission circuit
116 hardware
120,200 display device
122,400 timing controller
123,300 display panel
124,220 selection circuit
125,230 storage circuit
126 to 128,231 to 233,450 memory
129 data buffer circuit
210 conversion circuit
241 to 243, gate driver
251-253 data driver
260 display area
310 base plate
320 backlight board
330 back shell
321 to 324 light emitting region
331-334 hollow area
SSL1,SSL2Selection signal
EDIDA～EDIDCDisplay data
EDIDSSpecific data
Vsync vertical synchronization signal
Hsync horizontal synchronization signal
PW operating voltage
DIMImage data
SSTSetting signal
V1,V2Voltage of
GMA～GMCGamma curve
GMSSpecific curve
ODA～ODCOverdrive information
ODSSpecific information
PX pixel
SSScanning signals
SDData signal
T1-T5 period
410 receiver
420: decoder
430 processor
440 output interface
460 backlight controller
DIMDDecoding data
DPRDefault data
SENEnable signal
470 timer
CV count value
Detailed Description
In order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. The present description provides various examples to illustrate the technical features of various embodiments of the present invention. The configuration of each component in the embodiments is for illustration and not for limitation. In addition, the reference numerals in the embodiments are partially repeated, and for the sake of simplifying the description, the relevance between different embodiments is not intended.
Fig. 1 is a schematic view of an electronic device according to the present invention. The present invention is not limited to the type of electronic device 100. In one possible embodiment, the electronic device 100 is a notebook computer (NB). As shown, the electronic apparatus 100 includes a host 110 and a display device 120. The host 110 is used for controlling the display of the display device 120. In the present embodiment, the host 110 includes a control circuit 111 and an image generator 112.
The control circuit 111 includes a connection interface 113, a power generator 114, and a transmission circuit 115. The connection interface 113 is coupled to the display device 120. In the present embodiment, the connection interface 113 outputs an operation voltage PW, image data DIM and a setting signal SSTThe display device 120, and receives the specific data EDID provided by the display device 120S。
The power generator 114 is used for generating an operating voltage PW. In the embodiment, the power generator 114 generates a single operating voltage PW, but the invention is not limited thereto. In another possible embodiment, the power generator 114 generates a plurality of operating voltages. In this example, the connection interface 113 has a plurality of pins for transmitting different operating voltages. In other embodiments, the power generator 114 further provides power to other components of the host 110, such as the transmission circuit 115 or the image generator 112.
The transmission circuit 115 is coupled between the connection interface 113 and the image generator 112 for transmitting the image data DIM and the specific data EDIDSAnd a setting signal SST. In one embodiment, the transmitting circuit 115 includes a transmitter (transmitter) for transmitting the setting signal S generated by the image generator 112STAnd image data DIM to the connection interface 113. In other embodiments, when the image generator 112 is integrated into the control circuit 111, the transmission circuit 115 can be omitted. In this case, the image generator 112 directly provides the setting signal SSTAnd image data DIM to the connection interface 113 and receiving specific data EDID from the connection interface 113S。
In the present embodiment, the image generator 112 generates the setting signal SSTTo ask the display device 120 for specific data EDIDSThen according to the specific data EDIDSAnd generates image data DIM. The present invention does not limit the kind of the image generator 112. In one embodiment, the image generator 112 is a display adapter having a Graphics Processing Unit (GPU) or a scaling circuit (scalar).
The invention does not limit how the image generator 112 generates the setting signal SST. In one possible embodiment, when a hardware (hardware)116 is operated, the image generator 112 generates the setting signal S according to the state of the hardware 116ST. For example, when the hardware (e.g., the dip switch) 116 is switched to a first state, the image generator 112 commands the setting signal SSTIs at a first level (e.g., a high level or a low level) for instructing the display apparatus 120 to enter a first operation mode. When the hardware 116 is switched to a second state,the image generator 112 commands the setting signal SSTAt a second level (e.g., a low level or a high level) for instructing the display apparatus 120 to enter a second operation mode.
In other embodiments, the image generator 112 may generate more setting signals when the number of the hardware 116 is larger or the hardware 116 is switched to more states. For example, when the hardware 116 is in the first state, the image generator 112 generates a first setting signal and a second setting signal, and sets the first and second setting signals to a low level. When the hardware 116 is in the second state, the image generator 112 sets the first setting signal to low level and sets the second setting signal to high level. When the hardware 116 is in the third state, the image generator 112 sets the first setting signal to high level and sets the second setting signal to low level. When the hardware 116 is in the fourth state, the image generator 112 sets the first and second setting signals to high level. In this example, the connection interface 113 transmits the first and second setting signals to the display device 120 by using different pins.
In some embodiments, the image generator 112 generates the setting signal S according to an operation state of software (software)ST. For example, when the user starts a first specific software (e.g. video game), the image generator 112 commands the setting signal SSTIs at a first level. When the user turns on a second specific software (such as Microsoft word), the image generator 112 commands the setting signal SSTAt a second level.
In other embodiments, the image generator 112 generates a plurality of setting signals according to the operating state of the software. For example, when the user turns on the first specific software, the graphic generator 112 sets the first and second setting signals to low level. When the user turns on the second specific software, the image generator 112 sets the first setting signal to a low level and sets the second setting signal to a high level. When the user turns on the third specific software, the image generator 112 sets the first setting signal to a high level and sets the second setting signal to a low level. When the user turns on the fourth specific software, the image generator 112 sets the first and second setting signals to high level.
In some embodiments, when a mode switching function of a BIOS (not shown) of the host 110 is turned on, the host 110 dynamically adjusts the operating mode of the display device 120 according to the state of the hardware 116 and/or a software. For example, when a mode switching function of the BIOS of the host 110 is turned on, if the user turns on the first specific software, the image generator 112 commands the display device 120 to enter the first operation mode. In other embodiments, when a mode switching function of the BIOS of the host 110 is turned on, the image generator 112 commands the display device 120 to enter the first operating mode if the hardware 116 is switched to a first state.
The display device 120 is based on the setting signal SSTEnter different operation modes. The display device 120 provides different specific data EDID in different operation modesSTo the image generator 112. The image generator 112 further generates EDID according to different specific dataSAnd generates corresponding image data DIM. In this embodiment, the display device 120 includes a connection interface 121, a Timing Controller (TCON) 122, a display panel 123, a selection circuit 124, and a storage circuit 125.
The connection interface 121 is used for receiving an operating voltage PW, image data DIM and a setting signal S from the host 110STAnd providing specific data EDIDSTo the host 110. In one embodiment, the connection interface 121 has a specific pin for receiving the setting signal SST. In other embodiments, when the image generator 112 generates more setting signals, the connection interface 121 receives a plurality of setting signals by using different pins. Similarly, when the host 110 provides more operating voltages, the connection interface 121 also receives a plurality of operating voltages through different pins. Since the characteristics of the connection interface 121 are similar to those of the connection interface 113, detailed description thereof is omitted.
The timing controller 122 receives the operating voltage PW and outputs a setting signal SSTGenerating a selection signal SSL1. In one embodiment, when the first specific pin of the connection interface 121 receives the setting signal SSTTime, time sequence controlThe generator 122 generates the selection signal S according to the voltage level of the first specific pinSL1. In other embodiments, when the first specific pin and the second specific pin of the connection interface 121 receive a first setting signal and a second setting signal, the timing controller 122 generates the selection signal S according to the voltage levels of the first specific pin and the second specific pinSL1。
The selection circuit 124 selects the signal S according to the selection signalSL1Selecting display data EDIDA～EDIDCOne of which is as the specific data EDIDS. For example, when setting the signal SSTAt a first level, the timing controller 122 enters a first operating mode. In the first operation mode, the timing controller 122 may select the signal SSL1The selection circuit 124 is required to display the data EDIDAEDID as specific dataS. When setting the signal SSTAt a second level, the timing controller 122 enters a second operation mode. In the second operation mode, the timing controller 122 requests the selection circuit 124 to display the display data EDIDBEDID as specific dataS. When setting the signal SSTAt a third level, the timing controller 122 enters a third operating mode. In the third operation mode, the timing controller 122 requests the selection circuit 124 to display the display data EDIDCEDID as specific dataS。
In the present embodiment, the timing controller 122 receives the specific data EDIDSAnd outputs the specific data EDID through the connection interface 121S. In other embodiments, the selection circuit 124 directly outputs the specific data EDIDSTo the connection interface 121. The present invention is not limited to the architecture of the selection circuit 124. In one embodiment, the selection circuit 124 is a switch circuit. In another possible embodiment, the selection circuit 124 is a multiplexer.
The storage circuit 125 is used for storing display data EDIDA～EDIDC. In the present embodiment, the storage circuit 125 has memories 126-128. The memories 126 to 128 are independently provided. The memory 126 is used for storing display data EDIDA. The memory 127 is used for storing display data EDIDB. Memory device128 for storing display data EDIDC. The invention does not limit the types of the memories 126-128. In one possible embodiment, the memories 126-128 are Electrically Erasable-Programmable Read-Only-Memory (EEPROM).
In some embodiments, the memory 126 stores display data EDIDAThe address of the memory 127 is the same as the address of the display data EDID stored in the memory 127BAnd the memory 128 stores the display data EDIDCThe address of (2). For example, the memory 126 may display data EDIDAStore the addresses in the corresponding memory blocks of addresses 0037-004X. In this example, the memory 127 will display the data EDIDBStore the data in the corresponding memory block of addresses 0037-004X, and the memory 128 will also display the EDID dataCStore the addresses in the corresponding memory blocks of addresses 0037-004X.
In other embodiments, the timing controller 122 processes and converts the operating voltage PW and provides the converted voltage to other components, such as at least one of the display panel 123, the selection circuit 124 and the storage circuit 125. In the present embodiment, the timing controller 122 further decodes the image data DIM to generate a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync.
The display panel 123 operates according to the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the image data DIM. In the embodiment, the display panel 123 receives the image data DIM through the timing controller 122, but the invention is not limited thereto. In other embodiments, the display panel 123 may receive the image data DIM directly from the connection interface 121. The present invention does not limit the kind of the display panel 123. In one embodiment, the Display panel 123 is an Active Matrix Organic Light Emitting Diode (AMOLED) panel or an Active Matrix Liquid Crystal Display (AMLCD) panel.
In the present embodiment, the display data EDIDA～EDIDCDifferent vertical synchronization techniques are supported. For example, the display data EDIDASupport the vertical synchronization technique proposed by Intel corporation, such as an intelligent vertical synchronization (A)daptive Sync), display data EDIDBSupporting the vertical synchronization technique proposed by NVIDIA corporation, e.g. G-sync, display data EDIDCSupport AMD companies' vertical synchronization technologies, such as Free-sync.
When the user turns on the first specific software, the image generator 112 passes the setting signal SSTThe display device 120 is required to enter a first mode of operation. Accordingly, the timing controller 122 commands the selection circuit 114 to display the data EDIDAEDID as specific dataS. The image generator 112 EDID according to the specific dataSAnd generates image data DIM. In this example, assume that the frame rate (FPS) of the image generator 112 is a first predetermined value, such as 120Hz, indicating that the image generator 112 provides 120 frames per second. At this time, the timing controller 122 generates a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync according to the image data DIM. In one possible embodiment, the frequency of the vertical synchronization signal Vsync is also equal to 120Hz, which means that the display panel 123 refreshes 120 pictures per second. At this time, since the update rate of the display panel 123 is equivalent to the frame rate of the image generator 112, the frame presented by the display panel 123 is smoother and does not cause frame tearing (screen tearing).
However, when the user turns on the second specific software (e.g., the user may simply browse web pages or perform word processing), the image generator 112 requests the display device 120 to enter a second mode of operation. In the second operation mode, the timing controller 122 commands the selection circuit 114 to display the data EDIDBEDID as specific dataS. The image generator 112 EDID according to the specific dataSAnd generates image data DIM. At this time, the frame rate of the image generator 112 may be a second predetermined value, such as 60Hz, which means that the image generator 112 provides 60 frames per second. Accordingly, the timing controller 122 adjusts a blank (blanking) interval of the vertical sync signal Vsync according to the image data DIM. In one possible embodiment, the frequency of the vertical synchronization signal Vsync is also equal to 60 Hz. Since the refresh rate of the display panel 123 is equivalent to the frame rate of the image generator 112, the display panel 123 does not display a pause (lag) in the displayed image.
In other embodiments of the present invention, the substrate may be,when the user does not start any specific software (e.g., the host 110 is in an idle state), the image generator 112 requests the display device 120 to enter a third operation mode. In this mode, the timing controller 122 commands the selection circuit 114 to display the data EDIDCEDID as specific dataS. The image generator 112 EDID according to the specific dataSAnd generates image data DIM. At this time, the frame rate of the image generator 112 may be a third default value, such as 48 Hz. Therefore, the timing controller 122 adjusts the refresh rate of the display panel 123 according to the frame rate of the image generator 112 to reduce the power consumption of the display device 120.
In the present embodiment, the display device 120 supports different vertical synchronization technologies, so that it can be used with any brand image generator 112. For example, when the graphic generator 112 is a display adapter available from Intel corporation, the user may switch the hardware 116 to a first state. Thus, the image generator 112 passes the setting signal SSTCommanding the display device 120 to enter a first operating state for outputting the display data EDIDA. When graphics creator 112 is a display adapter available from NVIDIA corporation, the user may switch hardware 116 to a second state. At this time, the image generator 112 passes the setting signal SSTInstructing the display device 120 to enter a second operation state for outputting the display data EDIDB. When the display device 120 is a display produced by AMD, the user may switch the hardware 116 to a third state. Thus, the image generator 112 uses the setting signal SSTInstructing the display device 120 to output display data EDIDC。
In one possible embodiment, the display data EDIDA～EDIDCExtended Display capability Identification Data (EDID) indicating the resolution, pixel frequency (pixel clock), manufacturer name, and serial number of the Display panel 123. In this case, each display data may have a multiple pixel frequency, and the image generator 112 dynamically adjusts the frame rate according to the multiple pixel frequencies. For example, when the image generator 112 needs to output a large number of pictures, the image generator 112 has a high utilization frequencyAt a pixel frequency (e.g., 180Hz), image data DIM is generated. When the image generator 112 does not need to output a large number of pictures, the image generator 112 generates the image data DIM using a pixel frequency having a low frequency (e.g., 160 Hz). In this example, although the display device 120 is maintained in the same operation mode, the display device 120 provides different update rates according to the image data DIM of different frequencies.
In other embodiments, the display device 120 further includes a data buffer circuit (data buffer)129 for storing a default data. When the image generator 112 switches the operation mode of the display device 120 (i.e., sets the signal S)STWhen the level of (d) is changed), the display panel 123 may display a black frame when the timing controller 122 has not received the image data DIM. Therefore, when the signal S is setSTWhen the level of the display panel 123 is changed, the timing controller 122 reads the default data in the data buffer circuit 129 to command the display panel 123 to display a predetermined frame. In one embodiment, the data buffer circuit 129 stores the last complete frame. Therefore, when the signal S is setSTWhen the level of the display panel 123 is changed or the image generator 112 has not generated the image data DIM, the frame displayed on the display panel 123 remains unchanged. In one embodiment, the data buffer circuit 129 is integrated into the timing controller 122.
Fig. 2 is another schematic diagram of the display device of the present invention. Fig. 2 is similar to fig. 1, except that the display apparatus 200 of fig. 2 has a conversion circuit 210, a selection circuit 220 and a storage circuit 230. In the present embodiment, when the display apparatus 200 operates in different modes, the display panel 123 presents a screen according to different gamma and look up tables.
In the present embodiment, the converting circuit 210 converts the level of the operating voltage PW to generate the voltage V1And V2. Voltage V1May be the same or different from the voltage V2. The converting circuit 210 provides a voltage V1Providing a voltage V to the display panel 123 and the storage circuit 2302The pre-selection circuit 220. In other embodiments, the conversion circuit 210 also provides the voltage V1The storage circuit 125 is provided with a voltage V2Pre-selection circuit124. In one possible embodiment, the converting circuit 210 is a direct current converter (DC/DC converter).
The selection circuit 220 selects the signal S according toSL2Selecting a gamma curve GMA～GMCOne of them is taken as a specific curve GMSAnd providing a specific curve GMSThe display panel 123. In the present embodiment, the signal S is selectedSL2Provided by the timing controller 124. The timing controller 124 is controlled according to the setting signal SSTGenerating a selection signal SSL2. Since the characteristics of the selection circuit 220 are similar to those of the selection circuit 124, the description thereof is omitted.
The storage circuit 230 stores a gamma curve GMA～GMC. In the present embodiment, the storage circuit 230 includes memories 231 to 233. The memory 231 is used for storing gamma curve GMA. The memory 232 is used for storing gamma curve GMB. The memory 233 is used for storing gamma curve GMC。
In other embodiments, the memories 231-233 further store over-drive information (OD)A～ODC. In this example, the selection circuit 220 selects the signal S according to the selection signalSL2Selecting overdrive information ODA～ODCOne of which is used as a specific information ODSAnd provides specific information ODSThe display panel 123. In some embodiments, a gamma curve GMA～GMCAnd drive information ODA～ODCStored in memories 126-128. In this example, the selection circuit 124 selects the signal S according to the selection signalSL1And outputting the data stored in the corresponding memory.
In one possible embodiment, the selection circuit 220 applies the gamma curve GM when the display apparatus 200 enters the first mode of operationAAs a specific curve GMS. When the display apparatus 200 enters the second operation mode, the selection circuit 220 converts the gamma curve GMBAs a specific curve GMS. When the display apparatus 200 enters the third operation mode, the selection circuit 220 converts the gamma curve GMCAs a specific curve GMS。
In another possible embodiment, the display deviceWhen the apparatus 200 enters the first operation mode, the timing controller 122 knows the frame rate of the image generator 112 according to the image data DIM, and requests the selection circuit 220 to dynamically select the gamma curve GM according to the frame rate of the image generator 112A～GMCAs a specific curve GMS. For example, in the first operation mode, when the frame rate of the image generator 112 is 180Hz, the timing controller 122 may require the selection circuit 220 to select the gamma curve GMAAs a specific curve GMS. In this mode, when the frame rate of the image generator 112 is 120Hz, the timing controller 122 may require the selection circuit 220 to apply the gamma curve GMBAs a specific curve GMS. Thus, in the same operating mode, the selection circuit 220 dynamically selects the gamma curve GMA～GMCOne of them is taken as a specific curve GMS。
In other embodiments, the display panel 123 includes gate drivers 241-243, data drivers 251-253, and a display area 260. The display area 260 has a plurality of pixels (pixels) PX. In one possible embodiment, the pixels PX are arranged in a matrix.
The gate drivers 241-243 generate a plurality of scanning signals S according to the vertical synchronizing signal VsyncSThe pixel PX is provided. The number of gate drivers is not limited in the present invention. In other embodiments, the display panel 123 may have more or less gate drivers.
The data drivers 251-253 are used for generating horizontal synchronizing signals Hsync, image data DIM and specific curves GMSGenerating a plurality of data signals SDThe pixel PX is provided. The number of data drivers is not limited in the present invention. In other embodiments, the display panel 123 may have more or fewer data drivers. In some embodiments, the data drives 251-253 are OD based on specific informationSGenerating a data signal SDThe pixel PX is provided.
Fig. 3A is a schematic view of a display panel according to the present invention. The display panel 300 includes a substrate 310, a backlight panel (backlight panel) 320, and a back case 330. In one possible embodiment, the pixel PX shown in fig. 2 is formed on the substrate 310. In this case, the gate drivers 241 to 243 and the data drivers 251 to 253 may also be formed on the substrate 310. In other embodiments, the data drivers 251-253 are disposed on three Flexible Printed Circuits (FPCs), respectively. In this example, three flexible boards are coupled to the substrate 310 for providing data signals to the pixels PX.
The backlight 320 has light emitting regions (zones) 321 to 324. In the present embodiment, the timing controller 122 lights at least one light-emitting area 321-324 according to a specific sequence by using a High Dynamic Range (HDR) local dimming (local dimming) technique, and controls the brightness of the light-emitting areas 321-324. When the light-emitting regions 321-324 are illuminated, light can pass through the substrate 310 and the back case 330. In other embodiments, the backlight plate 320 has more light emitting areas.
In some embodiments, the timing controller 122 controls the lighting sequence, speed, brightness and color of the light-emitting regions 321-324 according to the operation mode of the display device 120. For example, when the display device 120 enters the first operation mode, the timing controller 122 sequentially lights the light-emitting regions 321 to 324. When the display device 120 enters the second operation mode, the timing controller 122 sequentially turns on the light-emitting regions 324-321. In other embodiments, when the display device 120 enters the first operation mode, the timing controller 122 commands the light-emitting regions 321-324 to emit red light. When the display device 120 enters the second operation mode, the timing controller 122 commands the light emitting regions 321 to 324 to emit green light.
The back shell 330 has hollow areas 331-334. In a possible embodiment, the back case 330 is an a cover (a cover) of the notebook computer, i.e. an outer portion of the upper cover of the notebook computer. In the present embodiment, the hollow areas 331-334 correspond to the light emitting areas 321-324, respectively. Therefore, when the light-emitting regions 321-324 are lighted, the light can pass through the hollow regions 331-334. The invention does not limit the color of the light passing through the hollow areas 331-334. In one embodiment, the light passing through the hollow areas 331-334 is white light or other colors.
FIG. 3B shows the light emitting sequence of the hollow areas 331-334 of the present invention. In the embodiment, the shapes of the hollow areas 331-334 are font acers, respectively. In this example, the light emitting regions 321 to 324 are not lit up during the period T1. Therefore, no light passes through the hollow areas 331-334. In the period T2, only the light-emitting region 321 is lit. Therefore, the light passes through the hollow area 331. In the period T3, the light-emitting regions 321 and 322 are lit. Therefore, the light passes through the hollow areas 331 and 332. In the period T4, the light emitting regions 321 to 323 are lit. Therefore, the light passes through the hollow areas 331-333. In the period T5, the light emitting regions 321 to 324 are all lit. Therefore, the light passes through the hollow areas 331-334.
Fig. 4 is a schematic diagram of a timing controller according to an embodiment of the invention. As shown, the timing controller 400 includes a receiver 410, a decoder 420, a processor 430, an output interface 440, a memory 450, and a backlight controller 460. The receiver 410 is configured to receive and output image data DIM to the decoder 420. In one embodiment, the receiver 410 has an Embedded Display Port (eDP) for receiving the image data DIM.
The decoder 420 decodes the image data DIM to generate a decoded data DIMD. In one possible embodiment, the decoder 420 supports High-definition Digital Content Protection (HDCP) encrypted image data DIM.
The output interface 440 outputs the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync to the gate drivers 241-243 and the data drivers 251-253. In addition, the output interface 440 further outputs a selection signal SSL1And a pre-selection circuit 124.
In other embodimentsIn the embodiment, when the display device 120 switches the operation mode, the processor 430 reads a default data D stored in the memory 450PRAnd according to default data DPRThe vertical synchronization signal Vsync and the horizontal synchronization signal Hsync are changed to prevent the display panel 123 from displaying black images and flickering images. In one embodiment, each time the processor 430 outputs a frame data (frame) to the display panel through the output interface 440, the processor 430 stores the frame data in the memory 450. In this case, when the signal S is setSTWhen the level of the display panel is changed, the processor 430 reads and outputs the frame data stored in the memory 450 to the display panel. In other embodiments, the memory 450 may be independent of the timing controller 400.
In some embodiments, the processor 430 is configured to generate the image data DIM according to the default data D stored in the memory 450 when the image generator 112 has not generated the image data DIMPRThe display panel is commanded to present a specific screen, such as a Logo (Logo) of a manufacturer of the display device. Taking FIG. 1 as an example, when the host 110 is powered on, the processor 430 outputs the default data D through the output interface 440 before entering the operating system (e.g. Windows)PRThe display panel 123 is used for displaying the brand of the display device. In this example, the pattern of the brand of the display device is stored in the memory 450 in advance. In other embodiments, when an abnormality occurs in the host 110, the processor 430 waits for the image data DIM at the display device 120, according to the default data DPRA default frame is presented.
In this embodiment, the processor 430 generates an enable signal SENTo the backlight controller 460. The backlight controller 460 according to the enable signal SENControls the backlight plate 320. For example, when the host 110 is powered on, the backlight controller 460 is enabled according to the enable signal SENThe light emitting sequence of the light emitting regions 321 to 324 of the backlight 320 is controlled. In one embodiment, the memory 450 further stores a default order. In this example, the processor 430 generates the enable signal S according to a default sequence stored in the memory 450EN. In other embodiments, the signal S is enabledENIs a pulse modulated signal (PWM).
In other embodiments, the backlight plate 32 is used as a backlightIf the cursor moves rapidly, such as from a lighted light emitting area (e.g., 321) to an unlit light emitting area 324, the user may not immediately determine the position of the cursor when a portion of the light emitting area 0 is unlit. However, each time the processor 430 outputs a frame data to the display panel through the output interface 440, the processor 430 stores the frame data in the memory 450. Thus, the processor 430 can compare the previous and subsequent picture data and predict which light emitting areas should be lit or unlit in the next picture data. For example, in the previous frame data, the cursor is located in the light emitting region 321, and in the current frame data, the cursor is located in the light emitting region 322. At this time, the processor 430 predicts that the cursor will move to the light emitting region 323. Therefore, the processor 430 utilizes the enable signal S before outputting the next frame data to the display panelENThe backlight controller 460 is instructed to light the light emitting region 323 in advance.
In other embodiments, the timing controller 400 further comprises a timer 470. The timer 470 is used to time the usage of the display device 120. In this example, the processor 430 outputs the counter value CV of the timer 470 to the image generator 112. The image generator 112 appropriately adjusts the image data DIM according to the count value CV. In one embodiment, when the count value CV reaches a threshold value, the image generator 112 commands the display panel 123 to display a notification frame through the image data DIM, so as to notify the user of the color correction operation. In another possible embodiment, the processor 430 directly processes the decoded data DIMDFor correcting the color of the frame displayed on the display panel 123.
Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as commonly understood by one of ordinary skill in the art to which this invention belongs. Moreover, unless expressly stated otherwise, the definition of a term in a general dictionary shall be construed as being consistent with its meaning in the context of the relevant art and shall not be construed as an idealized or overly formal definition.
Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. For example, the systems, devices, or methods described in connection with the embodiments disclosed herein may be embodied in hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention should be determined by the appended claims.
Claims (10)
1. A display apparatus receiving an image data generated by an image generator, comprising:
a first memory for storing a first display data;
a second memory for storing a second display data, wherein the first and second memories are independently configured;
a selection circuit for selecting one of the first and second display data as a specific data according to a first selection signal;
a time sequence controller, which generates the first selection signal according to the voltage level of a specific pin and provides the specific data to the image generator, and the image generator generates the image data according to the specific data; and
and the display panel presents a picture according to the image data.
2. The display apparatus according to claim 1, wherein an address of the first memory storing the first display data is the same as an address of the second memory storing the second display data.
3. The display device of claim 1, wherein the display panel comprises:
a display area including a plurality of pixels;
a gate driver for generating a plurality of scanning signals to the plurality of pixels according to a vertical synchronization signal; and
a data driver for generating a plurality of data signals to the plurality of pixels according to the image data and a specific curve;
the timing controller decodes the image data to generate a second selection signal and the vertical synchronization signal, and the selection circuit provides one of a first gamma curve and a second gamma curve as the specific curve to the data driver according to the second selection signal.
4. The display apparatus of claim 3, wherein said first gamma curve is stored in said first memory and said second gamma curve is stored in said second memory.
5. The display device of claim 3, further comprising:
a third memory for storing the first gamma curve;
a fourth memory for storing the second gamma curve, wherein the first, second, third and fourth memories are independent.
6. The display apparatus according to claim 3, wherein the vertical synchronization signal has a first frequency when the specific data is the first display data, and has a second frequency when the specific data is the second display data, the first frequency being different from the second frequency.
7. The display apparatus according to claim 1, wherein the frame remains unchanged when the voltage level of the specific pin is changed.
8. The display apparatus according to claim 1, wherein the display panel presents a specific frame before the image generator generates the image data.
9. The display device of claim 1, wherein the display panel comprises:
a backlight plate having a plurality of light emitting regions,
wherein at least one light-emitting area is lightened according to a specific sequence by the time schedule controller.
10. The display device of claim 1, further comprising:
a timer for adjusting a count value according to the time of the display device,
wherein the image generator adjusts the image data according to the count value.
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