JP2762989B2 - Image signal processing device, image signal processing system and display system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRT controlled by a display controller or a microprocessor in a personal computer and an engineering workstation having an enhanced graphic function.
The present invention relates to an image signal processing apparatus for generating an image signal for displaying a display, a liquid crystal display, a plasma display, or the like, and more particularly, to an image signal processing apparatus having a palette (also referred to as a look-up table) for converting display data into display display data. About.

[0002]

2. Description of the Related Art FIG. 8 shows display data in pixel units and display display data (for example, digital RGB data).
1 shows a conventional example of a system for displaying a CRT display and a liquid crystal or plasma display provided with a pallet for converting into a liquid crystal display. According to the conventional example shown in FIG. 8, the palette 82 is composed of a RAM (hereinafter, palette R).
AM) 1 from the display controller 81
Clock 92 corresponding to pixel unit (pixel clock)
And display data 99 (pixel address) for each image unit. The palette 82 converts the display data into display data 93 by performing a read operation of the RAM using the display data as an address. The converted data of the pallet is written into the pallet RAM by the microprocessor 80 via the data bus 96. The display data 93 converted by the palette is
The signal is converted into a CRT display display signal 88 (for example, an analog RGB signal) by a digital / analog converter (hereinafter referred to as a D / A converter) 83 and supplied to a CRT display 87. The synchronization signal 91 to the CRT display is supplied from the display controller 81. On the other hand, in order to display a liquid crystal or plasma display, an analog signal for a CRT display which is an output of the D / A converter 83 is converted into an A / D signal by an analog / digital converter 84 (hereinafter referred to as an A / D converter). After the D conversion, the data is supplied to the liquid crystal / plasma display interface device 85 as display display data 90. Further, the interface device 85 is supplied with a pixel clock 92 corresponding to one pixel unit from the display controller 81 and takes in data for each pixel. A synchronization signal 91 for displaying a liquid crystal display or a plasma display is also supplied from the display controller 81 to the interface device 85. After that, the interface device 85 outputs the digital display signal 89 to display the liquid crystal or the plasma display 86.

In FIG. 8, reference numeral 94 denotes a control signal of the palette 82 output from the microprocessor 80;
Is a read / write signal output from the processor to put the pallet 82 in a write or read state. The pallet 82 writes the display conversion data supplied from the bus 96 when the panel 95 is in the write state, and reads the display conversion data from the bus 96 when the pallet 82 is in the read state.

Reference numeral 97 denotes a control signal for controlling the display controller 81 by the processor 80, and 98 denotes a bidirectional data bus between the two.

[0005]

In the above-mentioned prior art,
When an attempt is made to display a flat display, the palette output is converted to an analog signal for displaying a CRT display.
After D / A conversion to an analog signal such as a GB signal, the signal must be converted again to a digital signal using an A / D converter to create a signal for displaying a liquid crystal or plasma display. There has been a problem that the size of the additional display system itself is increased and the price is increased. Further, as in the conventional example of FIG.
Since it is composed of a semiconductor memory such as AM or ROM, and performs a conversion operation by reading out the same, in FIG. 7, after the display data (pixel address) of 99 is supplied to the pallet, A delay time is required until the data is converted into the display data or the analog signal 88 and output. Further, this delay time is caused by the read time of the ROM or RAM, and the read time of the semiconductor memory is unstable and has a considerable variation due to manufacturing or the like. It will be. Therefore, the phase relationship between the pixel clock 92 or the synchronizing signal 91 output from the display controller in synchronization with the pixel address 99 and the display data including the time delay is unstable, and the timing shift is caused. Will wake up. In the conventional example shown in FIG. 7, the pixel clock 92 and the synchronization signal 91 are supplied from the display controller to the interface device 85.
Controlling the timing of the D-converter is not only very difficult, but also has a problem that accurate data is not always taken in and the display causes a trouble such as jitter. Further, there is a problem that it is very difficult to speed up the system due to the above-described phase relationship. Similarly, when displaying on the CRT display, the synchronization signal 91 and the display display signal 88 supplied to the CRT display are in an unstable phase relationship, and cause a trouble such as jitter. Had the problem that

Accordingly, the present invention solves such a problem, and an object of the present invention is to be suitable for a system for displaying a flat display such as a liquid crystal display or a plasma display, and to realize a small, low-cost, and high-speed processing. Another object of the present invention is to provide an image processing apparatus capable of generating a high-quality image.

[0007]

According to the present invention, there is provided an image signal processing apparatus comprising: a pallet for outputting digital data for display based on display data on a pixel basis; and a first palette based on a clock signal corresponding to one pixel. A timing generator circuit for generating a clock signal, a data register for outputting the display digital data in synchronization with the first clock signal, a clock signal output terminal for outputting the first clock signal, A data output terminal for outputting the display digital data output from the data register.

A pallet for outputting display digital data based on display data in pixel units; a timing generation circuit for generating a first clock signal based on a clock signal corresponding to one pixel unit; A data register that outputs the display digital data in synchronization with the first clock signal; and a data register that outputs at least one of a horizontal synchronization signal and a vertical synchronization signal in synchronization with the first clock signal. A first synchronizing signal register for outputting.

A pallet for outputting display digital data based on display data in pixel units; a timing generation circuit for generating a first clock signal based on a clock signal corresponding to one pixel unit; First and second registers for outputting the display digital data in synchronization with the first clock signal; and D / for converting the display digital data output from the first register into an analog signal. A converter, an analog signal output terminal that outputs the analog signal, a digital data output terminal that outputs the display digital data output from the second register, and in synchronization with the first clock, A first synchronization signal register that outputs at least one of a horizontal synchronization signal and a vertical synchronization signal;
A clock signal output terminal for outputting the first clock signal.

Further, the timing generation circuit generates a second clock signal based on the clock signal corresponding to the one pixel unit, and synchronizes the second clock signal with the display data in the pixel unit. Is output to the palette.

Further, the timing generation circuit generates a second clock signal based on a clock signal corresponding to the one pixel unit, and synchronizes the second clock signal with the display data in the pixel unit. And a second synchronization signal register that outputs the synchronization signal to the first synchronization signal register in synchronization with the second clock signal.

Further, the present invention is characterized in that a delay circuit is provided for delaying the synchronization signal output from the second synchronization signal register and outputting the delayed synchronization signal to the first synchronization signal register.

Further, the image signal processing device is characterized in that it is formed on a single semiconductor substrate.

Further, the image signal processing system of the present invention comprises:
A display control circuit that outputs the display data in pixel units and a clock signal corresponding to the one pixel unit; and the image signal processing device. Moreover, it said image signal processing apparatus, the digital of the picture image signal processing device
Signal output from the
Display device based on the signal output from the
And an interface device for driving the
And

Further, the display system of the present invention includes an image signal processing device, a display device, and a signal output from the digital data output terminal and a signal output from the clock signal output terminal of the image signal processing device. And an interface device for driving the display device based on the display device.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on embodiments. FIGS. 1A and 1B show a first embodiment of the present invention.
FIG. 1 shows an embodiment of the present invention, in which reference numeral 100 denotes an image signal processing apparatus according to the present invention. Reference numeral 101 denotes an interface I / F unit with a display controller, which receives a pixel clock 116 and a pixel address 117 from the display controller. The pixel clock is a clock having a pixel frequency. The pixel address is digital display data in pixel units synchronized with the pixel clock. 1
Numeral 02 denotes a pallet, which is composed of a RAM, and uses 8-bit display data (pixel address) supplied from the display controller as an address signal, and reads out data stored at a specified address to obtain R ( Re
d: red) 6 bits, G (Green: green) 6 bits, B
(Blue: blue) 6-bit digital color data (1
12 to 114). Decoders 103 to 105 decode the R, G, and B palette output data for D / A conversion, and 106 to 108 output R, G, and R output analog values corresponding to the outputs of the decoders. , B
D / A converter. Reference numeral 115 denotes a liquid crystal or plasma display interface device, which is supplied with data converted by a pallet from the image signal processing device 100 and displays a liquid crystal or plasma display. On the other hand, 109 to 111 are analog RGB signal outputs, and D / A converters 106 to 108 output D / A signals.
By outputting the converted analog RGB signals,
A color display or a CRT display is performed according to the combination of the degrees of the respective analog values of RGB. In FIG. 1A, G6 bits are input to the liquid crystal or plasma display interface device from the digital RGB data (18 bits) converted by the pallet. In addition, the present invention can be applied to a system for displaying a monochrome liquid crystal or plasma display capable of displaying 2 ⁶ = 64 gradations.

The reason why G6 bits of the digital RGB data are output for a liquid crystal display or a plasma display is as follows. When converting an RGB primary color signal into a luminance signal (Y), the following conversion formula is used.

Y = 0.3R + 0.59G + 0.11B As can be seen from the above equation, of the R, G, and B components, the G component has the largest weight with respect to the luminance signal (Y). Therefore, when trying to display a monochrome (monochrome) display using any one of the R, G, and B signals, the most natural display is to use the G signal. For these reasons, G data 6
The bits are output as display data for a liquid crystal or plasma display.

In FIG. 1B, a total of 6 bits, that is, the upper 2 bits of each of R, G, and B, are input to the interface device. With such a configuration, 64 colors are displayed together with the CRT display. It can be applied to possible color liquid crystal displays. The output to the liquid crystal or plasma display interface device may be determined according to the display capability of the display in addition to the above two examples. In the embodiment shown in FIG. 1, a circuit for writing data to the palette RAM is omitted. Further, the image signal processing device 10
0 is realized as a one-chip semiconductor integrated circuit configured on the same semiconductor substrate.

FIG. 2 shows a system for displaying a liquid crystal or plasma display using an image signal processing apparatus according to a second embodiment of the present invention. Reference numeral 140 denotes an image signal processing device according to an embodiment of the present invention. Reference numeral 120 denotes a display controller, which transmits pixel data 12 serving as digital display data in pixel units to an image signal processing device 140.
5 and a pixel clock 126 having a pixel frequency
Supply. Reference numeral 131 denotes a pallet, which is composed of a RAM. Reference numeral 121 denotes a microprocessor (hereinafter, referred to as an MPU) for controlling the entire system.
Reference numeral 123 denotes a read signal, and 122 denotes a write signal. In accordance with the signals 124, 123, and 122, the MPU writes and reads converted data to and from the palette RAM. 132 is an MPU interface circuit,
When a write or read request to the palette RAM is received from U, control and interface inside the image processing apparatus 140 are performed. A data bus 133 transfers data to and from the palette RAM. The pixel clock 126 sent from the display controller 120 is input to the timing generator circuit 127. The timing generator generates a clock 128 to the pixel address register 130 and a clock 136 to the display data register 135 from the input pixel clock. The pixel address input from 125 is input to the pixel address register 130 and is taken into the register by the clock 128, and the address 1 to the palette RAM is stored.
29. The palette RAM outputs the storage data 134 at the location designated by 129 to the display data register 135. Palette RA
Each location of M stores RG color data or green color data. The display display data register 135 stores the data 1 output from the palette RAM.
34 is fetched by a clock 136. The data taken into the register is output from the data bus 137. A clock 136 to the display display register 135 is also output from the image signal processing device 140. Clock 136 output from the image signal processing device
Then, the display display data 137 is input to the liquid crystal or plasma display interface device 138 to drive the display 139. With this configuration, the display display data 137 synchronized with the output clock 136 is supplied to the interface device. That is, the display data 137 is determined when the data is taken into the display data register 137 by the clock 136, and the clock 136 is output as it is, so that the display data 137 and the clock 136 are always synchronized and the phase shift occurs. Does not happen.

The image signal processing device 140 is realized as a one-chip semiconductor integrated circuit.

FIG. 3 shows a system for displaying a display device using an image signal processing device according to a third embodiment of the present invention. Reference numeral 161 denotes an image signal processing device according to an embodiment of the present invention. Reference numeral 141 denotes a display controller, which supplies a pixel address 143 serving as display data, a pixel clock 142 having a pixel frequency synchronized with the pixel address, a horizontal synchronization signal 144 synchronized with the pixel clock, and a vertical synchronization signal to the image signal processing device 161. A synchronization signal 145 is provided. 151 is a palette, and R
AM. Reference numeral 146 denotes a clock buffer circuit, which outputs 1 from the input pixel clock 142.
The clock 148 is supplied to 47 pixel address registers, 155 display display data registers, and 150 and 156 synchronization signal registers. The pixel address register 147 takes in the pixel address supplied from 143 by the clock of 148, and 151
The address 149 is supplied to the palette RAM. The pallet RAM converts the pixel address into display data stored at the address specified by the address, and outputs it to the display data register 155 through the data bus 154. The display data register 155 takes in the data output from the palette RAM by the clock 148.
The data taken into the display register is 1
The image data is output from the data bus 57 and supplied to the display device 160.

On the other hand, the horizontal synchronizing signal 144 and the vertical synchronizing signal 145 are input to an image signal processing device 161 and then to a synchronization signal register A 150. 150
The synchronization signal register A takes in the data by the clock 148 and outputs the horizontal synchronization data 152 and the vertical synchronization data 153 to the synchronization signal register B of 156. Fifteen
Similarly, the synchronization signal register B of No. 6 takes in the data by the clock 148, outputs the horizontal synchronization signal of 158 and 1
Each synchronization signal is output to the outside from 59 vertical synchronization signal outputs. The horizontal and vertical synchronization signals output from the image signal processing device are supplied to 160 display devices. With this configuration, the horizontal and vertical synchronizing signals supplied from 144 and 145 are output from 158 and 159 after being delayed by a shift register composed of two registers 150 and 156. Will be. Then, the pixel address is supplied from 143, and 147
And the horizontal and vertical synchronizing signals supplied from 144 and 145 are taken into the 150 registers. The delay time from the output to the output from 158 and 159 is the same. This is a result obtained by controlling the registers 147 and 150 with the same clock and controlling the registers 155 and 156 with the same clock. In the embodiment shown in FIG. 3, a circuit for writing data from the MPU to the palette RAM is omitted. The image signal processing device 16
1 is realized as a one-chip semiconductor integrated circuit.

FIG. 4 shows an example in which the functions shown in the first to third embodiments are realized as one image signal processing device.
Shown in The image signal processing device 15 is configured on the same semiconductor substrate, and inputs pixel addresses (8 bits), which are digital display data in pixel units, into R, G,
B, each of which is converted into 6-bit digital color data, and the RGB data is converted from digital to analog,
It outputs 6 bits of G data as digital data at the same time as outputting as an analog RGB signal for displaying an RT display. 16 is a pixel clock input terminal, 17 is a horizontal synchronizing signal input terminal, 18 is a vertical synchronizing signal input terminal, and 19 is a pixel address input terminal. These signals are supplied from a display controller. 20 is a data bus, 21 is a control signal input terminal, 22 is a read / write control signal input terminal, and the above signals are MPUs for controlling the system.
And is used when the MPU writes and reads conversion data to and from the palette RAM. The pixel clock is input to one timing generator, and the timing generator generates 24 clocks and 25 clocks whose phase change is delayed from 24 clocks. The clock 24 is supplied to two synchronization signal registers A and three pixel address registers. Clock 25 is 7
, A synchronizing signal register B, 8 R registers, 9 G registers, 10 B registers, and 11 GDATA registers. The pixel address register 3 receives the pixel address data input from the input terminal 19 in response to the clock 24 and stores the pixel address data in the 6-barrel RAM (256
Address 32 is supplied to (word × 8-bit RAM).
The pallet RAM performs an operation of reading data stored in the area specified by the address 32, and outputs R6 bits,
G6bit and B6bit data are converted to 35, 36, 37
Output in parallel to the data bus. The registers 8, 9, and 10 take in the data output from the palette RAM with the clock 25 and output the data to the D / A converters 12, 13, and I4. Each D / A of 12, 13, 14
The converter D / A converts the data of R6 bit, G6 bit, and B6 bit, respectively, and outputs 44 R output terminals, 45
G output terminal, 46 B output terminal, more analog RGB
Output as a signal. Also, among the RGB data output from the palette RAM, 36 G data of 6 bits
Is also supplied to the 11 G data registers. The 11 G data registers take in the data by the clock 25 and output them as 6-bit data from the 47 digital G data output terminals. The two synchronization signal registers are:
The horizontal synchronizing signal and the vertical synchronizing signal input from the terminals 7 and 18 are taken in by the clock 24. The synchronization signal captured by the register 2 is input to the delay circuit 5. In order to prevent the shift register including the two synchronization signal registers A and B from causing a malfunction due to clock skew, the delay circuit simultaneously receives the synchronization signals 17 and 18 and simultaneously operates the delay circuit.
The synchronization signals output as 6, 27 are delayed. Without this delay circuit, the synchronization signal held in the register A by the clock 24 is immediately held in the register B by the clock 25, and the synchronization signal may be output one pixel clock earlier. The synchronization signals 28 and 29 output from the delay circuit 5
Is input to the synchronization signal register B. The synchronization signal register 7 receives the synchronization signal by the clock 25 and
And a vertical synchronizing signal output terminal 43. The clock 25 is output from the pixel clock output terminal 41. Reference numeral 4 denotes an MPU interface circuit, which controls a control signal from a control signal input terminal 21 and a read / write signal input terminal 22
It controls writing and reading of converted data to the palette RAM according to the read / write signal from the CPU. 4 is a pixel address register 3
8 bit write address 30 to palette RAM 6
And a control signal 31 are output, a read / write signal 33 is output to the pallet RAM 6, and the conversion data 34 is read from and written to the pallet RAM. Address data and conversion data are supplied from the data bus 20 from the display controller. The control signal from 21 switches whether the data input from 20 is an address or conversion data. When the read / write signal from 22 indicates writing and the control signal indicates an address, the address from the data bus 20 is output to the address register 3 via the bus 30. At this time, the control signal 31 indicates that the data fetched by the three registers is one.
Switch from 9 to 30. Next, when the control signal of 21 indicates the converted data, the converted data from 20 is supplied to the palette RAM via 34 and read / read.
Since the write signal 33 indicates writing, the conversion data input from 20 is written in the area specified by the address input from 20 and taken into the register 3. When the read / write signal from 22 indicates reading, the converted data is 35, 36, 37 from the palette RAM according to the pixel address input from 19.
Or read from the palette RAM to the bus 20
The data is read to

FIG. 5 is a timing chart showing the operation of the image signal processing device of FIG. FIG.
6 is a pixel clock inputted from (6).
4 and 24, and (C) is the clock of FIGS. The phase difference between (b) and (C) is the time required to convert the display data in the palette RAM. 4D is a horizontal synchronizing signal input from FIGS. 4 and 17, and FIG.
This is a pixel address input from the address 19. (F) is the signal of FIGS. 4 and 26, and the synchronization signal register A of FIGS.
5A and 5B are horizontal synchronization signals captured by the clock of FIG. (G) is a signal of FIGS. 4 and 32, which is a pixel address taken into the pixel address register 3 by the clock of (b), and becomes the address 32 of the palette RAM. (H) shows the signals of FIGS. 4, 35, 36 and 37, which are the output data of the palette RAM. (I) is a horizontal synchronizing signal outputted from FIGS. 4 and 42, and is taken into the register of FIGS. 4 and 7 by the clock of (C) and outputted. (J)
Are digital G data output from FIGS. 4 and 47 or digital R data output to 38, 39 and 40, respectively.
4A, 4B, and 4C, which are GB data.
Each of the registers 1, 8, 9, and 10 is fetched and output. (K) is an analog RGB output output from FIGS. 4, 44, 45, and 46. The analog RGB output is taken into each register of FIGS. 4, 8, 9, and 10 by the clock of (C) and D / A converted. Output later.

FIG. 6 is a block diagram of a system for displaying a CRT display and a liquid crystal display using the image signal processing apparatus according to the embodiment of the present invention shown in FIG.
Shown in Reference numeral 52 denotes an image signal processing device according to the present invention implemented as a one-chip semiconductor integrated circuit. Reference numeral 50 denotes an MPU for controlling the entire system. For the image signal processing device 52, conversion data is designated by a palette RAM. Reference numeral 51 denotes a display controller, which is controlled by the MPU, and is connected to an image signal processing device 52.
A pixel clock 61, a horizontal synchronization signal 62, a vertical synchronization signal 63, and a pixel address 64 are supplied. The image signal processing device 52 supplies an analog RGB signal 69 and a delayed horizontal synchronization signal 68 and a vertical synchronization signal 67 within the image signal processing device to the CRT display 54. Further, the image signal processing device supplies the liquid crystal display or plasma display interface device 53 with a pixel clock output 66 and a digital G data 65, a horizontal synchronization signal 68 and a vertical synchronization signal 67 in synchronization with the output clock. Supply. Then, the liquid crystal display or the plasma display interface device drives the 55 liquid crystal or plasma display. 8, reference numerals 56, 57, 58, 59, and 60 correspond to reference numerals 98, 97, 94, 95, and 96 in FIG. According to FIG. 4 and FIG. 6, the liquid crystal or plasma display performs gradation display in which each pixel displays shades corresponding to the value of 6-bit G color data, but the present invention is not limited to this, and FIG. As described above, the upper several bits of the RGB color data may be output. In this case, the liquid crystal display performs color display on each pixel. Note that the number of bits of color data output from the image signal processing device is not limited to that of the embodiment, and the larger the number, the more grayscale or multicolor display is possible.

FIG. 7 shows a specific configuration of the timing generator shown in FIGS. 1
Reference numeral 70 denotes an inverter, to which a pixel clock from outside the 171 is input. This clock 171 is the clock of FIG. 172 is the clock of FIGS. 2, 128, 4 and 24, and is shown in FIG. 5 (b). 173 corresponds to FIGS.
6, FIG. 4 and FIG. 25, which are shown in FIG. 5 (C). As shown in FIG. 7, the phase of the input pixel clock is delayed by an inverter, and is output to 102 and further to 103, respectively.

In the embodiment of the present invention, the synchronizing signal is output from the apparatus. However, in order to apply the present invention to a CRT display apparatus which requires a blanking signal, the synchronizing signal has the same structure as that of the synchronizing signal. The ranking signal may also be delayed and output to the CRT display.

Further, in the embodiment of the present invention, a diagram is shown in which both a CRT display and a liquid crystal display or a plasma display are connected to the image signal processing apparatus, but in actual use, the CRT display, the liquid crystal display or the plasma display is used. Is connected and used as a display device. Further, the liquid crystal or plasma display may be an electroluminescence (EL) display.

As described above, according to the embodiment of the present invention, not only the display data converted by the pallet is output as a signal for displaying the CRT display such as an analog RGB signal, but also the liquid crystal or the plasma is simultaneously displayed. For display interface devices,
By supplying display display data, an A / D converter and a circuit for controlling the A / D converter, which were required in the conventional system, are no longer necessary. This has the effect that it can be constructed at a small size and at a low price.

Further, a clock signal (pixel clock) corresponding to one pixel unit and display display data are output in synchronization with the clock signal. In addition, since the display data is output through a circuit formed on the same semiconductor substrate, a temperature change occurs. Even if there is, the amount of delay applied to the output is the same, the phase difference between the two is stable and a constant phase relationship can always be maintained, so on the liquid crystal or plasma interface device side,
It is possible to capture data accurately and easily. Further, conventionally, when displaying on a liquid crystal or plasma display, the output of the D / A converter is A / D converted. However, the present invention does not require an A / D converter.
This has the effect of enabling high-speed processing of display data to be displayed on a liquid crystal or plasma display.

Further, the same delay time as converting the pixel address supplied by the display controller into display data and outputting the data is represented by the following formula:
Since the display control signals such as the horizontal and vertical synchronization signals supplied from the same display controller are output after being given, the relationship between the display control data and the display data is always in a stable state. There is an effect that a stable and high-quality image without obstacles can be supplied.

In addition, when an image signal processing apparatus such as the present invention is used to make a CRT display system capable of displaying on a liquid crystal display or a plasma display, the display interface side does not have a conventional configuration. It is not necessary to consider such a timing problem, and the system can be easily constructed.

[0034]

According to the present invention, a vertical or horizontal synchronizing signal is output in synchronization with a first clock, and display digital data converted into an analog signal is output in synchronization with the first clock. As a result, the phase relationship is stabilized, and there is no need to worry about occurrence of timing shift . Also, the display of the present invention
The system uses such an image signal display device.
Therefore, display troubles such as jitters can be solved.

[0035]

[Brief description of the drawings]

FIGS. 1A and 1B are block diagrams showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a display system using an image signal processing apparatus according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a display system using an image signal processing apparatus according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the image signal processing device of FIG. 4;

FIG. 6 is a block diagram of a system for displaying a CRT display or a liquid crystal display using the image signal processing device according to the embodiment of the present invention.

FIG. 7 is a specific configuration diagram of a timing generator.

FIG. 8 is a block diagram showing a display system using a conventional image signal processing device.

[Explanation of symbols]

1,127 Timing generator 2,150 Synchronous signal register A 3,130,147 Pixel address register 5 Delay circuit 6,82,102,131,151 Palette 7,156 Synchronous signal register B 8,106 R register 9,107 G register 10, 108 B register 11 Data register 12, 13, 14, 83, 106, 107, 108 D
/ A converter 80,121 Processor 81,120,141 Display controller 84 A / D converter 85,115,138 Liquid crystal / plasma display interface 86,139 Liquid crystal / plasma display 87,160 Display 101 Controller 132 MPU interface 135 Display display Register 146 Clock buffer

Claims (10)

(57) [Claims] A pallet for outputting digital data for display based on display data in pixel units; a timing generation circuit for generating a first clock signal based on a clock signal corresponding to one pixel unit; A data register that outputs the display digital data in synchronization with one clock signal; a clock signal output terminal that outputs the first clock signal; and outputs the display digital data output from the data register. And a data output terminal. 2. A pallet for outputting display digital data based on display data in pixel units; a timing generation circuit for generating a first clock signal based on a clock signal corresponding to one pixel unit; A data register that outputs the display digital data in synchronization with the first clock signal; and a data register that outputs at least one of a horizontal synchronization signal and a vertical synchronization signal in synchronization with the first clock signal. An image signal processing device, comprising: a first synchronization signal register for outputting. 3. A pallet for outputting display digital data based on display data in pixel units; a timing generation circuit for generating a first clock signal based on a clock signal corresponding to one pixel unit; First and second registers that output the display digital data in synchronization with the first clock signal; and D / that converts the display digital data output from the first register into an analog signal. An A converter, an analog signal output terminal that outputs the analog signal, a digital data output terminal that outputs the display digital data output from the second register, and in synchronization with the first clock, A first synchronization signal register for outputting at least one synchronization signal of a horizontal synchronization signal and a vertical synchronization signal; and the first clock signal And a clock signal output terminal for outputting a clock signal. 4. The timing generation circuit generates a second clock signal based on a clock signal corresponding to the one pixel unit, and synchronizes the second clock signal with the display data in the pixel unit. 4. The image signal processing apparatus according to claim 1, further comprising a pixel register that outputs a pixel register to the palette. 5. The timing generation circuit generates a second clock signal based on a clock signal corresponding to the one pixel unit, and synchronizes the second clock signal with the display data in the pixel unit. And a second synchronizing signal register that outputs the synchronizing signal to the first synchronizing signal register in synchronization with the second clock signal. 4. The image signal processing device according to 2 or 3. 6. The image signal according to claim 5, further comprising a delay circuit for delaying the synchronization signal output from the second synchronization signal register and outputting the delayed synchronization signal to the first synchronization signal register. Processing equipment. 7. The image signal processing device according to claim 1, wherein the image signal processing device is formed on a single semiconductor substrate. 8. A display control circuit for outputting the display data in pixel units and a clock signal corresponding to the one pixel unit, and the image signal processing device according to claim 1. Characteristic image signal processing system. 9. The image signal processing device according to claim 1, 3 or 4, and a signal output from the digital data output terminal and a signal output from the clock signal output terminal of the image signal processing device. And an interface device for driving the display device. 10. The image signal processing device according to claim 1, 3 or 4, a display device, and a signal output from the digital data output terminal and a signal output from the clock signal output terminal of the image signal processing device. And an interface device for driving the display device based on the signal.