JPS6374099A - Interface circuit for liquid crystal display device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an interface for a liquid crystal display device, and in particular to a C
By using only the separate video signal of RT display = 2 to generate the display data and timing signals necessary to operate the liquid crystal display device, and by replacing the CRT display device with the liquid crystal display device, Display O: 1; Indicates an ink-face circuit that can supply ink.

(Summary of the Invention) The present invention stores display data in a frame buffer memory (RAM) by using a display data synchronization signal of a CRT display device or a composite (separate video signal obtained by dividing No. 3 by 1 by 1). The input display data is processed in real-time and converted into a mixture of red, green, and blue display data without the need for color display.With the same drive circuit configuration as before, it has an interface function that allows color display and monochrome display. This invention relates to an interface circuit for a liquid crystal display having an interface function.

[Conventional technology]

Liquid crystal display devices have the characteristics of being thin, low voltage, and low power consumption, and have recently come to be put into practical use as display terminals for personal computers, word processors, etc. using large dot matrix panels. Today, C
Instead of RT, a liquid crystal interface circuit that can be directly connected to a CRT control circuit has been developed for use as a display terminal for a portable personal computer.

However, the interface circuit of the conventional liquid crystal display device is designed based on the idea that the liquid crystal panel is driven even during the blanking period of the CRT display device. Therefore, for display data, a frame buffer memory is prepared, and after the display data is written into the frame buffer memory, it is read out sequentially6.Furthermore, conventional interface circuits are only for monochrome display. Therefore, the display information fEiffl is insufficient when displayed in graph ink. 0N10 simply by using one or three of the red, green, and blue color display data on the Risox LCD panel.
Because of the FF display, the display device was not as attractive as a CRT display device. However, on the other hand, the technical strength of colored filters is placed on the surface of the transparent electrode of the liquid crystal panel, and TPT (thin film transistor) and M
Despite the development of panels with built-in active elements such as non-linear elements such as IM and MSI, or new liquid crystal panels with memory functions such as smectic liquid crystals, interface circuits for color liquid crystal display devices have not yet been developed. . For this reason, it was necessary to install interface circuits for the monochrome liquid crystal display device, which requires a frame buffer memory, for red, green, and blue colors.

[Problem that the invention seeks to solve]

As described above, the interface circuit of the conventional liquid crystal display device requires a frame buffer memory to be prepared as an external circuit and data to be loaded and read under the control of the interface circuit. As a result, the cost of the circuit structure became high, the circuit structure became complicated, and it was difficult to assemble it into a small display terminal. It is an interface circuit exclusively for monochrome display, and 47! interface circuits for color liquid crystal display devices! In order to achieve this, it is necessary to prepare three interface circuits for the monochrome display, and 4' is simply 3 (H'3's high 1ITli Hiiragi, and a complex configuration of 1). The present invention has been made to solve the above problems, and has a function of directly interfacing display data and timing signals to a liquid crystal display device by real-time processing of video signals of a CRT display.
It is an object of the present invention to provide an interface circuit that is applicable to monochrome and color liquid crystal display devices.

[Means for solving problems]

In order to solve the above problems, the present invention provides an interface circuit for a liquid crystal display device that receives a separate video signal for an RT display device and converts it into display data signals and timing signals for operating the liquid crystal display device. l'; 1. An S/P conversion circuit for converting G and H color display data into parallel data;
The first switching circuit group includes a color mixing means for converting the output of the /P conversion circuit into mixed color data with regularity for each bit of R, C, and B, and switches the mixed color data in a time-divisional manner. A monochrome display device comprising a color display data processing circuit section and a second switching circuit group for time-wise switching the output of the S/P conversion circuit for at least one of R, G, and B display data. The display data processing circuit includes a display data processing circuit section.

〔Example〕

Next, one embodiment of the present invention will be described.

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG.
The figure is a timing diagram to supplement the explanation of the operation of the circuit shown in FIG. 1 above.

In FIG. 1, l1syC is the horizontal synchronization signal, Vsy
c is a vertical synchronization signal, CK is a dot clock signal, R
D, CD, and BD are red, green, and blue display data, respectively. These l1syc, Vsyc, CK,
R.D.

GD and BD are equivalent to interface signals to a CRT display device. 1 is an X-axis display position adjustment circuit that counts the dot clock CK to adjust the display position in the X-axis direction; 4 is a Y-axis display position that counts the horizontal synchronization signal 11syc and adjusts the display position in the Y-axis direction. Adjustment circuit 3 is the X-axis and Y-axis display position 314
An AND circuit which takes the outputs of the F circuits 1 and 4 and the dot clock CK as a human value, 6, a /8 frequency divider circuit for dividing the frequency of Chronoquia No. 3 P1, which is the output of the AND circuit 3, by 178, 7 10.11.12 is a frequency dividing circuit for further dividing the output P2 of the 178 frequency dividing circuit 6 to generate a reset signal P3 for resetting the X-book display position adjustment circuit; (e) Shift register circuits for shifting the blue display data; 13, 14.15 are latch circuits for temporarily latching the display data of the shift registers 10.11 and 12; 41 to 46 are the above-described latch circuits; Launch circuit 1
a switching circuit 28 for time-divisionally switching the display data of 3 to 15 and outputting the display data to an X electrode drive circuit (X driver) of the liquid crystal display device; This is a shift register that cannot be used for switching.

24 and 25 are D-type flip-flop circuits (D-type F/F circuits) for receiving the clock No. 13 P2 as input and generating a launch (δ No. P4). 21 is a D-type flip-flop circuit for generating the latch signal P4. 16 and 17 are the set-reset flip flow knob circuits for setting by the above-mentioned Y!JI display position 4pJA.
When H11 rises, the set pulse signal P.

D-type flip-flop circuit and NOR to generate
It is a circuit. 18 is a flip-flop circuit for generating a cent output according to the set pulse signal P;
41.48 is a D-type flip-flop circuit for delaying the output of the flip-flop circuit 18. The output FRM of the above-described flip-flop circuit 48 is a frame signal. 20 is the frame signal FR
This is a flip-flop circuit that divides the frequency of the M signal by two. The output of the flip-flop circuit 20 is a liquid crystal AC drive No. 43M. Further, LK is a latch signal of a latch circuit built in the X-sheet drive circuit which transfers the display data transferred to the X-shape drive circuit. 31 is a clock signal I
) This is a divide-by-2 circuit that divides 1o by two. 33 is
This is a flip-flop circuit that divides the output I]1 of the frequency dividing circuit 31 by η. 39.40 is a switching circuit for switching the display data of the child circuit 15 in a circular manner. 35+36 and 37
is an A N D circuit and an OR circuit, and in the case of monochrome or color display, display data is converted to X electric I! i! It constitutes a long gate circuit for selecting the shift clock SK of the 4-bit parallel shift I register built into the drive circuit.

Next, a description will be given of an embodiment of the present invention made by IIJ shown in FIG. 1.

X and other display positions 3J8 adjustment circuit 1 outputs horizontal synchronization signal It S
When yc is input, the dot clock CK starts counting. When this count value matches the set value of the blanking period of display data, the output T1 of the X-axis display position "l adjustment circuit 1" rises to 'H'.

This blanking) setting can be adjusted in the 1F position by an external setting means such as a digital switch.The Y-axis display position adjustment circuit 4 opens horizontally when the vertical synchronization signal Vsyc is input. Start counting the 1 signal 11syc. If this count value exceeds the setting value of blanking 1tiXt in the Y-axis direction of the display data, the output T of the Y-axis display position adjustment circuit 4
2 rises to 'H'. The setting of this blanking period can be adjusted in units of 1 dot by an external setting means such as a digital switch as described above.The output T of the X-axis and Y-axis position adjustment circuit , and T2 are both II H1
1, the display starting point (home position)
Then, the AND circuit 3 outputs the clock signal P.

Clock signal P is input to 178 frequency divider circuit 6 and shift register 10.11.12. Display data RD.

CD and BD use shift registers 10 and 11 for each clock to use the clock signal P1 as a shift clock.
．． Shifted to 12. The output P2 of the 1 to 8 frequency divider circuit 6 generates a latch signal P4 every time eight clock signals P are inputted by the D-type flip-flop circuit 24 and the NOR circuit 25, and outputs the latch signal P4 to the shift register +0. .1
1.12 parallel display data, latch circuit 13,1
We had lunch at 4.15 and performed S/Pg exchange.

Latch signal P4 is inverted by inverter 26,
Since the flip-flop circuit 21 is set, the AND circuit 22 starts outputting the clock signal pH1.The clock signal PIG is frequency-divided by the '/S frequency divider circuit 27 and inputted as a shift clock signal of the shift register 28. . Since the shift register 28 uses the output of the NOR circuit 29 as shift data, it operates as a quaternary ring counter and receives the switching control in signals PS, P, , P,
, and the switching circuits 41, 42, 43, 44.
45 and 46 are time-divisionally switched Ow1 to output display data (UD, -Ul:h) and (LD, to LD,) in parallel. The clock signal P1° is frequency-divided by 2 by the flip-flop circuit 23 and outputs a clock signal P8.

Furthermore, since the flip-flop circuit 23 is reset by a signal obtained by inverting the shift l-data of the shift register 28 by the inverter 30, the clock signal P
Input 8 clocks of 1°, Chrono Quit No. 3 I) 8 to 3
The clock is outputted and passed through an AND circuit 36 and an OR circuit 37 to generate a shift clock SK.

The outputs of the launch circuits +5, 14, and 13 are input to the switching circuits 41 to 46 as follows in order to provide mixed color display data of R, G, and B (red, green, and blue). The switching circuits 41 to 46 are composed of 4-bit parallel transmission gates, and their inputs are R1°G+, B1 from the first bit of the launch circuit 15.14.13.
-Assuming 8 bits of Re, Go, and Bs, the switching circuits 41 to 46 are connected to (p) in the table below.

As described above, switching circuits 41, 43, 45 and 42.
44 and 46 are grouped into upper display data UD, ~UD, and lower display data LDo~LD, and display data of color display data RD, GD, and BD are displayed alternately from the Separated and entered.

Therefore, the display data UD, -1jDll is (R1,B
I.

Gz, R3><Bx, G4...), and the display data L Do ” L D z is (G8.R
z, Bz, G3) (1?4.B,,...) is generated.

Next, a timing signal sent to the liquid crystal display 2i will be explained.

When the output T2 of the Y-axis display position adjustment circuit 4 rises, it is inverted by the inverter 5, and the set pulse P is output by the D-type flip-flop circuit 16 and the NOR circuit 17.
, and sets the flip-flop circuit 18.

The clock signal P2 of the 178 frequency divider circuit 6 is counted by the frequency divider circuit 7, and after counting (for example, 700 counts) until the display data in the X-axis direction is manually input, the D-type flip-flop circuit 9 and the NOR circuit 8 generates a reset signal Pyu, and resets the frequency divider circuit 6, the frequency divider circuit 7, and the flip-flop circuit 18. This reset signal P3 is the X electric 1ff! This becomes the latch signal LK of the launch circuit incorporated in the drive circuit (X driver) and the shift clock YSCL of the shift register built in the Y electrode drive circuit (Y driver). The output of the flip-flop circuit 318 is delayed by D-type flip-flop circuits 47 and 48 to output a frame signal FRM, which becomes scanning start data for the Y electrode drive circuit (Y driver). The frame signal F
The frequency of RM is divided by a frequency divider circuit 20, and the AC drive signal M is divided so that the polarity of the drive voltage is inverted every frame.
is generated and output to the X'-pole and Y-electrode drive circuits.

The above is an explanation of the operation when displaying in color.

Next, the case of monochrome display will be explained.

The clock signal P1G is input to the A frequency dividing circuit 31,
A frequency-divided output pH is output, and the frequency is further divided by 2 by the 2-divider circuit 33, and the switching control signal Pli pus of the switching circuits 39 and 40 is output. The inverted output of the frequency-divided output PI3 of the divide-by-2 circuit 31 is connected to the AND circuit 3.
5. Through the OR circuit 37, the X7S pole drive circuit (X
The exclusive OR circuits 47, 48, and !9 are polarity switching circuits for inverting or normal rotation of the display data RD, CD, and BD. (Yes, switch SW+ is ON), the display -j'-ta RD, CD, BD
C. Since the display data is reversed when it is inverted and OFF, it is possible to switch the display between NEGA/Po5i. Further, the switch SK2 is for selecting color display or monochrome display, and when the switch SW is OFF, the inverted output of the output pH of the A frequency dividing circuit 31 is sent to the selection gate circuit 35, At the same time as the monochrome display shift clock SK is generated via the OR circuit 37, the output of the switching circuit 39□40 is made active, and the outputs of the switching circuits 41 to 46 are placed in a high impedance state. Conversely, when the switch S6 is ON, the clock signal P8 of the flip-flop circuit 23
passes through the AND circuit 36, 017, and circuit 37, and generates the color display shift clock, SK, and at the same time, makes the outputs of the switching circuits 41 to 4G active, and switches the output of the switching circuit 39, 40 to high impedance. works.

As described above, the display mode can be switched between color display and monochrome display by changing the voltage level of the selection terminal S2. Further, the selection of NEGA/Po5i display can also be changed by setting the voltage level of the selection terminal S.

In the timing diagram of Figure 2, (A) indicates the X axis and Y axis.
It shows the timing of outputs Tl and T2 of the axis display position adjustment circuit. (B) shows the timing of clock signals P1 and P3, and (C) shows the switching control signal P3. P,
, P, and display data UD, ~UD,, LD, ~LD,
The timing of (D) is the display data L in monochrome display.
The timing of D, ~LD, (E) is the shift clock CK which is the timing signal to the drive circuit of the liquid crystal display device.
, shows the timings of the latch clock LK, frame signal FRM, and AC drive signal M, respectively.

FIG. 3 shows an example of the electrode configuration of a color liquid crystal panel for color display according to the present invention.

The colored arrangement tube of the electrodes is not limited to this example. FIG. 4 shows the system configuration of an embodiment of the present invention. (A) shows a system configuration for monochrome display, and (B) shows an example of a system configuration for color display, which allows for a deeper understanding of the present invention.

〔Effect of the invention〕

As described above, according to the present invention, interface signals of a CRT display device are used to convert into display data and timing signals of a liquid crystal display device in real-time processing, so that: ■ a frame buffer memory is not required; It has become possible to manufacture small, low-cost liquid crystal display terminals by using gate array ICs.

■It has become possible to supply interface circuits for color display, which did not previously exist, further increasing the appeal of liquid crystal display devices. (2) The interface S allows selection of monochrome display or color display mode. (2) Since the same conventional drive circuit can be used, there is no need to develop a dedicated color drive circuit, which has great effects.

The present invention also applies to active matrices with built-in non-linear resistance elements such as MIS and MIM, active matrices with built-in switching transistors such as TPT panels, and ferroelectric liquid crystal panels with memory properties such as Smectinok liquid crystal panels. Regarding this, it is particularly effective for these new type of liquid crystal panels that utilize the memory properties of the elements even during the blanking period.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a diagram showing the timing of FIG. 1, FIG. 3 is an electrode configuration diagram of an embodiment of a color liquid crystal panel, and FIG. 4 (A>, (B) is a diagram showing the system configuration. 1... X-axis display position adjustment circuit 2...Y-axis display position adjustment circuit 3...AND circuit 10.11.12...Shift register 13.14.1
5...Latch circuits 39-46...Switching circuit 6...178 Frequency divider circuit 7...Frequency divider circuit 9, 16, 24, 47.48...D type flip-flop circuit 18.2L23. ...Flip-flop circuit 20
．． 27.33...2 frequency divider circuit 31...Z frequency divider circuit or higher 'T2-112F--4 B) lJDa-t, VDi product-L/DJ D)

Claims (2)

[Claims] (1) In the interface circuit of the liquid crystal display device, which receives separate video signals for the CRT display device and converts them into display data signals and timing signals for operating the liquid crystal display device, R, G, and B color display data are An S/P conversion circuit for parallel conversion and a color mixing means for converting the output of the S/P conversion circuit into mixed color data with regularity for each bit of R, G, and B are provided, and the mixed color data is and a color display data processing circuit section including a first switching circuit group that time-divisionally switches the output of the S/P conversion circuit for at least one of the R, G, and B display data in a time-divisional manner. 1. An interface circuit for a liquid crystal display device, comprising a monochrome display data processing circuit section having a second switching circuit group for the purpose of processing. (2) In the interface circuit for a liquid crystal display device according to claim 1, a display for selectively switching ON/OFF the output of the color display data processing circuit section and the monochrome display data processing circuit section. An interface circuit for a liquid crystal display device, comprising a mode switching means and a display data inverting means for inverting color display data.