JPS62244098A - Color liquid crystal display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention <<Industrial Application Field>> The present invention relates to an interface circuit for a color liquid crystal display device, and in particular uses only the interface signals of a CRT display device, which is often used in personal computers, etc. The present invention relates to a color liquid crystal display device having an interface circuit that can be used as a substitute for a conventional liquid crystal display device.

(Summary of the Invention) The present invention utilizes interface signals of a CRT display to store independent color display data in an independent RAM, and when reading it, converts it into mixed display data of red, green, and blue. The present invention relates to a color liquid crystal display device that can provide an interface circuit capable of color display with a drive circuit configuration equivalent to that of the present invention.

(Prior Art) Liquid crystal display devices have the characteristics of being thin, low voltage, and low power consumption, and have recently come to be put into practical use as display terminal devices for personal computers, word processors, etc. using large dot matrix panels. . Today, LSIs that can be directly connected to a CRT interface are used as a replacement for CRTs and are used as portable personal computers.
The circuit was developed, and each 0AII device developer manufacturer
Interface circuits dedicated to liquid crystal displays have come to be manufactured using gate arrays, and this has led to a significant demand for liquid crystals. [However, although these liquid crystal display devices have a display capacity such as 640 x 200 dots that can replace a CRT, they have a monochrome, single-color display, so when displaying graphics, etc., it is difficult to display information. It is insufficient. On the simple matrix display panel, red, green,
Since ON/OFF display is simply performed using one or two of the blue color display data, the display device is not as attractive as the CRT:F display.

(Problems to be Solved by the Invention) As mentioned above, the interface circuits of conventional liquid crystal display devices were monochrome displays, which made them less attractive, but in recent years color liquid crystal display devices have been developed. Therefore, it is an object of the present invention to provide an interface circuit that is applicable to a liquid crystal display device and is capable of color display using interface signals of a color CRT.

(Example) Next, an example of the present invention will be described. Figure 1 shows
1 is a configuration diagram showing the entire color liquid crystal display device of the present invention. In FIG. 1, tlsyc is the horizontal same m signal, vs
yc vertical synchronization signal, OR, DG, DB are red, green, respectively.
This is a blue display data signal.

GK is a clock signal. Y-axis display area control circuit 1
is a control circuit that counts the horizontal synchronization signal HSYc and determines the display area in the Y-axis direction. X@Area control circuit 3
is a control circuit that counts the clock signal CK and determines the display area in the X-axis direction.

During the display area period, the sampling pulse generation circuit 5
The S/P conversion circuit 8.9.10, which is a circuit for dividing the clock signal CK and sampling and capturing data, is
Conversion circuit and RAM for converting red, green, and blue serial display data DR, DG, and DB into parallel data, respectively.
11.12.13 is a memory circuit for storing red, green, and blue parallel data. P/S conversion transformation circuit 145.1
6 is a conversion circuit that converts each parallel data of the memory circuit RAM 11, 12, 13 into serial data.

The AND circuits 17, 18, and 19 and the OR circuit 20 are selective gate circuits that selectively and sequentially take out the outputs of the respective P/S conversion conversion circuits 145 and 16, and convert them into mixed serial data of red, green, and blue. The S/P conversion circuit 31 is a conversion circuit that converts serial mixed display data into parallel data.

Write address counter 21 receives vertical synchronization signal V
After being reset by syc, the memory circuit RAM11, 12
．． A circuit that counts 13 addresses. The latch pulse generation circuit 6 is a circuit for generating a latch pulse every time the sampling pulse generation circuit counts eight zumbling pulses, and latching the register of the S/P conversion circuit 8.9.10. . Further, the latch pulse of the latch pulse generation circuit 6 becomes a counter input of the write address counter 21 mentioned above. The road address counter 24 is a read address counter circuit for the memory circuit RAM11.12.13. The selection circuit 33 is a memory circuit RA.
Write the address of M11, 12゜13 (Write
) or Read) to switch the address line. Frequency dividing circuit 7 is a circuit that divides the frequency of the clock signal CK to reduce the frequency. The ring counter 22 is constituted by a ternary ring counter, and is
Sequentially take out the red, green, and blue display data of the S conversion circuit 14, 15, and 16, and generate a selection pulse to obtain mixed serial display data from the selection gate circuit 17, 18, 19, 20. circuit.

The 1/9 counter 23 receives the counter input signal of the read address counter 24 and the memory circuit RAM 11.
, 12. The display data of 13 is converted to P/S by the transformation circuit 145.
．． This is a circuit that generates a latch signal to latch the ring counter 22, and outputs a carry signal of one pulse every time nine pulses of the carry signal q of the ring counter 22 are input.

The 1/4 counter 25 is a circuit for supplying a latch signal to the S/P conversion circuit 31 every time four output pulses from the frequency dividing circuit 7 are input. The shift clock generator 26 is a circuit that generates a shift clock signal for a 4-bit parallel shift register built in the X electrode drive circuit 32.

The latch clock generator 27 is the X sovereign drive circuit 3
2, and the data of the Y electrode drive circuit 30.

A circuit that generates a latch signal that turns on. The frame signal generation circuit 28 is a circuit that generates a frame signal (data for the Y electrode). The AC signal circuit 29 is connected to the X electrode drive circuit 32 . Y
A circuit for switching the polarity of the drive signal of the electrode drive circuit 30. The color liquid crystal panel 34 has red and green as X@main electrode and transparent electrode.

LCD panel with a blue filter attached. The Xff1 pole drive circuit 32 is a circuit for driving the X-axis electrode of the color liquid crystal panel 34. Next, the operation of one embodiment of the present invention will be explained.

The Y-axis display area control circuit 1 inputs 1lsyc and
A signal indicating the axis effective display area time is output to the AND circuit 2. The clock signal output from the AND circuit 2 is input to the X-axis display area control circuit 3, and the X@display area control circuit 3 outputs a signal q of the X-axis display area time to the AND circuit 4. Here, the Y-axis display area control circuit 1 and
Since both the X-axis display area control circuits 3 are constituted by variable pull counters, the effective display area on the color liquid crystal panel in the X-axis and Y-axis directions can be set arbitrarily. Next, since the output of the AND circuit 4 is a clock signal in the effective display area, the display data DR, D
G and DB are valid.

The sampling pulse circuit 5 converts the output of the AND circuit 4 into 1
The frequency is divided by 4 to generate a sampling pulse, and a data sampling pulse is generated as a shift clock for the S/P conversion circuit 8.9.10.

The latch pulse generation circuit 6 generates the sampling pulse by 1/
The frequency is divided by 8, and this carry signal is used as the S/P converter circuit 8.
．． 9. Output the latch signal at 10. Furthermore, this latch pulse is applied to l'lr i te address counter 219.
Selection circuit 33. Wr of memory circuit RAM11.12.13
IteDI control signal is input. Therefore, the 8-bit parallel signals of the S/P conversion circuits 8.9.10 are simultaneously stored at predetermined addresses of the storage circuits 11.12.13. Each time data is stored, the write address counter 21 is incremented by a latch pulse from the latch pulse generating circuit 6, and the display data is successively stored at a predetermined address. Next, the read operation will be explained.

When there is no latch pulse output from the latch pulse generation circuit 6, the selection circuit 33 selects the count output of the read address counter 24 and stores the memory circuit RAM11.12.1.
3 is a read operation. Therefore, the memory circuit RAM11.1
2.13 display data is Read address counter 2
4, the P/S conversion circuit 14,
Entered on 15.16. FIG. 2 shows the configuration of the P/S conversion circuits 14, 15, 16, selection gate circuit, and ring counter 22 showing a specific example of the present invention.

In FIG. 2, a switch 45 is a changeover switch that switches the count value of the ring force counter 22 to binary or ternary. Resistor 46 is a pull-down resistor. Memory circuit R
Parallel data of AM11.12.13 is latched into P/S conversion circuit 14.15.16. The ternary count output of the ring counter passes through AND circuits 40, 41, and 42, and becomes the shift clock for the P/S conversion circuits 14, 15.16. , 18 and 19, and then serially transferred to the OR circuit 20. The output of the ring counter is 1/9
Since the input signal is input to the ternary counter 23, one pulse is output every time the output CL1 of the ternary counter is counted by nine. Therefore, when there is no pulse output, AND circuits 40, 41 .
42 is opened and sends a shift clock to the P/S conversion circuit 14.1516, but at the 9th count, the AND circuit 40.
41.42 is closed. Then, the output C of the 1/9 counter
Since L2 is input to the memory circuit RAM11.12.13, the parallel data of the memory circuit RAM11.12.13 is simultaneously output to the P/S conversion circuit 14.15.16. The output CL2 of the 1/9 counter is delayed by the delay circuit 44 and becomes C10. By this C10, the parallel data in the memory circuit RAM11, 12, and 13 is latched into the P/S conversion circuit again as new data.

In this way, since the parallel data in the memory circuit RAM11, 12.13 is 8 bits, each time eight shift clocks are input and the shift operation is completed, new data is input into the period of the ternary ring counter CLI. be transferred. In the above, an example of a ternary ring counter has been described, but when the switch 45 is turned on, the ring counter 22 performs the same operation as described above as a binary ring counter.

In FIG. 1, the output of the OR circuit 20 of the selection gate circuit is serial data in which display data of red, green, blue, red, . . . blue is mixed. This serial data is S/P
The signal is input to the conversion circuit 31. The output frequency-divided by 1/4 by the 1/4 counter 25 is input as a latch of the S/P conversion circuit 31, so the S/P conversion circuit 31
red, green, blue.

red), (green, blue, red, green), (blue, red, green, blue).

(Red, Green, Blue, Red)... Converts display data to parallel.

The shift clock generator 26 delays the output signal of the 1/4 counter 25 in order to supply the display data of the S/P conversion circuit 31 with a shift clock of the 4-bit parallel shift register of the X electrode drive circuit 32. to generate a shift clock.

Further, the latch clock generator 27 is a circuit that generates a latch signal for latching the display data of the 4-bit parallel shift register of the X electrode drive circuit 32.
When the display data on the X-axis electrode is shifted to the end, a latch clock is generated, the display data is latched at the same time, and the X'l poles are driven at the same timing. Furthermore, it becomes a shift clock signal that shifts the display data of the Y-axis electrode and drives the next Y-axis electrode. The frame signal generation circuit 28 is a circuit that generates a frame signal that becomes display data for the Y electrode drive circuit 30, and divides the output of the latch clock generator 27 and outputs data for selecting the first Y-axis electrode. . Further, the frame signal generation circuit 28 generates a reset pulse to clear the output of the read address counter 24 to 0 and set the address of the memory circuit RAM 11.12.13 to address O.

As described above, the present invention can directly replace the red, green, and blue display data of a conventional CRT display with a color liquid crystal panel, and the P/S conversion circuit board selection gate. By adding this, it is possible to handle it in the same way as a conventional monochrome liquid crystal display system configuration. Also, a P/S conversion circuit board selection gate.

The system configuration using the 1/9 counter and the ring counter is logical, and colorization is possible with an extremely simple circuit configuration.

(Effects of the Invention) As described above, according to the present invention, the color display of the liquid crystal can be performed using the interface signal of the CRT display, so the amount of displayed information can be increased, and the TV can be made lighter, thinner, smaller, and wall-mounted. It can be made into an attractive display device such as a flat display terminal. Furthermore, since the same drive circuit can be used for monochrome, there is no need to develop a dedicated color drive circuit, which has great effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing a specific example of a P/S conversion circuit, a selection gate circuit, and a ring counter section. 1... Y-axis display area control circuit 3... X-axis display area control circuit 5... Sampling pulse generation circuit 6... Latch pulse generation circuit 7... Frequency division circuit 8-10...S /P conversion circuits 11 to 13...RAM 17 to 20...Selection gate circuit 21...-rite address counter 22...Ring counter 23...1/9 counter 24...Read address counter 25...1/4 counter 26...Shift clock generator 27...Latch clock generator 28...Frame signal generation circuit 30...Y electrode drive circuit 31...S/P conversion circuit 32... ...X electrode drive circuit 34...color liquid crystal panel

Claims (1)

[Claims] 1) X-axis electrodes and Y-axis electrodes are arranged in a matrix,
A color liquid crystal panel with red, blue, and green filters on the axis electrodes, an X electrode drive circuit that drives the X axis electrode, a Y axis electrode drive circuit that drives the Y axis electrode, and serial display data for red, blue, and green. each S/P conversion circuit for exchanging the data in parallel, each storage circuit for storing the parallel-converted display data, and each P/S conversion circuit for converting the stored parallel display data into serial data. It has an interface circuit configured with a selection gate circuit for selectively outputting the output signal of the P/S conversion circuit, and a second S/P conversion circuit for converting the serial signal of the selection gate circuit into a parallel signal. Color liquid crystal display device. 2) In the color liquid crystal display device according to claim 1, the serial transfer of the P/S conversion circuit is performed in the form of red,
When green and blue are completed, a transfer clock suspension period of the P/S conversion circuit is provided, and new parallel data is transferred.
A color liquid crystal display device having an interface circuit that simultaneously inputs input to the P/S conversion circuit. 3) A color liquid crystal display device having an interface circuit according to claim 1, wherein the control signal for the selection gate circuit is constituted by a ring counter.