JP2617103B2 - Interface circuit for color flat display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit of a flat type color display device such as a liquid crystal display, an EL display, a plasma display, and an LED. The present invention relates to a color display device having an interface circuit which can be replaced with a light, thin and small liquid crystal display device using an interface signal.

[Summary of the Invention]

The present invention uses an interface signal of a CRT display to independently store independent color display data in a RAM, converts the data into read data of a mixture of red, green, and blue at the time of readout, and provides a drive circuit equivalent to a conventional drive circuit. This is an interface circuit that can be configured to perform color display.

[Conventional technology]

Since liquid crystal display devices have characteristics of low profile, low voltage and low power consumption, they have recently been put to practical use as display terminal devices such as personal computers and word processors with large dot matrix panels. Today, as an alternative to CRTs, LSI circuits that can be directly connected to CRT interfaces have been developed as portable personal computers, and each OA equipment developer manufactures interface circuits exclusively for liquid crystal display devices using gate arrays. As a result, there has been a great demand for liquid crystals. However, these liquid crystal display devices are 640 × 200
Although it is necessary to have a display capacity such as a dot in place of a CRT, the amount of display information is insufficient when displaying a graphic because the display is monochrome monochrome. The simple matrix display panel uses one or two of the red, green, and blue color display data to simply display ON and OFF. The charm was not enough.

[Problems to be solved by the invention]

As described above, the interface circuit of the conventional flat-type display device has been less attractive because it has a monochrome display, but in recent years a color liquid crystal display device has been developed and the interface signal of a color CRT is used. It is another object of the present invention to provide an interface circuit applicable to a flat display device capable of performing color display.

[Means for solving the problem]

 Next, a specific example of the present invention will be described.

FIG. 1 is an overall configuration diagram showing the entire color liquid crystal display device of the present invention. In FIG. 1, Hsyc is a horizontal synchronizing signal, Vsyc is a vertical synchronizing signal, and DR, DG, and DB are red, green, and blue display data signals, respectively. CK is a clock signal.

A Y-axis display area control circuit 1 counts the horizontal synchronizing signal Hsyc and determines a display area in the Y-axis direction. The X-axis display area control circuit 3 is a control circuit that counts the clock signal CK and determines a display area in the X-axis direction. The sampling pulse generation circuit 5 is a circuit for dividing the clock signal CK during the display area period to sample and take in data, and the S / P conversion circuits 8, 9, and 10 are for red, green,
Conversion circuits for converting blue serial display data into parallel data, respectively, and RAMs 11, 12, and 13 are storage circuits for storing red, green, and blue parallel data. Latch circuit 1
Reference numerals 4, 15, and 16 denote storage circuits for temporarily storing parallel data of the storage circuits RAM 11, 12, and 13.The write address counter 21 resets the vertical synchronization signal Vsyc, and then stores the storage circuits RAM 11, 12, and 13. , 13 address counting circuit. The latch pulse generation circuit 6 is a circuit for generating a latch pulse every time the sampling pulse of the sampling pulse generation circuit counts 8 and latching the registers of the S / P conversion circuits 8, 9, and 10. Further, the latch pulse of the latch pulse generating circuit 6 becomes a counter input of the write address counter.

The read address counter 24 is a counter circuit for reading addresses of the storage circuits RAM11, RAM12, RAM13. The selection circuit 33 is a selection circuit for switching an address line by writing (Write) or reading (Read) an address of the storage circuits RAM11, RAM12, RAM13. The frequency dividing circuit 7 divides the frequency of the clock signal CK to reduce the frequency. The ring counter 22 is constituted by a hexadecimal counter, and the switch circuits 40 to
A circuit that generates a control signal for switching 46.
The / 8 counter 23 is a circuit that generates a latch signal for latching read data of the storage circuits RAM 11, 12, and 13 and a counter input signal of the read address counter circuit 24. Latch circuits 14, 15, and 16 are circuits for latching read data. The switch circuits 40, 41, 42, 43, 44, 45
A switch circuit for inputting the output signals of 15, 16 so that the red, green, and blue data of the minimum bit are mixed in order and switches every four bits. 1/4 counter 25
Each time four output pulses of the frequency divider 7 are input, 1
A frequency divider that outputs pulses. The shift clock generator 26 is a circuit that generates a shift clock signal SCL of a 4-bit parallel shift register built in the X electrode drive circuit 32. The latch clock generator 27 is a circuit that generates a latch signal LCL for latching data of the X electrode drive circuit 32 and the Y electrode drive circuit 30. The frame signal generation circuit 28 is a circuit that generates a frame signal (data for the Y electrode) FRM to the Y electrode drive circuit 30. AC signal circuit 29
Is a circuit for switching the polarity of the drive signals of the X electrode drive circuit 32 and the Y electrode drive circuit 30 in order to drive the color liquid crystal panel 34 into AC. The color liquid crystal panel 34 is a liquid crystal panel in which red, green, and blue filters are attached to a transparent electrode of the X-axis electrode. The X electrode driving circuit 32 is a circuit for driving the X-axis electrode of the color liquid crystal panel 34. The X electrode drive circuit is Y
This is a circuit for driving the axis electrode. Next, the operation of the present invention will be described.

The Y-axis display area control circuit 1 inputs Hsyc and outputs a signal of the Y-axis effective display area time to the AND circuit 2. The clock signal output from the AND circuit 2 is the X-axis display area control circuit 3
The X-axis display area control circuit 3 outputs a signal of the X-axis effective display area time to the AND circuit 4. Here, since the Y-axis display area control circuit 1 and the X-axis display area control circuit 3 are both constituted by variable counters, the effective display area on the color liquid crystal panel in the X-axis and Y-axis directions is arbitrary. Can be set to Next, since the output of the AND circuit 4 is a clock signal in the effective display area, the display data DR, DG, and DB are valid.

The sampling pulse generation circuit 5 divides the output of the AND circuit 4 by 1/4 to generate a sampling pulse, and generates a data sampling pulse as a shift clock for the S / P conversion circuits 8, 9, and 10. The latch pulse generation circuit 6 reduces the sampling pulse of the sampling pulse generation circuit 5 by 1 /.
After dividing the frequency by 8, latch signals are output to the S / P conversion circuits 8, 9, and 10. (If the display screen is not compressed, the sampling pulse generation circuit may be deleted.) Further, this latch pulse is output from the write address counter 2
1, input to the write control signal of the selection circuit 33 and the storage circuits RAM11, 12, and 13. Therefore, the 8-bit parallel signal of the S / P conversion circuit is sampled at a predetermined address and stored in the storage circuits 11, 12, and 13 at the same time. Each time the data is stored, the write address counter 21 is incremented by the latch pulse of the latch pulse generation circuit 6, and the display data is stored one after another at predetermined addresses.

Next, the read operation will be described. When there is no latch pulse output from the latch pulse generation circuit 6, the selection circuit 33
Selects the count output of the read address counter 24,
The storage circuits RAM 11, 12, and 13 perform a read operation. Therefore, the display data of the storage circuits RAM 11, 12, 13 is addressed by the output of the read address counter 24, and the latch circuits 14, 15, 16
Is input to Display data by the output of the 1/8 reduction counter 23 divided signal C ₁ that a dot clock signal CK is formed by dividing the frequency divider circuit 7 is latched by the latch circuit 14, 15 and 16, ring counter Entered in 22.

The ring counter 22 is constituted by a hexadecimal ring counter as described above, and this output signal is output from a switch circuit.
40 to 45 are time-divisionally switched and the display data of the latch circuits 14 to 16 is output as 4-bit data as color mixture data, and is input to the X electrode drive circuit 32. Therefore, the switch circuits 40 to 45 perform time-division switching (red, green, blue, red), (green, blue, red, green),
(Blue, red, green, blue), (red, green, blue, red) as in the ..., to convert the display data in parallel, and outputs the mixed color display data 0 _{1-0 4} of 4dit parallel.

Shift clock generator 26, a display data 0 _{1-0 4} of the switching circuits 40 to 45, in order to supply the shift clock 4-bit parallel shift register of the X electrode drive circuit 32, the 1/4 of the counter 25 The shift clock is generated by delaying the output signal.

The latch clock generator 27 is a circuit that generates a latch signal for latching display data of the 4-bit parallel shift register of the X electrode drive circuit 32.
When the display data of the axis electrode is shifted to the end,
A latch clock is generated, display data is simultaneously latched, and X electrodes are driven at the same timing. Further, a shift clock signal for driving the next Y-axis electrode by shifting the display data of the Y-axis electrode is obtained. The frame signal generation circuit 28 is a circuit for generating a frame signal serving as display data of the Y electrode driving circuit 28. The frame signal generation circuit 28 divides the output of the latch clock generator 27 and outputs display data for selecting the first Y-axis electrode. I do. Further, the frame signal generating circuit 28 clears the output of the read address counter 24 to 0, and generates a reset pulse for setting the addresses of the memory circuits RAM11, 12, 13 to 0.

FIG. 2 shows a panel electrode configuration diagram of a color liquid crystal panel used in the present invention. In FIG.
Y ₁ , Y ₂ ,..., Y _n are a group of Y electrodes of a color liquid crystal panel.
R ₁ , G ₁ , B ₁ , R ₂ ,..., R _n , G _n , B _n are a group of X electrodes to which a color filter is attached in the order of red, green, blue, red,. The intersection of the electrode group and the X electrode group is a color display dot.

FIG. 3 is a timing chart of an interface signal to the liquid crystal drive circuit. In FIG. 3, 0 ₁
~ _{0. 4} is a mixed color display data of the switch circuits 40 to 45.
SCL is a shift clock of a 4-bit parallel shift register built in the X electrode drive circuit 32. LCL
The symbol は denotes a latch signal of a latch circuit built in the X electrode drive circuit 32 and a shift clock of a shift register built in the Y electrode drive circuit 30. FRM is scanning start data for starting scanning of the Y electrode drive circuit 30, and is generated by the frame signal generation circuit 28 in FIG. FRM is a carry signal obtained by dividing LCL by 1 / N.

M is a signal obtained by dividing the frequency of the FRM signal by 1/2, and is an output signal of the AC signal generation circuit shown in FIG.

〔The invention's effect〕

As described above, in the present invention, color display of liquid crystal can be easily performed using an interface signal of a CRT display, so that an amount of display information is increased and an attractive display device can be obtained. In addition, since the same driving circuit as that for monochrome can be used, a great effect is obtained such that it is not necessary to develop a driving circuit dedicated to color.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG.
FIG. 3 shows an example of an electrode structure of a color liquid crystal panel.
FIG. 5 is a timing chart of a liquid crystal drive circuit interface signal. 1 Y-axis display area control circuit 3 X-axis display area control circuit 8, 9, 10 S / P conversion circuit 11, 12, 13 Memory circuit RAM 14, 15, 16 Latch circuit 21 ... Write address counter 24 ... Read address counter 30 ... Y electrode drive circuit 32 ... X electrode drive circuit 33 ... selection circuit 34 ... color liquid crystal panels 40,41,42,43,44,45 switches circuit

Claims (1)

(57) [Claims] An X-axis electrode and a Y-axis electrode are arranged in a matrix, a color liquid crystal panel having red, green and blue filters formed on the X-axis electrode, an X-electrode drive circuit for driving the X-axis electrode, and a Y-electrode. Y-electrode drive circuit to drive the axis electrode, each S / P to convert red, green and blue serial display data into parallel
Conversion means and respective storage circuits for storing the parallel-converted display data, and a plurality of switch circuits for converting the stored display data of each storage circuit into mixed display data of red, green and blue An interface circuit for a color flat display device, which outputs display data to an X-electrode drive circuit via mixed display data generating means comprising: