JP2512297B2 - Color liquid crystal display device interface circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color liquid crystal display device, and in particular, it utilizes a CRT display device interface signal that is widely used in color televisions, color graphic display terminals, etc. The present invention relates to a color liquid crystal display device having a video interface circuit which can be substituted for a short and small liquid crystal display device.

[Outline of Invention]

The present invention is an interface circuit for causing a color liquid crystal display device to display a video by using an interface signal of a color CRT display.
The blue video signal is sent to the upper side by the switching means and the two systems of data shift and shift clock means.
The video signal is time-divisionally separated and transferred to the lower X-electrode drive circuit and driven from the upper and lower sides of the color liquid crystal panel.

[Conventional technology]

Since the liquid crystal display device has the features of thinness, low voltage, and low power consumption, it has recently been put to practical use as a display terminal device such as a personal computer and a word processor by using a large dot matrix panel. However, these liquid crystal display devices have
Although it has a display capacity to replace the CRT, it is insufficient as the amount of display information in the case of graphic display because it is monochrome monochromatic display. Since the ON / OFF display is simply performed by using one or two of the color display data of the CRT, the display device is less attractive than the CRT.

[Problems to be solved by the invention]

As described above, the conventional liquid crystal display device is not attractive because it is a monochrome display, but with the development of a color display panel in recent years, the interface signal of the color CRT was used to provide gradation. The present invention aims to provide an attractive color display terminal by providing a circuit for color video display. Further, in the conventional color liquid crystal display device, the connection work between the X electrode drive circuit and the X electrode terminal of the display panel tends to be extremely difficult because the pitch of the connection terminals is small. This is red compared to the conventional monochrome display
Since it is necessary to transfer the green and blue display data, the X electrode interval is 1/3 when comparing the same display area.
This problem is simply understood because it becomes narrower. According to the present invention, the connection pitch interval between the X electrode terminal and the X electrode drive circuit is not simply 1/3, but the X electrode drive circuit is separated into two systems like the upper and lower electrodes. The purpose is to eliminate the difficulty of connection.

[Means and Examples for Solving Problems]

 Next, specific examples of the present invention will be described.

FIG. 1 shows an interface circuit of the color liquid crystal display device of the present invention. In FIG. 1, H _syc is a horizontal synchronizing signal, V _syc is a vertical synchronizing signal, and RD, GD, and BD are red, green, and blue video display data signals, respectively. CK is a clock signal. The Y-axis display area control circuit 2 is a control circuit that counts the horizontal synchronizing signal H _syc and determines the display area in the Y-axis direction. The X-axis display area control circuit 4 is a control circuit that counts the clock signal CK and determines the display area in the X-axis direction. The D-type flip-flop (hereinafter referred to as D-type F / F) 6 and the NOR circuit 12 are circuits that generate a data hold signal HP for holding data to the segment driver. D type F / F circuit 1 and NOR circuit 13 and F / F
The circuit 14 is a circuit for generating the frame signal FRM. The F / F circuit 15 is a circuit that generates a drive signal polarity inversion control signal DF for AC driving the liquid crystal. FF circuit 7
Is a circuit for dividing the effective horizontal dot signal φ ₂ . D type F
The F circuit 8 and the NOR circuit 10 are circuits that generate a shift clock USK for transferring the data UST to the shift register of the upper segment driver. D-type F / F circuit 9 and NOR circuit 11
Is the data in the shift register of the lower segment driver
A circuit that generates a shift clock LSK for transferring LST. D type F / F circuit 23 and NOR circuit 24 are F / F circuits 25 and 26.
Circuit for generating the set signal φ ₅ in the set / reset circuit of. The delay circuits 27 and 28 are the data shift clock US
A circuit that delays K and LSK and generates a reset signal to the F / F circuits 25 and 26. Transmission gates 16 and 19,17 and 20,18 and
21 is for alternately distributing the red, green and blue video signals to the upper segment driver red, green and blue UR, UG and UB and the lower segment driver red, green and blue LR, LG and LB. Switching circuit. The configuration is as described above.

Next, the operation of FIG. 1 will be described. FIG. 2 shows the timing diagram of FIG. In FIG. 1, a Y-axis display area control circuit 2 is a circuit that sets an effective display period in the Y-axis direction, a counter circuit that counts a vertical blanking period after the vertical synchronization signal V _syc is input, and A counter circuit for counting the horizontal synchronizing signal in the effective display area period is built in. The horizontal synchronizing signal H _syc is input to the Y-axis display area control circuit 2 as a clock input. As the output T ₁ of the Y-axis display area control circuit 2 shown in FIG. 2, the period of the effective display area of the Y-axis direction, the "H" level of the output signal. Therefore, the output φ ₁ of the AND circuit 3 is Y
The horizontal synchronizing signal H _syc during the period of the effective display area in the axial direction is _set to X
Input to the axis display area control circuit 4. The X-axis display area control circuit 4 has the same configuration as the Y-axis display area control circuit 2 described above, and includes a counter circuit that counts the horizontal blanking period after the horizontal synchronizing signal H _syc is input, and a dot. There is a built-in counter circuit that counts the clock CK. The dot clock CK is input as the clock input. The output of the X-axis display area control circuit 4 T _2, as shown in FIG. 2, the period "H" level of the output signal of the effective display area of the X-axis direction. Therefore, the AND circuit 5 outputs the dot clock signal φ ₂ within the effective display area. Red, green and blue video signals RD, GD and BD are transmitted through transmission gate 16
And the upper side video signal data UK, UG, UB and the lower side LR, LG, LB by the switch circuit constituted by 19,17 and 20,18 and 21.
Are selectively distributed to the upper and lower segment drivers. The transmission gate
The selection control of 16 to 21 is controlled by the dot clock signal φ ₂ .
The output signal φ ₆ divided by 1/2 is used for distribution. D type F
The F circuit 8 and the NOR circuit 10 generate the shift clock USK at the falling edge of the Q output of the F / F circuit 7 and serve as the shift clock of the shift register built in the upper segment driver. The shift clock LSK is generated at the falling edge of the output of the D-type F / F circuit 7, and becomes the shift clock of the shift register built in the lower segment driver.

The D-type F / F circuit 23 and the NOR circuit 24 generate a set pulse φ ₅ for setting shift data at the rising edge of φ ₁ , and set the F / F circuits 25 and 26 to the "H" level. F ・
Since the F circuits 25 and 26 are reset by the first one of the shift clock USK of the upper segment driver and the shift clock LST of the lower segment driver, the outputs LSK and LST of the F / F circuits 25 and 26 are reset. Are data of the shift registers of the upper and lower segment drivers. The D type F / F circuit 1 and the NOR circuit 13 are
When the output T ₁ of the axis display area control circuit 2 rises, a set pulse signal φ ₃ is generated to set the FF circuit 14.
The D-type F / F circuit 6 and the NOR circuit 12 have a data hold pulse at the falling edge of the output T ₂ of the X-axis display area control circuit.
Generates HP and holds data for the upper and lower segment drivers. Further, after being delayed by the delay circuit 30, it is added as a reset signal of the F / F circuit 14,
・ Reset the F circuit 14. Therefore, the output of the F / F circuit 14
The FRM becomes scan start data of the shift register of the common driver as a frame signal for starting scan. F ・
The F circuit 15 divides the frequency of the FRM signal, inputs a polarity inversion signal DF that inverts the polarity of the drive voltage to the upper and lower segment drivers and the common driver, and switches the polarity for each frame.

FIG. 3 shows an overall configuration diagram of a color graphic liquid crystal display device using the interface circuit according to the present invention. In FIG. 3, 42 is an upper segment driver, 43 is a lower segment driver, 41 is a common driver, and 60 is a color liquid crystal display panel. The upper and lower segment drivers 42, 43 are shift registers 44, 52, switching circuits 45, 46, 50, 51, waveform switching circuit.
It is composed of 48, 53 and data hold circuits 47, 49. X-axis electrodes R ₁ , G ₁ , B _{1 to} R ₄ , G ₄ , of the color liquid crystal panel 60
B ₄ is connected to the upper and lower segment drivers,
Driven from above and below. The shift data UST and LST of the shift registers 44 and 52 are shifted by the shift clocks USK and LSK. The outputs Q _{1 to} Q ₄ of the shift registers 44, 52 are sequentially controlled by the switching circuits 45, 50, 46, 51 to sample and hold the data, and then the data hold signal HP causes the data hold circuit 47 to perform one horizontal scan. The analog voltage of the line is held and the X electrodes R ₁ , G ₁ , B _{1 to} R ₄ , G ₄ , B ₄ are driven. The common driver 41 receives the frame signal FRM as frame start data,
Line sequential scanning is performed by HP. The waveform switching circuits 48 and 53 are controlled so as to switch the polarity of the analog voltage according to the polarity of the polarity switching signal DF, and perform AC drive.

〔The invention's effect〕

As described above, according to the present invention, the color video signal and the interface signal of the CRT are used to directly display the video signal on the color liquid crystal display device. The interface circuit can be simplified without requiring a circuit and can be manufactured at low cost. Further, as a side effect of the present invention, since the color video signal is vertically distributed and transferred, there is also an effect that the connection pitch between the X electrodes of the color liquid crystal panel and the drive circuit can be increased. Also, since the data transfer clock frequency can be reduced to 1/2, I
C price can be reduced. Further, by laying out the drive circuit on the upper side and the lower side, pattern design and mounting around the drive circuit can be facilitated. Conventionally, a large-scale liquid crystal display device which has been used only for OA equipment such as a personal computer or a word processor for monochrome / monochrome display and ON / OFF display, by using the interface circuit of the present invention, a computer graphic display, or It has a great effect such that it can be widely used as a substitute for a multicolor halftone display such as a wall-mounted television and a video display terminal device.

[Brief description of drawings]

FIG. 1 is an interface circuit diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing the timing in FIG.
FIG. 3 is an overall configuration diagram showing an embodiment of a color liquid crystal display device using the interface circuit of the present invention. 2 …… Y-axis display area control circuit 4 …… X-axis display area control circuit 1,6,8,9,23,25,26 …… D type F / F circuit 16,17,18,19,20,21 ...... Transmission gate circuit 40 …… Interface circuit 41 …… Common driver 42 …… Upper segment driver 43 …… Lower segment driver 44,52 …… Shift register 45,46 …… Switching circuit 44,49 …… Data hold circuit

Claims (1)

(57) [Claims] 1. A color liquid crystal panel in which X-axis electrodes and Y-axis electrodes are arranged in a matrix, and the X-axis electrodes display red, green, and blue colors, and two systems of segments for driving the X-axis electrodes. An interface circuit of a color liquid crystal display device for driving a liquid crystal device including a driver and a common driver for driving the Y-axis electrode, wherein a horizontal synchronizing signal, a vertical synchronizing signal and a dot clock signal (CK) are input, From the display area control means (2 to 5) for outputting the effective horizontal dot signal (Φ ₂ ) corresponding to the effective display area of the color liquid crystal panel, the effective horizontal dot signal (Φ ₂ ) and the dot clock signal (CK) Shift clock generating means (7 to 11) for generating two shift clock signals (USK, LSK) to be output to the two segment drivers, and the effective horizontal dot Signal ([Phi ₂₎ frequency divider which enter and outputs a 1/2 frequency-divided signal of the (7), red, green, enter a video display data signal corresponding to the blue, each color video display A color liquid crystal display device comprising a switching circuit (16 to 21) for distributing and outputting a data signal to the two-system segment driver in synchronization with the output signal of the frequency dividing circuit (7). Interface circuit.