JPH02242224A - Matrix display device - Google Patents

Abstract

PURPOSE:To lower the action frequency of a data driver and to accomplish the matrix display of large capacity by pairing two display elements and alternately driving odd numbered and even numbered scanning buses every one frame in the case of writing. CONSTITUTION:The display element 7a and 7b adjacently arranged in the extension direction of the scanning bus 1 are paired and the terminals for writing the data of respective switching elements 6 are connected to the same data bus 2 and the terminals for on/off are respectively connected to the odd numbered scanning bus I0 and the even numbered scanning bus Ie. In the case of writing, a scanning driver 4 which drives the scanning bus 1 and the data driver 5 which drives the data bus 2 are made to execute jump driving for writing the data alternately in the odd numbered scanning bus and the even numbered scanning bus every one frame with a signal from a control means 3 and one screen is constituted of two frames.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a matrix IJ display device that performs 2:1 interlaced scanning, and provides a device that can display a large capacity by reducing the number of elements in the bus driver of the matrix display device. In a matrix display device that includes a scanning bus and a data bus arranged orthogonally to each other, and a display element is provided at the intersection thereof via a switching element, the matrix display device is arranged adjacent to the scanning bus in the extending direction. The data writing terminals of each switching element are connected to the same data bus, the on/off terminals are connected to an odd-numbered scanning bus and an even-numbered scanning bus, respectively, and the control means The scan driver that drives the scan bus and the data driver that drives the data bus are caused to perform interlaced scanning driving in which data is written alternately to odd-numbered scan buses and even-numbered scan buses every frame. Configure.

[Industrial application field]

The present invention relates to a matrix display device, and particularly to a matrix display device suitable for large-capacity display.

In recent years, large monochrome liquid crystal displays and plasma displays have been put into practical use in portable word processors and laptop-type personal computers.
The number of dots has reached 640 x 400, and the development of large-sized liquid crystal display devices capable of color display is progressing. In order to increase the capacity of display devices, there is a demand for matrix display devices that are large in size, have a low operating frequency, have a simple operating circuit configuration, and are inexpensive.

[Conventional technology]

FIG. 7 shows an example of the configuration of a conventional monochrome matrix display device (liquid crystal display device).

The liquid crystal display device in this figure includes a liquid crystal panel 70, which is composed of a first substrate 73 and a second substrate 79 with a liquid crystal 78 sealed between them.

A scan bus 71 and a data bus 72 are provided to intersect with each other on the first substrate 73, and near the intersection, the gate is connected to the scan bus 71, the drain is connected to the data bus 72, and the source is connected to the electrode 7.
There are thin film transistors (TPTs) 76 which are connected switching elements, and a second substrate 79 is provided with a counter electrode (not shown). In addition, the liquid crystal panel 73
Externally, there are a scan driver 74 and a data driver 75,
and its control circuit (not shown). In such a liquid crystal display device, the scan driver 74
Select lines in order and press T P T76 on that line.
data driver 7 every time you select one line.
T P T with the data voltage corresponding to the display turned on from 5
76 to the liquid crystal 78. Then, data is written to the pixel at the intersection of the selected scanning line and data line. Then, when sequential scanning lines are selected and writing of all lines is completed, one screen is displayed.

The data driver 75 in FIG. 7 has a configuration as shown in FIG. 8. The data driver 75 shifts the serially sent display data D using a shift register 81 based on the clock signal CK, takes in display data for one line, converts the voltage level using a level conversion circuit 82, and then converts the display data D into each row using a shift register 81 based on the clock signal CK. One row of data is simultaneously applied to the data bus.

This allows one line to be written at the same time.

[Problem to be solved by the invention]

Generally, in a display device such as a CRT, it is necessary to rewrite one screen with 40 to 607 in order to prevent flickering. For this purpose, as shown in FIGS. 9(a) to (C),
The operating time required for 1 horizontal opening signal is 320 x 2
65μ51640 for a liquid crystal panel with a size of 00 dots
40μ51 for an LCD panel of about X400 dots
1120 x 750 For a dot-sized LCD panel, 3
The number of dots (line number) in the scanning direction, such as 0 μs.
As the display capacity increases, the display data transfer speed becomes faster as the display capacity increases.

There is a problem in that the dot clock in a liquid crystal panel of about 1000 x 800 dots reaches as high as 50 MHz, which exceeds the capability of the data driver.

In other words, as the capacity of the liquid crystal panel increases, the conventional single C
MO8 ICs no longer work, and the number of ICs must be increased, resulting in an increase in the number of parts and power consumption, making it difficult to realize large-capacity display devices. be.

The present invention was made in order to solve the above-mentioned problems in matrix display devices, and an object of the present invention is to reduce the number of data drivers and lower the operating frequency of the data drivers, and to provide a large-capacity matrix display device. It is said that

[Means to solve the problem]

The structure of a matrix display device of the present invention that achieves the above object is shown in FIG. The matrix display device in the figure includes a scanning bus and a data bus arranged orthogonally,
In an IJ display device in which a display element is provided at the intersection via a switching element, two display elements 7a and 7b arranged adjacent to each other in the extending direction of the scanning bus 1 are set as a set, and each switching element 6 The data writing terminals of 1 and 2 are connected to the same data bus 2, and the on/off terminals are connected to the odd-numbered scanning bus 1o and the even-numbered scanning bus 1e, respectively, and the scanning bus 1 is driven by a signal from the control means 3. The scanning driver 4 that drives the data bus 2 and the data driver 5 that drives the data bus 2 are configured to perform interlaced scanning driving in which data is written alternately to odd-numbered scanning buses and even-numbered scanning buses every frame. There is.

[For production]

According to the matrix display device of the present invention, two adjacent dots arranged in one display line are connected to a common data bus and odd-numbered and even-numbered scanning buses, respectively, so that scanning in each frame is Either the odd-numbered bus or the even-numbered bus is performed alternately, and 1
During the horizontal scanning period, only half of the dots of one display line are written, and two frames constitute one screen.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

2 to 1 show the structure of an embodiment of the matrix display device of the present invention. A scanning bus Sot is arranged orthogonally on one substrate of the liquid crystal panel 20.

SB+, SOz, SB2. ...””SOm, SBm
Tochi-9 Lotus X1. There are X2゜...X9, odd-numbered scanning buses SOI, SO2゜...
・SO, is connected to the first scan driver 21, and even-numbered scan buses SR,,SB,...SR, are connected to the second scan driver 21.
are connected to the scan driver 22 and have data buses XI, X2 .
. . . Xh is connected to the data driver 23. Scan buses SQ, SB, SO2, Se2. −・
...SQ, SB, and data bus xI.

X2. A pixel electrode is provided near the intersection with (not shown) constitutes each pixel. Odd-numbered liquid crystal cells 24a and even-numbered liquid crystal cells 24b, which are arranged adjacent to each other in the extending direction of the scan bus, are made into a set of two, and Ts connected to the liquid crystal cells 24a and 24b, respectively, are arranged in pairs. P T2
5 are connected to the same data bus, and their gates are connected to the odd-numbered scan bus SOi and the even-numbered scan bus St!
i (i is a natural number).

The first scan driver 2L, the second scan driver 22 and the data driver 23 are connected to a control circuit 26 into which a horizontal synchronization signal and a vertical synchronization signal are input, and this control circuit 26
A scan driver control signal is output to the first scan driver 21 and the second scan driver 22, and a data driver control signal is output to the data driver 23. In addition, the control circuit 26
The output control signal 01E is outputted to the first scanning driver 21 and the clock frequency division selection circuit 27 into which the clock signal is input, and this output control signal 01E is inverted by the inverter 29 and also sent to the second scanning driver 22. Output. Display data Din to be displayed on the liquid crystal panel 20 is input to the data driver 23 via the flip-flop circuit 28. Further, the output of the clock frequency division selection circuit 27 is input to the flip-flop circuit 28 and the data driver 23.

Next, the operation of the apparatus of the embodiment configured as above will be explained using the waveform diagram of FIG. 3-1.

The first scan driver 21 and the second scan driver 22, which scan even-numbered lines and odd-numbered lines, are controlled by an output control signal OB, and are controlled by a control circuit 26 so as to sequentially scan one line at a time like a normal scan driver. controlled by The control circuit 26 generates normal control signals to the first scan driver 21 and the second scan driver 22, and
As shown in FIG. 3(C), the vertical synchronizing signal is frequency-divided by two to generate an output control signal DE, which is sent to the first scanning driver 21.
At the same time, this output control signal OB is inverted by an inverter 29 and is input to the second scanning driver 22. In this embodiment, the first scan driver 21 is configured to output a scan signal when this output control signal 0ε is at a high level, and the second scan driver 22 is configured to output a scan signal when this output control signal OB is at a low level. If so, the control circuit 26 causes the first scanning driver 21 to output a scanning signal during odd frames, and causes the second scanning driver 22 to output a scanning signal during even frames.

As shown in FIG. 3-1(a), the clock frequency division selection circuit 27 divides the clock signal to generate a signal CLKI and a signal CL which sample even and odd display data. The clock frequency division selection circuit 27 receives, for example, an output control signal O input from the control circuit 26.
It is configured to output the signal CLKI when the output control signal B is at the high level 1o, and output the signal CLK2 when the output control signal OE is at the low level 00.

Display data Di input manually to the flip-flop circuit 28
As shown in FIG. 3, n is latched by the flip-flop circuit 28 at the rising edge of the signal CLKI or the signal CLK2. Therefore, flip-flop circuit 2
When the signal CLKI is input to the flip-flop circuit 28, the data of the odd columns of one display line is inputted to the data driver 23 as the display data Dout, and when the signal CLK2 is input to the flip-flop circuit 28, the data of the even columns of one display line is inputted to the data driver 23 as the display data Dout. The data is manually input to the data driver 23 as display data DOtlt.

In the display data Din input in this way, only the odd-numbered data in the odd-numbered frame is the display data Do.
ut to the data driver 23, and at this time the first
The scan driver 21 connects the odd-numbered scan bus SDI, SO
□,...SO,,l is scanned to display the display data Di
Half of the data of n is written into the liquid crystal cell 24a.

Similarly, in even frames, display data Di
Only n even-numbered data is sent to the data driver 23 as display data Dout, and at this time, the second scan driver 22 transfers the even-numbered scan buses 3B, , SE2 .・・・・・・
...SE is scanned, and the remaining half of the display data Din is written into the liquid crystal cell 24b. FIG. 4-1 shows the operation of odd-numbered frames in the apparatus shown in FIG. No signal is output.

Therefore, data is written to every other liquid crystal cell 24a as shown by diagonal lines among the liquid crystal cells lined up in one display line.
In even frames, data is written to liquid crystal cells 24b that are not shaded.

In the embodiments described above, the display panel and peripheral circuits are provided so as to write even and odd data of the display data for each frame, but even and odd data may be written for each line.

Examples in this case are shown in FIGS. 2-2 to 4-2.

2-2 differs in two points: (1) the method of connecting the liquid crystal panel 20 and the first and second scan drivers 21 and 22, and (2) controlling the clock frequency division selection circuit 27 by the signal SEL.

As shown in FIG. 3-2, the signal SBL is a signal that is inverted every time one scanning line is selected, and its polarity is inverted in odd and even frames. The clock frequency division selection circuit 27 receives the signal SE
When L is high level 1, signal CLKI is selected and signal S
When EL is at low level 0, signal CLK2 is selected. FIG. 4-2 shows the operation of odd-numbered frames in FIG. 2-2, and as in the previous embodiment, the first scanning driver 2
The scanning signals are sequentially output from SE2.1, but because the connection with the panel is different, SQL, SE2. SO3...
Scanning is performed as shown in the figure, and at the same time, odd and even display data is sent line by line to the data driver 23 by the signal SEL, and the data is written into the liquid crystal cells indicated by diagonal lines.

In even frames, data is written to liquid crystal cells that are not shaded.

FIG. 5 shows a configuration example of a liquid crystal panel according to yet another embodiment of the present invention, and this example is an example in which the present invention is applied to a color matrix display device.

In a color display device, RGB dots constituting the three primary colors are arranged in the line direction, and the gates of TFT51 of each dot are connected to the upper and lower scanning buses SO and S every other dot.
H and write half the pixels in one frame as in the previous embodiment.

Furthermore, in the embodiment shown in FIG. 6, the three primary color display elements RG
B is arranged in the scanning direction so that three dots in the scanning direction constitute a single color pixel, and the number of scanning buses is set to the scanning bus SRO for red odd frames.

Scan bus SRE for red even frames, scan bus SGO for green odd frames, scan bus SGE for green even frames, scan bus SH for odd frames blue.
O, 3 like scan bus SBE for blue even frames
It's doubling. In the device of this embodiment, half of the data for one color is written in one frame, and all the data for one screen is written in six frames. That is, in the first frame, data is written to the red odd-numbered dots shown in Figure 6, and in the second frame, data is written to the green odd-numbered dots shown in the third frame. One screen is constructed by writing data to the dots, ■ dots in the fourth frame, ■ dots in the fifth frame, and ■ dots in the sixth frame. In this case, the number of data drivers can be reduced to 1/6 compared to the normal case.

〔Effect of the invention〕

As explained above, according to the present invention, the number of scan drivers is doubled, but since the scan driver has a simple configuration,
When the display capacity is large or when displaying in color, the operation speed of the data driver is halved, which does not cause problems with operation speed, and it is also possible to realize a matrix display device without increasing the number of drivers for monochrome and color displays. Therefore, the device configuration is simplified and the cost is reduced.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle configuration of a matrix display device of the present invention, Fig. 2-1 is an overall block diagram of an embodiment of a matrix display device of the present invention, and Fig. 2-2 is Fig. 2-1. FIG. 3-1 is an operating waveform diagram of the device in FIG. 2-1, FIG. 3-2 is an operating waveform diagram of the device in FIG. 2-2, and FIG.
Figure-1 is a diagram showing the operation of the liquid crystal panel in Figure 2-1, and Figure 4
Figure-2 is a diagram showing the operation of the liquid crystal panel in Figure 2-2, and Figure 5.
6 is a block diagram of still another embodiment of the present invention, FIG. 7 is a block diagram of a conventional monochrome matrix display device, and FIG. 8 is a block diagram of a conventional monochrome matrix display device. FIG. 7 is a configuration diagram of the data driver, and FIG. 9 is an explanatory diagram showing changes in data transfer speed as the display capacity increases. 1...Scanning bus, IO...Odd numbered scanning bus, 1
e... Even-numbered scan bus, 2... Data bus, 3
...Control circuit, 4...Scan driver, 5...Data driver, 6...Switching element, 7a, 7b
. . . Liquid crystal cello 20 . . . Liquid crystal panel, 21 . . . First scanning driver, 22 . . . Second scanning driver, 23.
...Data driver, 24.24a, 25b...Liquid crystal Senope 25...TFT, 26...Control circuit, 27
...Clock frequency division selection circuit, 28...Flip-flop circuit.

Claims (1)

[Claims] In a matrix display device including a scan bus and a data bus arranged orthogonally to each other and a display element provided at the intersection thereof via a switching element, the display element is arranged adjacent to the scanning bus (1) in the extending direction. (7a, 7b) as a set, the data write terminals of each switching element (6) are connected to the same data bus (2), and the on/off terminals are connected to the odd-numbered scanning bus (1o) and the even-numbered scanning bus (1o), respectively. a scan driver (4) that drives the scan bus (1) and a data driver (5) that drives the data bus (2) according to a signal from the control means (3). 1
A matrix display device characterized in that interlaced scanning driving is performed in which data is written alternately to odd-numbered scanning buses and even-numbered scanning buses for each frame.