JP2002366057A - Display device - Google Patents

Display device

Info

Publication number
JP2002366057A
JP2002366057A JP2001175614A JP2001175614A JP2002366057A JP 2002366057 A JP2002366057 A JP 2002366057A JP 2001175614 A JP2001175614 A JP 2001175614A JP 2001175614 A JP2001175614 A JP 2001175614A JP 2002366057 A JP2002366057 A JP 2002366057A
Authority
JP
Japan
Prior art keywords
pixel
display device
semiconductor layer
formed
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001175614A
Other languages
Japanese (ja)
Inventor
Yoshiaki Aoki
良朗 青木
Original Assignee
Toshiba Corp
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, 株式会社東芝 filed Critical Toshiba Corp
Priority to JP2001175614A priority Critical patent/JP2002366057A/en
Publication of JP2002366057A publication Critical patent/JP2002366057A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a display device of which the display quality can be improved by spatially dispersing periodical display irregularity. SOLUTION: The display device having a display area composed of a plurality of pixels arranged in a matrix is equipped with at least one TFT(thin film transistor) 121 containing a polysilicon semiconductor layer 112 in each pixel to switch the pixel. The polysilicon semiconductor layer 112 of the TFT 121 has a source region S connected to a signal line X and has a drain region D connected to a pixel electrode 151. The display area is equipped with switching elements having the position of the source region S and the drain region D different from one another.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a display device, and more particularly to an active matrix type display device having at least one switching element for each pixel.

[0002]

2. Description of the Related Art In recent years, a thin film transistor having a polysilicon semiconductor layer as a switching element, that is, a TFT
Has been developed for each pixel. This polysilicon semiconductor layer first has C
It is formed by forming an amorphous silicon film by a VD method or the like, annealing the film by irradiating an excimer laser beam, and then patterning it into an island shape having a predetermined shape. Thereafter, a source region and a drain region are formed in the semiconductor layer by implanting impurities into the polysilicon semiconductor layer as necessary.

However, in such a TFT, there is a possibility that periodic characteristic unevenness may occur due to the manufacturing process of the array substrate.

For example, in a polysilicon semiconductor layer formed by excimer laser annealing, the characteristics of the film periodically change depending on the scanning direction of the excimer laser beam. For this reason, when a TFT is formed with such a polysilicon semiconductor layer, particularly, the direction from the source to the drain of the TFT is “whether arranged perpendicular or parallel to the scanning direction” or “in the traveling direction of the scanning direction”. Along or vice versa "
, The TFT characteristics are greatly affected.

For this reason, when the TFT having the above-described structure is applied to an active matrix display device, there is a possibility that periodic display unevenness occurs in the scanning direction of the excimer laser beam.

[0006]

As described above, in the conventional active matrix type display device having a TFT having a polysilicon semiconductor layer for each pixel, the periodicity of the TFT characteristic generated due to the manufacturing process is reduced. The unevenness may appear as periodic display unevenness during screen display.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to provide a display device capable of improving display quality by spatially dispersing periodic display unevenness. It is in.

[0008]

According to a first aspect of the present invention, there is provided a display device having a plurality of pixels arranged in a matrix, wherein each of the pixels comprises a thin film transistor. A plurality of switching elements, wherein the directions of the source region and the drain region of the switching elements are different.

A second aspect of the present invention includes a plurality of pixels arranged in a matrix, a signal line arranged corresponding to each column of the pixels, and a scanning line arranged corresponding to each row of the pixels.
Wherein each of the pixels includes at least one thin film transistor including an island-shaped semiconductor layer, and a gate electrode which is disposed on the semiconductor layer via a gate insulating film and connected to a corresponding scan line. Comprising, the semiconductor layer of the thin film transistor contains a predetermined concentration of impurities,
It has a source region connected to the corresponding signal line and a drain region connected to the corresponding display element, and the arrangement positions of the source region and the drain region of the thin film transistor are different for each of a predetermined number of pixels. It is characterized by being arranged in.

According to a seventh aspect of the present invention, there is provided a display device having a display area including a plurality of pixels arranged in a matrix, comprising at least one switching element arranged for each pixel and switching a pixel. A first connection unit connected to the drive source;
A second connection unit connected to a pixel, wherein the display area includes a switching element in which the arrangement position of the first connection unit and the second connection unit is different from each other in a column direction of the display area. Features.

According to another aspect of the present invention, there are provided a plurality of signal lines, a plurality of scanning lines arranged substantially orthogonal to the signal lines, a switching element arranged near the intersection thereof, and a display connected to the switching element. And a switching device, wherein the switching element is an island-shaped semiconductor layer and a gate disposed on the semiconductor layer via a gate insulating film and connected to a corresponding scanning line. An electrode, the semiconductor layer of the thin film transistor includes a predetermined concentration of impurities, a source region connected to the corresponding signal line, and a drain region connected to the corresponding display element, Wherein the switching elements are arranged such that arrangement positions of the source region and the drain region are different for each predetermined number in the signal line direction. Wherein the placed.

According to a nineteenth aspect, in the display device provided with a display area including a plurality of pixels arranged in a matrix, each of the pixels is connected to a pixel switching element for selecting the pixel and the pixel switching element. A driving element, and a display element driven by the driving element, wherein the driving element is formed of a thin film transistor, and a direction of a source region and a drain region of the thin film transistor is different in the display area. I do.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the display device according to the present invention will be described below with reference to the drawings.

(First Embodiment) First, an embodiment of an active matrix type liquid crystal display device will be described as a display device of the present invention.

(Embodiment 1) As shown in FIG. 1, an active matrix type liquid crystal display device 10 has an array substrate 100.
And an opposing substrate 2 disposed opposite to the array substrate 100.
00 and a liquid crystal composition 300 disposed between the array substrate 100 and the counter substrate 200. In such a liquid crystal display device 10, a display area 102 for displaying an image is formed from a plurality of pixels arranged in a matrix in a region surrounded by an outer edge seal member 106 for bonding the array substrate 100 and the counter substrate 200. ing. The peripheral area 104 where the driving circuit and the like are arranged is formed outside the outer edge seal member 106 and in a region other than the display area.

In the display area 102, the array substrate 1
1, reference numeral 00 denotes m × n pixel electrodes 151 arranged in a matrix, m scanning lines Y formed along the row direction of these pixel electrodes 151, and N signal lines X formed along the column direction,
m × n thin film transistors, ie, pixel TFTs 1, disposed as switching elements near the intersections of the scanning lines Y and the signal lines X corresponding to the m × n pixel electrodes 151.
21. The pixel TFT 121 is formed by an n-channel thin film transistor. This thin film transistor is, for example, a top gate thin film transistor using a polysilicon thin film as an active layer.

In the peripheral area 104, the array substrate 100 includes a scanning line driving circuit 1 for driving the scanning lines Y.
8, a signal line driving circuit 19 for driving the signal line X, and the like. The scanning line driving circuit 18 and the signal line driving circuit 1
Reference numeral 9 denotes a complementary circuit including an n-channel thin film transistor and a p-channel thin film transistor. These thin film transistors are, for example, top gate thin film transistors using a polysilicon thin film as an active layer, and are formed on the insulating substrate 11 in the same process as the pixel TFT.

As shown in FIG. 1, the liquid crystal capacitance CL is formed by the pixel electrode 151, the counter electrode 204, and the liquid crystal composition 300 sandwiched between these electrodes. Also,
The auxiliary capacitance Cs is formed electrically in parallel with the liquid crystal capacitance CL. The auxiliary capacitance Cs is formed by a pair of electrodes opposed to each other via an insulating layer, that is, an auxiliary capacitance electrode 61 having the same potential as the pixel electrode 151 and an auxiliary capacitance line 52 set to a predetermined potential. . The auxiliary capacitance electrode 61 is formed of a polysilicon thin film and is in contact with the pixel electrode 151. The auxiliary capacitance line 52 is formed of the same material as the scanning line Y integrated with the gate electrode 63.

As shown in FIG. 2, the liquid crystal display device includes a liquid crystal composition 30 between an array substrate 100 and a counter substrate 200.
Thus, a reflection type liquid crystal display device sandwiching 0 is formed.

The array substrate 100 of the liquid crystal display device has a pixel electrode 15 disposed for each of a plurality of pixels on a transparent insulating substrate 11 such as a glass substrate in a display area 102.
1. Switching elements formed corresponding to the pixel electrodes 151, that is, the pixel TFTs 121, and the alignment film 13A formed so as to cover the whole of the plurality of pixel electrodes 151.
And so on.

More specifically, the array substrate 100 has an undercoating layer 60 on the insulating substrate 11. The undercoating layer 60 is formed by stacking, for example, a silicon nitride film and a silicon oxide film.

The pixel TFT 121 has a semiconductor layer 112 formed of a polysilicon film disposed on the undercoating layer 60. This semiconductor layer 112
Is a drain region 112D formed by doping impurities on both sides of the channel region 112C.
And a source region 112S. This pixel TFT
The reference numeral 121 includes a scanning line Y and a gate electrode 63 integrated with the channel region 112C of the semiconductor layer 112 with the gate insulating film 62 interposed therebetween.

The source electrode 88 of the pixel TFT 121 is formed integrally with the signal line X, and is electrically connected to the source region 112S of the semiconductor layer 112 via a contact hole 77 penetrating the gate insulating film 62 and the interlayer insulating film 76. Have been. The drain electrode 89 of the pixel TFT 121 is connected to the drain region 112 of the semiconductor layer 112 through a contact hole 78 penetrating the gate insulating film 62 and the interlayer insulating film 76.
D is electrically connected.

The array substrate 100 is provided with a liquid crystal capacitor CL.
A storage capacitor electrode 61 having the same potential as the pixel electrode 151 disposed on the semiconductor layer 112 via the gate insulating film 62 to form a storage capacitor CS electrically in parallel with the storage capacitor CS set at a predetermined potential And a line 52.

The auxiliary capacitance line 52 is provided in a layer on the same plane as the scanning line Y and is formed in parallel with the scanning line Y. A part of the auxiliary capacitance line 52 is arranged to face the auxiliary capacitance electrode 61 via the gate insulating film 62.

The auxiliary capacitance electrode 61 is formed of an impurity-doped polysilicon film provided in the same step on the same plane as the semiconductor layer 112 of the pixel TFT 121. The connection wiring 90 extending from the drain electrode 89 of the pixel TFT 121 is electrically connected to the auxiliary capacitance electrode 61 via a contact hole 91 penetrating the gate insulating film 62 and the interlayer insulating film 76.

Further, the array substrate 100 includes the insulating film 24
It has a pixel electrode 151 disposed thereon. The pixel electrode 151 is formed of a light-reflective material such as aluminum, and is electrically connected to the connection wiring 90 via a contact hole 81 penetrating the insulating film 24. Thus, the drain electrode 89 of the pixel TFT 121 is electrically connected to the auxiliary capacitance electrode 61 and the pixel electrode 151 via the connection wiring 90.

Signal line X, scanning line Y, and auxiliary capacitance line 52
Are formed of a light-shielding low-resistance material such as aluminum or molybdenum-tungsten. In this embodiment, the scanning line Y and the auxiliary capacitance line 52 are formed of molybdenum-tungsten,
The signal line X is mainly formed of aluminum.

On the surface of the array substrate 100 facing the liquid crystal composition 300, an alignment film 13A for aligning the liquid crystal molecules contained in the liquid crystal composition 300 in a predetermined direction is disposed.

The counter substrate 200 includes a color filter layer 2 formed on a transparent insulating substrate 21 such as a glass substrate.
4, an opposing electrode 204, and an alignment film 13B covering the opposing electrode 204.

The color filter layer 24 is formed of a colored resin layer colored red (R), green (G), and blue (B). The opposing electrode 204 is formed of a light-transmitting conductive member such as ITO (indium tin oxide), and the pixel electrode 151 on the array substrate 100 side.
Are arranged on the entire surface in opposition to. The alignment film 13B aligns liquid crystal molecules included in the liquid crystal composition 300 in a direction shifted by, for example, 90 degrees from a predetermined direction. Counter substrate 2
A polarizing plate PL2 is provided on the outer surface of the sheet No. 00.

Next, a method of manufacturing the above-described liquid crystal display device will be described.

In the manufacturing process of the array substrate 100, first,
C is placed on an insulating substrate 11 such as glass having a thickness of 0.7 mm.
By a VD method, a silicon nitride film and a silicon oxide film are successively formed to form an undercoating layer 60 having a two-layer structure. Subsequently, on the undercoating layer 60,
An amorphous silicon film is formed by a CVD method or the like. Then, the amorphous silicon film is irradiated with an excimer laser beam and is annealed to be polycrystallized. After that, the polycrystallized silicon film, that is, the polysilicon film is patterned by a photolithography process to form the semiconductor layer 112 of the TFT 121 and the auxiliary capacitance electrode 61.

Subsequently, a gate insulating film 62 is formed by forming a silicon oxide film on the entire surface by the CVD method. Subsequently, by sputtering, the entire surface of the gate insulating film 62 is tantalum (Ta), chromium (Cr), aluminum (Al), molybdenum (Mo), tungsten (W),
A simple substance such as copper (Cu), a laminated film thereof, or an alloy film thereof (in this embodiment, Mo-W
Alloy film), and is patterned into a predetermined shape by a photolithography process. Accordingly, the scanning line Y, the auxiliary capacitance line 52, and the gate electrode 63 integrated with the scanning line Y
And various wirings are formed.

Subsequently, using the gate electrode 63 as a mask,
The semiconductor film 11 is formed by ion implantation or ion doping.
2 is implanted with impurities. Thus, a drain region 112D and a source region 112S of the TFT 121 are formed. Then, the impurities are activated by annealing the entire substrate.

Subsequently, a silicon oxide film is formed on the entire surface by the CVD method, and an interlayer insulating film 76 having a two-layer structure is formed.

Subsequently, by a photolithography process,
Through the gate insulating film 62 and the interlayer insulating film 76, the TFT
Contact hole 7 reaching source region 112S of 121
7 and contact hole 7 reaching drain region 112D
8 and a contact hole 91 reaching the auxiliary capacitance electrode 61
And form

Subsequently, Ta, Cr, Al, Mo, W, and C are formed on the entire surface of the interlayer insulating film 76 by sputtering.
A single film of u or the like, a laminated film thereof, or an alloy film thereof (in this embodiment, a laminated film of Mo—Al) is formed and patterned into a predetermined shape by a photolithography process. Thus, the signal line X is formed, and the source electrode 88 of the TFT 121 is formed integrally with the signal line X. At the same time, a drain electrode 89 of the TFT 121 and a connection wiring 90 extending from the drain electrode 89 are formed.

Subsequently, at least one of a silicon nitride film and a silicon oxide film is formed by a CVD method or the like, and an insulating layer 24 is formed. In the step of forming the insulating layer 24,
A through hole 81 for connecting the connection wiring 90 and the pixel electrode 151 is also formed at the same time. In the case of a reflective display device as in this embodiment, an acrylic resin having an uneven surface is disposed on an insulating layer, and a pixel electrode formed in a later step is formed to have an uneven shape. good. Subsequently, a pixel electrode 151 in contact with the TFT 121 is formed by depositing aluminum on the insulating layer 24 by a sputtering method and patterning the film into a predetermined pixel pattern.

Subsequently, an alignment film material such as polyimide is applied to the entire surface of the substrate at a thickness of 500 Å, and after baking, rubbing is performed to form an alignment film 13A.

Thus, the array substrate 100 is manufactured.

On the other hand, in the manufacturing process of the counter substrate 200, first, a light-transmitting insulating substrate 2 made of glass or the like having a thickness of 0.7 mm is used.
A UV curable acrylic resin resist in which a red pigment is dispersed is applied on the entire surface of the substrate 1 by a spinner. Then, exposure is performed through a photomask that irradiates light to a portion corresponding to the red pixel. Then, the resist film is developed with a predetermined developer, washed with water, and baked. Then, the red color filter layer 24
(R) is formed.

Subsequently, by repeating the same steps, a green color filter layer 24 (G) and a blue color filter layer 24 (B) are formed. Thereby, about 3μ
m color filter layer 24 (R, G, B)
Is formed.

Subsequently, about 100 ITO was deposited on the color filter layer 24 (R, G, B) by sputtering.
The counter electrode 204 is formed to a thickness of nm. Then, an alignment film material such as polyimide is applied to the entire surface of the light-transmitting insulating substrate 21 so as to cover the opposing electrode 204, baked, and then subjected to an alignment process to form an alignment film 13B.

Thus, the counter substrate 200 is manufactured.

In the manufacturing process of the liquid crystal display device, the outer edge sealing member 106 is applied along the outer edge of the array substrate 100 so as to surround the liquid crystal accommodating space except for the liquid crystal inlet, and the outer edge of the array substrate 100 and the outer edge of the counter substrate 200 are formed. And glue. The outer edge sealing member 106 is, for example, a thermosetting epoxy adhesive.

Subsequently, the liquid crystal composition 300 is injected in a vacuum state from the liquid crystal injection port into the liquid crystal accommodating space, and the liquid crystal injection port is sealed with an injection port sealing member which is a thermosetting epoxy adhesive. The liquid crystal composition 300 is composed of, for example, a nematic liquid crystal to which a chiral material is added.

The liquid crystal display device is manufactured by the above manufacturing method.

FIG. 3 is a schematic plan view of the array substrate showing a part of the display area, and FIG. 4 is a diagram showing the positions of the source region and the drain region of each pixel TFT in FIG.

By the way, in the first embodiment, in the reflection type liquid crystal display device, as shown in FIG.
In the semiconductor layer 112 of T121, a source region S (first connection portion) connected to a driving source (signal line driving circuit) and a drain region D (second connection portion) connected to a pixel (pixel electrode 151).
The connection position with the connection unit) is set to be different for each pixel of the display area 102.

That is, as shown in FIG. 3 and FIG.
The semiconductor layer 112 of the FT 121 is formed so as to extend along the row direction substantially in parallel with the scanning line Y. In the pixel P1, the source region S is located on the side of the semiconductor layer 112 close to the signal line X.
And a drain region D is formed on the side away from the signal line X. A pixel P2 adjacent to the pixel P1 in the row direction
In (2), the source region S is formed on the side of the semiconductor layer 112 away from the signal line X, and the drain region D is formed on the side near the signal line X. In the pixel P3 adjacent to the pixel P2 in the row direction, the source region S is formed on the side of the semiconductor layer 112 close to the signal line X, and the drain region D is formed on the side away from the signal line X.

Also, as shown in FIG. 5, a source region S is formed on the side of the semiconductor layer 112 away from the signal line X in the pixel adjacent to the pixel P1 in the column direction, and the side near the signal line X is formed. A drain region D may be formed.

As described above, in the liquid crystal display device including the TFT including the semiconductor layer formed of the polysilicon film as the switching element for switching the pixel, the pixels are arranged in each of the pixels adjacent to each other in the display area. The TFT is set so that the arrangement positions of the drain region and the source region are different from each other. This makes it possible to disperse periodic unevenness in TFT characteristics due to excimer laser annealing when forming a polysilicon semiconductor layer.

That is, in the display area, the direction from the source to the drain of the TFT is alternately switched for each pixel, so that periodic display unevenness can be prevented from being visually recognized.
The display quality can be improved.

In the first embodiment described above, the direction from the source to the drain of the TFT is changed for each pixel. However, the present invention is not limited to this, and may be set for each of a predetermined number of pixels.
The three pixels R, G, and B may be set as one set, and the direction from the source to the drain may be changed for each set.

In the first embodiment described above, an example in which the present invention is applied to a reflective liquid crystal display device has been described. However, the pattern of the first embodiment can be applied to a transmissive liquid crystal display device. When the pattern of the first embodiment is applied to a transmissive display device, it is desirable to provide a dummy light-shielding wiring for a pixel having the largest aperture ratio and to make the aperture ratios of all the pixels uniform.

In the first embodiment, the present invention is applied to the pixel TFT in the display area. However, the present invention can be applied to a driving circuit.

(Embodiment 2) The active matrix type liquid crystal display device 10 is a transmission type liquid crystal display device, and as shown in FIG.
Opposing substrate 200 disposed opposite to the
Liquid crystal composition 300 disposed between a substrate and a counter substrate 200
And

The array substrate 100 of the liquid crystal display device has a pixel electrode 15 disposed for each of a plurality of pixels on a transparent insulating substrate 11 such as a glass substrate in a display area 102.
1. Switching elements formed corresponding to the pixel electrodes 151, ie, pixel TFTs 121, a color filter layer 24 colored red (R), green (G), and blue (B) for each pixel, and a plurality of pixel electrodes. An alignment film 13A and the like formed so as to cover the whole 151 are provided.

More specifically, the array substrate 100 has an undercoating layer 60 on the insulating substrate 11. The undercoating layer 60 is formed by stacking, for example, a silicon nitride film and a silicon oxide film.

The pixel TFT 121 has a semiconductor layer 112 formed of a polysilicon film disposed on the undercoating layer 60. This semiconductor layer 112
Is a drain region 112D formed by doping impurities on both sides of the channel region 112C.
And a source region 112S. This pixel TFT
The reference numeral 121 includes a scanning line Y and a gate electrode 63 integrated with the channel layer 112C of the semiconductor layer 112 with the gate insulating film 62 interposed therebetween.

The source electrode 88 of the pixel TFT 121 is formed integrally with the signal line X, and is electrically connected to the source region 112S of the semiconductor layer 112 via a contact hole 77 penetrating the gate insulating film 62 and the interlayer insulating film 76. Have been. The drain electrode 89 of the pixel TFT 121 is connected to the drain region 112 of the semiconductor layer 112 through a contact hole 78 penetrating the gate insulating film 62 and the interlayer insulating film 76.
D is electrically connected.

The array substrate 100 is provided with a liquid crystal capacitor CL.
The semiconductor layer 112 is disposed via the gate insulating film 62 in order to form an auxiliary capacitance CS electrically parallel to the storage capacitor CS. The auxiliary capacitance electrode 61 has the same potential as the pixel electrode 151 and the auxiliary capacitance set at a predetermined potential. And a capacitance line 52.

The auxiliary capacitance line 52 is provided in a layer on the same plane as the scanning line Y and is formed in parallel with the scanning line Y. A part of the auxiliary capacitance line 52 is arranged to face the auxiliary capacitance electrode 61 via the gate insulating film 62.

The auxiliary capacitance electrode 61 is formed of an impurity-doped polysilicon film provided on the same plane as the semiconductor layer 112 of the pixel TFT 121. The auxiliary capacitance electrode 61 is electrically connected to the connection electrode 80 via a contact hole 91 penetrating the gate insulating film 62 and the interlayer insulating film 76.

Further, the array substrate 100 includes a pixel TFT
A color filter layer 24 is provided for each pixel so as to cover 121 and the like. This color filter layer 24
Are formed by colored resin layers colored red (R), green (G), and blue (B), respectively.

Further, the array substrate 100 has a pixel electrode 151 disposed on the color filter layer 24. The pixel electrode 151 is formed of a transparent conductive material such as ITO, and is electrically connected to the drain electrode 89 of the pixel TFT 121 via a contact hole 81 penetrating the color filter layer 24. The pixel electrode 151 is electrically connected to the connection electrode 80 via a contact hole 92 penetrating the color filter layer 24.

As a result, the drain electrode 89 of the pixel TFT 121 is electrically connected to the auxiliary capacitance electrode 61 and the pixel electrode 151.

The signal line X, the scanning line Y, and the auxiliary capacitance line 52
Are formed of a light-shielding low-resistance material such as aluminum or molybdenum-tungsten. In this embodiment, the scanning line Y and the auxiliary capacitance line 52 are formed of molybdenum-tungsten,
The signal line X is mainly formed of aluminum.

On the surface of the array substrate 100 facing the liquid crystal composition 300, an alignment film 13A for aligning the liquid crystal molecules contained in the liquid crystal composition 300 in a predetermined direction is disposed. On the outer surface of the array substrate 100, a polarizing plate PL1 is provided.

The counter substrate 200 has a counter electrode 204 formed on a transparent insulating substrate 21 such as a glass substrate, and an alignment film 13B covering the counter electrode 204.

The counter electrode 204 is formed of a transparent conductive material such as ITO, and is arranged so as to face the entire pixel electrode 151 on the array substrate 110 side. Alignment film 13B
Aligns liquid crystal molecules included in the liquid crystal composition 300 in a direction shifted by, for example, an angle of 90 degrees from a predetermined direction.
On the outer surface of the counter substrate 200, a polarizing plate PL2 is provided.

Next, a method of manufacturing the above-described liquid crystal display device will be described.

In the manufacturing process of the array substrate 100, first,
A silicon nitride film and a silicon oxide film are successively formed by a CVD method on a light-transmitting insulating substrate 11 such as glass having a thickness of 0.7 mm to form an undercoating layer 60 having a two-layer structure. Subsequently, the undercoating layer 60
An amorphous silicon film is formed thereon by a CVD method or the like. Then, the amorphous silicon film is irradiated with an excimer laser beam and is annealed to be polycrystallized. After that, the polycrystallized silicon film, that is, the polysilicon film is patterned by a photolithography process to form the semiconductor layer 112 of the TFT 121 and the auxiliary capacitance electrode 61.

Subsequently, a gate insulating film 62 is formed by forming a silicon oxide film over the entire surface by the CVD method. Subsequently, by sputtering, the entire surface of the gate insulating film 62 is tantalum (Ta), chromium (Cr), aluminum (Al), molybdenum (Mo), tungsten (W),
A simple substance such as copper (Cu), a laminated film thereof, or an alloy film thereof (in this embodiment, Mo-W
Alloy film), and is patterned into a predetermined shape by a photolithography process. Accordingly, the scanning line Y, the auxiliary capacitance line 52, and the gate electrode 63 integrated with the scanning line Y
And various wirings are formed.

Subsequently, using the gate electrode 63 as a mask,
The semiconductor film 11 is formed by ion implantation or ion doping.
2 is implanted with impurities. Thus, a drain region 112D and a source region 112S of the TFT 121 are formed. Then, the impurities are activated by annealing the entire substrate.

Subsequently, a silicon oxide film is formed on the entire surface by the CVD method, and an interlayer insulating film 76 is formed.

Subsequently, by a photolithography process,
Through the gate insulating film 62 and the interlayer insulating film 76, the TFT
Contact hole 7 reaching source region 112S of 121
7 and contact hole 7 reaching drain region 112D
8 and a contact hole 91 reaching the auxiliary capacitance electrode 61
And form

Subsequently, Ta, Cr, Al, Mo, W, C are deposited on the entire surface of the interlayer insulating film 76 by sputtering.
A single film of u or the like, a laminated film thereof, or an alloy film thereof (in this embodiment, a laminated film of Mo—Al) is formed and patterned into a predetermined shape by a photolithography process. Thus, the signal line X is formed, and the source electrode 88 of the TFT 121 is formed integrally with the signal line X. At the same time, the drain electrode 89 of the TFT 121 and the connection electrode 80 are formed.

Subsequently, a silicon nitride film SiNx is formed and patterned by a CVD method to form a passivation film 63.

Subsequently, an ultraviolet curable acrylic resin resist in which a red pigment is dispersed is applied to the entire surface of the substrate by a spinner. Then, exposure is performed through a photomask that irradiates light to a portion corresponding to the red pixel. Then, the resist film is developed with a predetermined developer, washed with water, and baked. Then, a red color filter layer 24 (R) is formed.

Subsequently, by repeating the same steps, a green color filter layer 24 (G) and a blue color filter layer 24 (B) are formed. Thereby, about 3μ
m color filter layer 24 (R, G, B)
Is formed.

In the process of forming the color filter layer 24, the drain electrode 89 of the pixel TFT 121 and the pixel electrode 1
At the same time, a through hole 81 for contacting the pixel electrode 51 and a through hole 92 for contacting the connection electrode 80 and the pixel electrode 151 are formed.

Subsequently, an ITO film is formed on the color filter layer 24 by a sputtering method, and is patterned into a predetermined pixel pattern, thereby forming a pixel electrode 151 in contact with the TFT 121.

Subsequently, an alignment film material such as polyimide is applied to the entire surface of the substrate at a thickness of 500 Å, and after baking, rubbing is performed to form an alignment film 13A.

Thus, the array substrate 100 is manufactured.

On the other hand, in the manufacturing process of the counter substrate 200, first, an ITO film is formed to a thickness of about 100 nm on a glass substrate 21 having a thickness of 0.7 mm by a sputtering method.
The counter electrode 204 is formed by patterning. Then, an alignment film material such as polyimide is applied to the entire surface of the transparent substrate 21 so as to cover the opposing electrode 204, baked, and then subjected to an alignment process to form the alignment film 13B.

Thus, the opposing substrate 200 is manufactured.

In the manufacturing process of the liquid crystal display device, the outer edge seal member 106 is applied along the outer edge of the array substrate 100 so as to surround the liquid crystal accommodating space except for the liquid crystal inlet, and the outer edge of the array substrate 100 and the outer edge of the counter substrate 200 are formed. And glue. The outer edge sealing member 106 is, for example, a thermosetting epoxy adhesive.

Subsequently, the liquid crystal composition 300 is injected into the liquid crystal accommodating space from the liquid crystal injection port 32 in a vacuum state, and the liquid crystal injection port 32 is sealed with an injection port sealing member 33 which is a thermosetting epoxy adhesive. . The liquid crystal composition 300 is composed of, for example, a nematic liquid crystal to which a chiral material is added.

A liquid crystal display panel is manufactured by the above manufacturing method.

In the second embodiment, in the transmission type liquid crystal display device, as shown in FIG.
In the semiconductor layer 112 of T121, a source region S (first connection portion) connected to a driving source (signal line driving circuit) and a drain region D (second connection portion) connected to a pixel (pixel electrode 151).
The connection position with the connection unit) is set to be different for each pixel of the display area 102.

That is, as shown in FIG. 7 and FIG.
The semiconductor layer 112 of the FT 121 extends in the column direction substantially perpendicular to the scanning line Y. In the pixel P1, the source region S is located on the side of the semiconductor layer 112 near the scanning line Y.
Is formed, and a drain region D is formed on the side away from the scanning line Y. A pixel P2 adjacent to the pixel P1 in the row direction
In, the source region S is formed on the side of the semiconductor layer 112 away from the scanning line Y, and the drain region D is formed on the side near the scanning line Y. In the pixel P3 adjacent to the pixel P2 in the row direction, the source region S is formed on the side of the semiconductor layer 112 near the scanning line Y, and the drain region D is formed on the side away from the scanning line Y. Similarly, for the pixel adjacent to the pixel P1 in the column direction, the source region S is formed on the side of the semiconductor layer 112 away from the scanning line Y, and the scanning line Y
The drain region D may be formed on the side closer to.

As described above, in a liquid crystal display device provided with a TFT including a semiconductor layer formed of a polysilicon film as a switching element for switching a pixel, each of the pixels adjacent to each other in a display area is disposed in each pixel. The TFT is set so that the arrangement positions of the drain region and the source region are different from each other. This allows
It is possible to disperse periodic TFT characteristic unevenness caused by excimer laser annealing when forming a polysilicon semiconductor layer.

That is, in the display area, by switching the direction from the source to the drain of the TFT alternately for each pixel, periodic display unevenness can be prevented from being visually recognized.
The display quality can be improved.

Further, as described above, the method of arranging the TFT and
By devising the contact between the pixel electrode and the TFT and between the pixel electrode and the auxiliary capacitance electrode, even when applied to a transmissive liquid crystal display device, the aperture ratio of each pixel is kept the same.
The direction from the source to the drain of the TFT can be switched.

Further, in the above-described second embodiment, the description has been given of the case where the direction from the source to the drain is switched for each pixel. However, the present invention is not limited to this, and may be set for each predetermined number of pixels. The three pixels R, G, and B may be set as one set, and the direction from the source to the drain may be changed for each set.

Further, in the above-described second embodiment, the direction from the source to the drain is changed in the row direction. However, the present invention can be applied to pixels in the column direction.

In the second embodiment, an example in which the present invention is applied to a transmissive liquid crystal display device has been described.
The pattern of the second embodiment described above can be applied to a reflective liquid crystal display device.

In the second embodiment, the case where the present invention is applied to the pixel TFT in the display area has been described. However, the present invention can be applied to a driving circuit.

(Second Embodiment) Next, as a display device of the present invention, a self-luminous display device, for example, an organic EL
(Electroluminescence) An embodiment of the display device will be described.

Example 1 As shown in FIG.
The display device 1 includes an array substrate 100 on which organic EL elements are arranged in a matrix, and a sealing substrate for sealing the array substrate 100. The display area 102 for displaying an image on the array substrate 100 is provided with three types of light-emitting portions that emit red, green, and blue light, that is, organic EL elements 40.

The organic EL element 40 has a first electrode formed in an independent island shape for each element, a second electrode arranged opposite to the first electrode and formed in common for each element, and And an organic light-emitting layer as a light-emitting layer to be held.

The array substrate 100 has a display area 10
2, two thin film transistors, ie, pixel TF
It includes a T10 and a driving TFT 20, a storage capacitor element 30, and an organic EL element 40. The organic EL element 40
The excitation power selected through the pixel TFT 10 as a switching element and applied to the organic EL element 40 is the driving TF
It is controlled by T20.

The array substrate 100 includes a plurality of scanning lines Y arranged along the row direction of the organic EL elements 40 and a plurality of signal lines X arranged along the column direction of the organic EL elements 40. And a power supply line PSL for supplying power to the first electrode side of the organic EL element 40. further,
The array substrate 100 includes, in its peripheral area 104, a scanning line driving circuit 107 for supplying a driving signal to the scanning lines Y and a signal line driving circuit 108 for supplying a driving signal to the signal lines X.

The scanning line Y is connected to the scanning line driving circuit 107, and the signal line Y is connected to the signal line driving circuit 108. The pixel TFT 10 is arranged near the intersection of the scanning line Y and the signal line X. The driving TFT 20 is an organic EL
It is connected in series with the element 40. The storage capacitor 30 is connected in series with the pixel TFT 10 and in the drive TFT 20.
Are connected in parallel, and both electrodes of the storage capacitor 30 are connected to the gate electrode and the source electrode of the driving TFT 20, respectively.

The power supply line PSL is connected to a first electrode power supply line 110 arranged around the display area 102. The end of the organic EL element 40 on the second electrode side is the display area 1
02, which is connected to a second electrode power supply line 114 that supplies a common potential, that is, a ground potential.

More specifically, the gate electrode of the pixel TFT 10 is connected to the scanning line Y, the source electrode is connected to the signal line X, and the drain electrode is connected to one end of the storage capacitor 30 and the gate electrode of the driving TFT 20. Have been.
The source electrode of the driving TFT 20 is connected to the power supply line PSL, and the drain electrode is connected to the lower electrode of the organic EL element 40. The other end of the storage capacitor 30 is connected to the power supply line PSL.

When the pixel TFT 10 is selected via the corresponding scanning line Y, the driving signal of the corresponding signal line X is written into the storage capacitor 30 and the driving of the driving TFT 20 is controlled.
The gate voltage of the driving TFT 20 is adjusted based on the driving signal, and a desired driving current is supplied to the organic EL element 40 from the power supply line PSL.

FIG. 10 is a schematic sectional view of the driving TFT 20 and the organic EL element 40 of the array substrate.

The driving TFT 20 includes a polysilicon semiconductor layer 20P disposed on an insulating support substrate 120 such as a glass substrate, a gate electrode 20G disposed via a gate insulating film 52, a gate insulating film 52 and an interlayer insulating film. Insulating film 5
The source electrode 20S is in contact with the source region 20PS of the polysilicon semiconductor layer 20P through a contact hole 93 that penetrates through the gate insulating film 52 and the interlayer insulating film 54. And a drain electrode 20D in contact with the drain region 20PD.

The organic EL element 40 is provided on an insulating film 56 provided on the interlayer insulating film 54. The organic EL elements 40 for one pixel are partitioned by the partition walls 130 arranged in a lattice. The organic EL element 40 includes an organic light emitting layer 64 sandwiched between a first electrode 60 disposed below and a second electrode 66 disposed above.

That is, the first electrode 60 is disposed on the insulating film 56 and the contact hole 9 penetrating through the insulating film 56 is formed.
5, and is connected to the drain electrode 20D of the driving TFT 20. This first electrode 60 is made of ITO (Indiu).
m Tin Oxide: formed of a transparent conductive material such as indium-tin-oxide (IZO) or indium-zinc-oxide (IZO), and constitutes an anode.

The organic light-emitting layer 64 may be composed of a three-layer structure of a hole transport layer, an electron transport layer, and a light-emitting layer formed for each color, which are formed in common for each color. It may be composed of a single layer or a single layer. For example, the hole transport layer is disposed on the anode (first electrode) 60 and is formed by a thin film of an aromatic amine derivative, a polythiophene derivative, a polyaniline derivative, or the like. The light emitting layer is disposed on the hole transport layer, and is formed of an organic compound that emits red, green, or blue light. This light emitting layer is made of PP, for example, when a polymer material is used.
V (polyparaphenylene vinylene), a polyfluorene derivative, a precursor thereof, or the like is laminated.

The second electrode 66 is arranged on the organic light emitting layer 64 in common for each organic EL element. This second electrode 66
Is formed of a light-shielding metal film such as Ca (calcium), Al (aluminum), Ba (barium), and Ag (silver), and constitutes a cathode.

In the organic EL element 40 thus configured, electrons and holes are injected into the organic light emitting layer 64 sandwiched between the first electrode 62 and the second electrode 66, and these are recombined. An exciton is generated, and light is emitted by light emission of a predetermined wavelength generated when the exciton is deactivated. This EL
Light is emitted on the lower surface side of the array substrate 100, that is, the first electrode 6
The light is emitted from the 0 side.

By the way, in the first embodiment, as shown in FIG.
Driving source (power supply line) in semiconductor layer 20P of T20
The source region S (first connection portion) connected to the pixel and the pixel (first
Drain region D (second connection part) connected to electrode 60)
Are set to be different from each other for each pixel of the display area 102.

That is, as shown in FIGS. 11 and 12, the semiconductor layer 20P of the driving TFT 20 is formed to extend substantially in parallel with the scanning line Y in the row direction. Pixel P1
In, the source region S is formed on the side of the semiconductor layer 20P close to the signal line X, and the drain region D is formed on the side away from the signal line X. In the pixel P2 adjacent to the pixel P1 in the row direction, the source region S is formed on the side of the semiconductor layer 20P away from the signal line X, and the drain region D is formed on the side near the signal line X. In the pixel P3 adjacent to the pixel P2 in the row direction, the source region S is formed on the semiconductor layer 20P near the signal line X, and the drain region D is formed on the side away from the signal line X.

Similarly, for the pixel adjacent to the pixel P1 in the column direction, the source region S is formed on the side of the semiconductor layer 20P away from the signal line X, and the drain region D is formed on the side near the signal line X. You may.

As described above, in the organic EL display device including the TFT including the semiconductor layer formed of the polysilicon film as the switching element constituting the constant current circuit for driving the organic EL element, the display areas are adjacent to each other. In the pixel, the TFTs arranged in each pixel are set so that the arrangement positions of the drain region and the source region are different from each other. This makes it possible to disperse periodic unevenness in TFT characteristics due to excimer laser annealing when forming the polysilicon semiconductor layer.

That is, by alternately switching the direction from the source to the drain of the TFT for each pixel in the display area, it is possible to prevent the periodic display unevenness from being visually recognized.
The display quality can be improved.

In the first embodiment described above, the direction from the source to the drain of the TFT is changed for each pixel. However, the present invention is not limited to this, and may be set for each of a predetermined number of pixels.
The three pixels of R, G, and B may be set as one set, and the direction from the source to the drain may be changed for each set.

In the first embodiment, the present invention is applied to a TF provided for driving the organic EL element 40 in the display area.
Although applied to T20, the present invention can be applied to the pixel TFT 10 and other TFTs included in a driving circuit, thereby further improving display quality.

(Example 2) Organic EL according to Example 2
As shown in FIG. 13, the display device includes a circuit incorporated to cancel the variation in threshold value in order to make the characteristics of the TFT 20 for driving the organic EL element uniform.
That is, this organic EL display device includes a threshold variation canceling capacitive element 31 between the TFT 10 and the storage capacitive element 30, and further includes two threshold variation canceling operation controlling TFTs 33 and 3 connected to the control wiring 32.
4 is provided.

Also in the organic EL display device having such a configuration, when a polysilicon film is applied to the semiconductor layers of the TFTs 10, 20, 33, and 34, there is a problem that variations in mobility cannot be completely canceled.

Therefore, in the second embodiment, by switching the direction from the source to the drain of the TFT 20 for driving the organic EL element alternately for each pixel, the characteristic unevenness (movement) of the periodic TFT caused by excimer laser annealing is obtained. (Including degrees and thresholds) can be spatially dispersed.

That is, in the display area, by switching the direction from the source to the drain of the TFT alternately for each pixel, periodic display unevenness can be prevented from being visually recognized.
The display quality can be improved.

Further, by taking the same measures for other TFTs, it is possible to further improve the display quality.

In this embodiment, the storage capacitor 3
Although the description has been made using the configuration in which both electrodes of the driving TFT 20 are connected to the gate electrode and the source electrode of the driving TFT 20, the present invention is not limited to this. It may be configured to be connected to a line, and can be appropriately adopted without departing from the gist of the present invention.

(Third Embodiment) Next, the first embodiment will be described.
A modification example common to the liquid crystal display device according to the embodiment and the self-luminous display device according to the second embodiment will be described. In the following modified example, TF
Only the direction from the source to the drain of the polysilicon semiconductor layer at T is different, and the other configuration is the same as that of the above-described first or second embodiment. In order to simplify the description, the source ( The description will be made only in the directions of S) and the drain (D).

(Modification 1) As shown in FIG. 14, in this modification 1, in four pixels P1 to P4 adjacent to each other, the direction from the source to the drain of the TFT in each pixel is changed in the row direction and the column direction. , And are switched in four directions for each pixel.

That is, in the pixel P1, the source region S is formed at one end of the semiconductor layer extending in the row direction, and the drain region D is formed at the other end. In the pixel P2 adjacent to the pixel P1 in the row direction, the source region S is formed on one end of the semiconductor layer extending along the column direction, and the drain region D is formed on the other end.

In the pixel P3 adjacent to the pixel P1 in the column direction, the source region S is formed on the other end of the semiconductor layer extending in the column direction, and the drain region D is formed on one end. In the pixel P4 adjacent to the pixel P3 in the row direction, the source region S is formed on the other end of the semiconductor layer extending in the row direction, and the drain region D is formed on one end.

The first modified example is characterized in that no TFT having the same direction from the source to the drain as the own pixel exists in all adjacent pixels (eight surrounding directions).

As described above, in the display device including the TFT including the polysilicon semiconductor layer, in the pixels adjacent to each other in the display area, the TFTs arranged in each pixel are arranged such that the drain region and the source region are arranged at different positions. It is set differently. This makes it possible to disperse periodic unevenness in TFT characteristics due to excimer laser annealing when forming a polysilicon semiconductor layer.

That is, in the display area, by alternately switching the direction from the source to the drain of the TFT for each pixel, it is possible to prevent periodic display unevenness from being visually recognized.
The display quality can be improved.

(Modification 2) As shown in FIG. 15, in this modification 2, in the four pixels P1 to P4 adjacent to each other along the row direction, the direction from the source to the drain of the TFT in each pixel is changed. The pixels are arranged in opposite directions in the row direction and the column direction, and are switched in four directions for each pixel.

That is, in the pixel P1, the source region S is formed at one end of the semiconductor layer extending in the row direction, and the drain region D is formed at the other end. In the pixel P2 adjacent to the pixel P1 in the row direction, the source region S is formed on the other end of the semiconductor layer extending in the column direction, and the drain region D is formed on one end.

In the pixel P3 adjacent to the pixel P2 in the row direction, the source region S is formed on the other end of the semiconductor layer extending in the row direction, and the drain region D is formed on one end. In the pixel P4 adjacent to the pixel P3 in the row direction, the source region S is formed at one end of the semiconductor layer extending along the column direction, and the drain region D is formed at the other end.

The second modification is characterized in that no TFT having the same source-to-drain direction as its own pixel exists in pixels vertically and horizontally adjacent (in four directions). Focusing on four pixels adjacent to each other in the row direction as compared with the above-described first modification, the first modification has a change in two directions of “→ ↑ → ↑”, whereas the second modification has a change in the two directions. , "→ ↓ ←
↑ ”in four directions. For this reason, when compared with the first modification, it is possible to more spatially disperse the display unevenness.

(Modification 3) As shown in FIG. 16, in Modification 3, in the four pixels P1 to P4 adjacent to each other along the row direction, the direction from the source to the drain of the TFT in each pixel is changed as follows. The pixels are arranged in opposite directions in the row direction and the column direction, and are switched in four directions for each pixel.

That is, in the pixel P1, the source region S is formed at one end of the semiconductor layer extending along the row direction, and the drain region D is formed at the other end. In the pixel P2 adjacent to the pixel P1 in the row direction, the source region S is formed on the other end of the semiconductor layer extending in the column direction, and the drain region D is formed on one end.

In the pixel P3 adjacent to the pixel P2 in the row direction, the source region S is formed on the other end of the semiconductor layer extending in the row direction, and the drain region D is formed on one end. In the pixel P4 adjacent to the pixel P3 in the row direction, the source region S is formed at one end of the semiconductor layer extending along the column direction, and the drain region D is formed at the other end.

In this modification 3, in the four pixels P3 to P6 adjacent to each other, the direction from the source to the drain of the TFT in each pixel is reversed in the row direction and the column direction, and the Are switched in four directions.

That is, in the pixel P5 adjacent to the pixel P3 in the column direction, the source region S is formed at one end of the semiconductor layer extending in the row direction, and the drain region D is formed at the other end.
Is formed. In the pixel P6 adjacent to the pixel P5 in the row direction, the source region S is formed at one end of the semiconductor layer extending along the column direction, and the drain region D is formed at the other end.

The third modification is characterized in that, similarly to the first modification, no TFT having the same source-to-drain direction as that of the own pixel exists in all adjacent pixels (eight surrounding directions). Further, in the third modification, similar to the second modification, when attention is paid to four pixels adjacent in the row direction, “→
↓ ← ↑ ”in four directions.

In the second modified example, there is a pixel having the same source-to-drain direction in the pixel in the oblique direction of the own pixel. In the third modified example, this is also improved, and the display unevenness is more spatially dispersed. It becomes possible.

(Modification 4) As shown in FIG. 17, in this modification 4, two or more TFTs having the same function are provided.
Are arranged in parallel in the same pixel, and the direction from the source to the drain is arranged in the opposite direction in the same pixel.

As a result, the source of the TFT in each pixel →
The characteristic unevenness of the TFT depending on the direction of the drain can be averaged, and the periodic display unevenness of the active matrix display device can be improved.

(Modification 5) As shown in FIG. 18, in Modification 5, two or more TFTs having the same function are provided.
Are arranged in parallel in the same pixel, and the direction from the source to the drain is arranged in the same pixel in the opposite direction. Further, in the fifth modification, in the four pixels P1 to P4 adjacent to each other, the direction from the source to the drain of the TFT in each pixel is reversed in the row direction and the column direction, respectively, so that the four Switched and arranged.

The fifth modification will be described more specifically by taking a liquid crystal display device as an example.

That is, as shown in FIG. 19, the pixel P1
In the above, a source region S is formed at one end of one semiconductor layer extending in the row direction, and a drain region D is formed at the other end.
Is formed. In the pixel P1, the source region S is formed on the other end of the other semiconductor layer extending in the row direction, and the drain region D is formed on one end.

Pixel P2 adjacent to pixel P1 in the row direction
In the above, a source region S is formed on one end of one semiconductor layer extending along the column direction, and a drain region D is formed on the other end.
Is formed. In the pixel P2, a source region S is formed on the other end of the other semiconductor layer extending in the column direction, and a drain region D is formed on one end.

In the pixel P3 adjacent to the pixel P1 in the column direction, the source region S is formed on the other end of one semiconductor layer extending in the column direction, and the drain region D is formed on one end. In the pixel P3, a source region S is formed at one end of the other semiconductor layer extending in the column direction, and a drain region D is formed at the other end.

Pixel P4 adjacent to pixel P3 in the row direction
In the above, a source region S is formed on the other end of one semiconductor layer extending along the row direction, and a drain region D is formed on one end.
Is formed. In the pixel P4, a source region S is formed at one end of the other semiconductor layer extending in the row direction, and a drain region D is formed at the other end.

As a result, the source of the TFT in each pixel →
The characteristic unevenness of the TFT depending on the direction of the drain can be averaged, the periodic display unevenness of the active matrix type display device can be improved, and the display quality can be further improved.

As described above, according to the display device of the present invention, a display area including a plurality of pixels arranged in a matrix is provided, and at least one switching area is arranged for each pixel in this display area. Device. This switching element has a first connection part connected to the driving source and a second connection part connected to the pixel. And this display device is provided with the switching element from which the arrangement position of a 1st connection part and a 2nd connection part differs mutually in a display area.

That is, this switching element has the first
The display device includes a polysilicon semiconductor layer including a connection portion and a second connection portion, and in pixels adjacent to each other in the display area, positions of the first connection portion and the second connection portion of the switching element arranged in each pixel are different from each other. It is configured as follows.

Further, in one pixel of the display area, a plurality of switching elements arranged in the same pixel may be arranged such that the arrangement positions of the first connection portion and the second connection portion are different from each other.

With such a configuration, it is possible to spatially disperse periodic display unevenness caused by the periodic unevenness of the TFT characteristics caused by the manufacturing process of the array substrate. The display quality can be improved.

[0161]

As described above, according to the present invention, it is possible to provide a display device capable of spatially dispersing periodic display unevenness and improving display quality.

[Brief description of the drawings]

FIG. 1 is a perspective view showing one embodiment of an active matrix liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a sectional view schematically showing a structure of Example 1 of the active matrix type liquid crystal display device according to the first embodiment of the present invention.

FIG. 3 is a plan view schematically showing a structure of an array substrate of the active matrix type liquid crystal display device shown in FIG. 2;

FIG. 4 is a diagram for explaining Example 1 according to the first embodiment.

FIG. 5 is a diagram for explaining another example of Example 1 according to the first embodiment.

FIG. 6 is a sectional view schematically showing a structure of Example 2 of the active matrix type liquid crystal display device according to the first embodiment of the present invention.

FIG. 7 is a plan view schematically showing a structure of an array substrate of the active matrix type liquid crystal display device shown in FIG. 6;

FIG. 8 is a diagram for explaining Example 2 according to the first embodiment.

FIG. 9 is a schematic plan view showing one embodiment of a self-luminous display device according to a second embodiment of the present invention.

FIG. 10 is a sectional view schematically showing a structure of a first embodiment of the self-luminous display device according to the second embodiment of the present invention.

FIG. 11 is a plan view schematically showing a structure of an array substrate of the self-luminous display device shown in FIG.

FIG. 12 is a first example according to the second embodiment;
FIG.

FIG. 13 is a second example according to the second embodiment;
FIG.

FIG. 14 is a diagram schematically showing a configuration of Modification 1 according to the third embodiment of the present invention.

FIG. 15 is a diagram schematically showing a configuration of a modification 2 according to the third embodiment of the present invention.

FIG. 16 is a diagram schematically showing a configuration of a modification 3 according to the third embodiment of the present invention.

FIG. 17 is a diagram schematically showing a configuration of a modification 4 according to the third embodiment of the present invention.

FIG. 18 is a diagram schematically showing a configuration of a modification 5 according to the third embodiment of the present invention.

FIG. 19 is a plan view schematically showing a structure of an array substrate when the configuration shown in FIG. 18 is applied to an active matrix liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Pixel TFT 20 ... Driving TFT 40 ... Organic EL element 60 ... First electrode 64 ... Organic light emitting layer 66 ... Second electrode 100 ... Array substrate 102 ... Display area 112 ... Polysilicon semiconductor layer 121 ... TFT 151 ... Pixel electrode 200 ... counter substrate 204 ... counter electrode 300 ... liquid crystal composition

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 29/786 H01L 29/78 612Z H05B 33/14 627G F-term (Reference) 3K007 AB17 CA03 EB00 5C094 AA03 BA03 BA12 BA29 BA43 CA19 CA24 DA14 DA15 DB04 EA04 EA07 EB02 EB05 ED11 5F052 AA02 BB07 DA02 DB01 JA01 5F110 AA30 BB04 CC02 DD02 DD13 DD14 DD17 EE02 EE03 EE04 EE06 EE44 FF02 FF29 GG02 GG13 HG13 HG13 HG13 HG13 HG13 H04 NN77 PP01 PP03 PP29

Claims (21)

[Claims]
1. A display device including a plurality of pixels arranged in a matrix, wherein each of the pixels includes a plurality of switching elements formed of thin film transistors, and the directions of a source region and a drain region of the switching elements are different. A display device characterized by the above-mentioned.
2. A plurality of pixels arranged in a matrix,
In a display device including a signal line arranged corresponding to each column of the pixel and a scanning line arranged corresponding to each row of the pixel, each of the pixels includes an island-shaped semiconductor layer. And a gate electrode disposed on the semiconductor layer via a gate insulating film and connected to a corresponding scan line. The semiconductor layer of the thin film transistor includes a predetermined concentration of impurities. A source region connected to the signal line, a drain region connected to the corresponding display element,
A display device, comprising: the thin film transistor, wherein the arrangement positions of the source region and the drain region of the thin film transistor are different for each of a predetermined number of pixels.
3. The thin film transistor according to claim 2, wherein the thin film transistors are arranged such that arrangement positions of the source region and the drain region are different for every predetermined number of pixels in the signal line direction. Display device.
4. The thin film transistor according to claim 2, wherein the thin film transistors are arranged such that arrangement positions of the source region and the drain region are different for every predetermined number of pixels in the scanning line direction. Display device.
5. The display device according to claim 2, wherein the thin film transistors are arranged such that the arrangement positions of the source region and the drain region are different for each of the adjacent pixels.
6. The display according to claim 2, wherein each of the pixels includes a plurality of the thin film transistors, and the thin film transistors have different directions of the source region and the drain region in each pixel. apparatus.
7. A display device having a display area composed of a plurality of pixels arranged in a matrix, comprising at least one switching element arranged for each pixel and switching a pixel, wherein the switching element is A first connection unit connected to a driving source, and a second connection unit connected to a pixel. In the display area, an arrangement position of the first connection unit and the second connection unit is the display area. A switching device that is different from each other in the column direction.
8. The pixel adjacent to the display area, wherein the switching elements arranged in each pixel are different in the arrangement position of the first connection portion and the second connection portion. Item 8. The display device according to Item 7.
9. In one pixel of the display area, the plurality of switching elements arranged in the same pixel are different in the arrangement position of the first connection portion and the second connection portion. The display device according to claim 7.
10. The display device according to claim 7, wherein said switching element has a polysilicon semiconductor layer including said first connection part and said second connection part.
11. The display device according to claim 7, wherein said display device is a liquid crystal display device having a liquid crystal layer sandwiched between a pair of substrates.
12. One of the substrates includes a scanning line, a signal line disposed substantially orthogonal to the scanning line, and the switching element disposed at an intersection of the scanning line and the signal line. , A pixel electrode connected to the switching element, wherein the switching element is connected to the first signal line.
The display device according to claim 11, further comprising a polysilicon semiconductor layer including a connection portion and a second connection portion connected to the pixel electrode.
13. The display device according to claim 7, wherein the display device is a self-luminous display device in which pixels having light-emitting layers formed in an independent island shape are arranged in a matrix. .
14. The switching device according to claim 11, wherein the switching element has a polysilicon semiconductor layer including a first connection portion connected to the signal line and a second connection portion connected to the pixel electrode. The display device according to the above.
15. A scanning line disposed on a substrate, a signal line disposed substantially perpendicular to the scanning line, a power supply line disposed substantially perpendicular to the signal line, A switching element disposed at an intersection of a power supply line and the signal line; a first electrode independently formed for each of the display elements and connected to the switching element; and commonly formed by a plurality of the display elements. The switching element has a polysilicon semiconductor layer including the first connection part connected to the power supply line and the second connection part connected to the first electrode. The display device according to claim 13, wherein:
16. A plurality of signal lines, a plurality of scanning lines arranged substantially orthogonal to the signal lines, a switching element arranged near the intersection thereof, and a display element connected to the switching element. A display device comprising pixels formed in a matrix, comprising: a switching element, an island-shaped semiconductor layer, a gate electrode disposed on the semiconductor layer via a gate insulating film and connected to a corresponding scan line, The semiconductor layer of the thin film transistor contains a predetermined concentration of impurities, a source region connected to the corresponding signal line, a drain region connected to the corresponding display element,
The display device, wherein the switching elements are arranged so that arrangement positions of the source region and the drain region are different from each other by a predetermined number in the signal line direction.
17. The display device according to claim 16, wherein said semiconductor layer is constituted by a polysilicon semiconductor layer.
18. The display device according to claim 16, wherein the switching elements are arranged such that arrangement positions of the source region and the drain region are different from each other by a predetermined number in the scanning line direction. .
19. A display device having a display area including a plurality of pixels arranged in a matrix, wherein each of the pixels includes a pixel switching element for selecting the pixel, and a drive connected to the pixel switching element. A display device comprising: an element; and a display element driven by the driving element, wherein the driving element is configured by a thin film transistor, and a direction of a source region and a drain region of the thin film transistor is different in the display area. .
20. The display device according to claim 19, wherein the semiconductor layer of said thin film transistor is constituted by a polysilicon semiconductor layer.
21. The display device according to claim 19, wherein said display element is a self-luminous display element.
JP2001175614A 2001-06-11 2001-06-11 Display device Pending JP2002366057A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001175614A JP2002366057A (en) 2001-06-11 2001-06-11 Display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001175614A JP2002366057A (en) 2001-06-11 2001-06-11 Display device

Publications (1)

Publication Number Publication Date
JP2002366057A true JP2002366057A (en) 2002-12-20

Family

ID=19016716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001175614A Pending JP2002366057A (en) 2001-06-11 2001-06-11 Display device

Country Status (1)

Country Link
JP (1) JP2002366057A (en)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004213027A (en) * 2003-01-08 2004-07-29 Samsung Electronics Co Ltd Polycrystalline silicon thin film transistor display panel and its manufacturing method
JP2005164741A (en) * 2003-11-28 2005-06-23 Toshiba Matsushita Display Technology Co Ltd Active matrix type display device and manufacturing method therefor
JP2006201765A (en) * 2005-01-07 2006-08-03 Samsung Electronics Co Ltd Thin-film transistor display panel
JP2008033073A (en) * 2006-07-31 2008-02-14 Sony Corp Display device and its manufacturing method
JP2008270540A (en) * 2007-04-20 2008-11-06 Sony Corp Manufacturing method of semiconductor device and display unit
US7595849B2 (en) 2002-12-27 2009-09-29 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
JP2009258638A (en) * 2008-03-25 2009-11-05 Sony Corp Method of producing display, display, method of producing thin film transistor substrate, and thin film transistor substrate
JP2010097051A (en) * 2008-10-17 2010-04-30 Sony Corp Panel
JP2010151865A (en) * 2008-12-24 2010-07-08 Sony Corp Display device and method of manufacturing the same
JP2011085925A (en) * 2009-10-15 2011-04-28 Samsung Mobile Display Co Ltd Organic light-emitting display device and method of fabricating the same
JP2012073649A (en) * 2008-04-24 2012-04-12 Samsung Mobile Display Co Ltd Manufacturing method of organic light emitting display device
JP2014013404A (en) * 2004-09-16 2014-01-23 Semiconductor Energy Lab Co Ltd Display device and electronic apparatus
US8654045B2 (en) 2006-07-31 2014-02-18 Sony Corporation Display and method for manufacturing display
JP2014067047A (en) * 2013-11-08 2014-04-17 Seiko Epson Corp Light emission device and electronic apparatus
US9066388B2 (en) 2005-11-30 2015-06-23 Seiko Epson Corporation Light-emitting device and electronic apparatus
US9070649B2 (en) 2005-11-30 2015-06-30 Seiko Epson Corporation Light-emitting device and electronic apparatus
JP2015166872A (en) * 2015-04-07 2015-09-24 セイコーエプソン株式会社 Light emission device and electronic apparatus
JP2016040596A (en) * 2014-08-12 2016-03-24 上海和輝光電有限公司Everdisplay Optronics (Shanghai) Limited Organic electroluminescence display

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02242224A (en) * 1989-03-16 1990-09-26 Fujitsu Ltd Matrix display device
JPH02244125A (en) * 1989-03-17 1990-09-28 Seiko Epson Corp Active matrix substrate
JPH0333724A (en) * 1989-06-30 1991-02-14 Hitachi Ltd Liquid crystal display device
JPH0876088A (en) * 1994-09-08 1996-03-22 Sharp Corp Image display device
JPH10135135A (en) * 1996-10-30 1998-05-22 Semiconductor Energy Lab Co Ltd Manufacturing semiconductor device
JPH1124606A (en) * 1997-07-02 1999-01-29 Seiko Epson Corp Display device
JP2000147562A (en) * 1991-10-16 2000-05-26 Semiconductor Energy Lab Co Ltd Electrooptical display device
JP2000172200A (en) * 1998-09-29 2000-06-23 Canon Inc Display element and color display element
JP2001035662A (en) * 1999-07-27 2001-02-09 Pioneer Electronic Corp Organic electroluminescence element display device and its manufacture
JP2001067018A (en) * 1999-06-21 2001-03-16 Semiconductor Energy Lab Co Ltd El display device, driving method therefor and electronic device
JP2001102595A (en) * 1999-09-30 2001-04-13 Sanyo Electric Co Ltd Thin film transistor and display
JP2001109405A (en) * 1999-10-01 2001-04-20 Sanyo Electric Co Ltd El display device

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02242224A (en) * 1989-03-16 1990-09-26 Fujitsu Ltd Matrix display device
JPH02244125A (en) * 1989-03-17 1990-09-28 Seiko Epson Corp Active matrix substrate
JPH0333724A (en) * 1989-06-30 1991-02-14 Hitachi Ltd Liquid crystal display device
JP2000147562A (en) * 1991-10-16 2000-05-26 Semiconductor Energy Lab Co Ltd Electrooptical display device
JPH0876088A (en) * 1994-09-08 1996-03-22 Sharp Corp Image display device
JPH10135135A (en) * 1996-10-30 1998-05-22 Semiconductor Energy Lab Co Ltd Manufacturing semiconductor device
JPH1124606A (en) * 1997-07-02 1999-01-29 Seiko Epson Corp Display device
JP2000172200A (en) * 1998-09-29 2000-06-23 Canon Inc Display element and color display element
JP2001067018A (en) * 1999-06-21 2001-03-16 Semiconductor Energy Lab Co Ltd El display device, driving method therefor and electronic device
JP2001035662A (en) * 1999-07-27 2001-02-09 Pioneer Electronic Corp Organic electroluminescence element display device and its manufacture
JP2001102595A (en) * 1999-09-30 2001-04-13 Sanyo Electric Co Ltd Thin film transistor and display
JP2001109405A (en) * 1999-10-01 2001-04-20 Sanyo Electric Co Ltd El display device

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7595849B2 (en) 2002-12-27 2009-09-29 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
JP4636487B2 (en) * 2003-01-08 2011-02-23 サムスン エレクトロニクス カンパニー リミテッド Method for manufacturing thin film transistor array panel
JP2004213027A (en) * 2003-01-08 2004-07-29 Samsung Electronics Co Ltd Polycrystalline silicon thin film transistor display panel and its manufacturing method
JP2005164741A (en) * 2003-11-28 2005-06-23 Toshiba Matsushita Display Technology Co Ltd Active matrix type display device and manufacturing method therefor
JP4686122B2 (en) * 2003-11-28 2011-05-18 東芝モバイルディスプレイ株式会社 Active matrix display device and manufacturing method thereof
JP2017083828A (en) * 2004-09-16 2017-05-18 株式会社半導体エネルギー研究所 Display device
US9577008B2 (en) 2004-09-16 2017-02-21 Semiconductor Energy Laboratory Co., Ltd. Display device and driving method of the same
JP2016066104A (en) * 2004-09-16 2016-04-28 株式会社半導体エネルギー研究所 Display device and electronic apparatus
JP2014013404A (en) * 2004-09-16 2014-01-23 Semiconductor Energy Lab Co Ltd Display device and electronic apparatus
JP2006201765A (en) * 2005-01-07 2006-08-03 Samsung Electronics Co Ltd Thin-film transistor display panel
US9917145B2 (en) 2005-11-30 2018-03-13 Seiko Epson Corporation Light-emitting device and electronic apparatus
US9379172B2 (en) 2005-11-30 2016-06-28 Seiko Epson Corporation Light-emitting device and electronic apparatus
US9070649B2 (en) 2005-11-30 2015-06-30 Seiko Epson Corporation Light-emitting device and electronic apparatus
US9066388B2 (en) 2005-11-30 2015-06-23 Seiko Epson Corporation Light-emitting device and electronic apparatus
JP2008033073A (en) * 2006-07-31 2008-02-14 Sony Corp Display device and its manufacturing method
US8810489B2 (en) 2006-07-31 2014-08-19 Sony Corporation Display and method for manufacturing display
US8654045B2 (en) 2006-07-31 2014-02-18 Sony Corporation Display and method for manufacturing display
US8994626B2 (en) 2006-07-31 2015-03-31 Sony Corporation Display and method for manufacturing display
JP2008270540A (en) * 2007-04-20 2008-11-06 Sony Corp Manufacturing method of semiconductor device and display unit
US8034672B2 (en) 2008-03-25 2011-10-11 Sony Corporation Method of producing display device, display device, method of producing thin-film transistor substrate, and thin-film transistor substrate
JP4538767B2 (en) * 2008-03-25 2010-09-08 ソニー株式会社 Display device manufacturing method and display device, and thin film transistor substrate manufacturing method and thin film transistor substrate
JP2009258638A (en) * 2008-03-25 2009-11-05 Sony Corp Method of producing display, display, method of producing thin film transistor substrate, and thin film transistor substrate
JP2012073649A (en) * 2008-04-24 2012-04-12 Samsung Mobile Display Co Ltd Manufacturing method of organic light emitting display device
US9171892B2 (en) 2008-04-24 2015-10-27 Samsung Display Co., Ltd. Method of manufacturing an organic light emitting display device by patterning and formation of pixel and gate electrodes
JP2010097051A (en) * 2008-10-17 2010-04-30 Sony Corp Panel
JP2010151865A (en) * 2008-12-24 2010-07-08 Sony Corp Display device and method of manufacturing the same
JP2011085925A (en) * 2009-10-15 2011-04-28 Samsung Mobile Display Co Ltd Organic light-emitting display device and method of fabricating the same
JP2014067047A (en) * 2013-11-08 2014-04-17 Seiko Epson Corp Light emission device and electronic apparatus
JP2016040596A (en) * 2014-08-12 2016-03-24 上海和輝光電有限公司Everdisplay Optronics (Shanghai) Limited Organic electroluminescence display
JP2015166872A (en) * 2015-04-07 2015-09-24 セイコーエプソン株式会社 Light emission device and electronic apparatus

Similar Documents

Publication Publication Date Title
US9618816B2 (en) Array substrate for liquid crystal display device and method of fabricating the same
US8743025B2 (en) Electro-optical device, method of manufacturing the same, and electronic apparatus
US9030637B2 (en) In-plane switching mode liquid crystal display and method for fabricating the same
US8846458B2 (en) Array substrate for in-plane switching mode liquid crystal display device and fabricating method thereof
US20190157619A1 (en) Flexible organic light emitting display device
JP5218604B2 (en) Display device and electronic device
KR101499234B1 (en) Organic light emitting device, method of manufacturing the same and shadow mask therefor
US8106577B2 (en) Organic EL device and electronic apparatus
KR101407309B1 (en) Organic electro-luminesence display panel and manufacturing method of the same
KR100626007B1 (en) TFT, manufacturing method of the TFT, flat panel display device with the TFT, and manufacturing method of flat panel display device
US9312277B2 (en) Array substrate for display device and method of fabricating the same
JP4044014B2 (en) Thin film transistor for active matrix organic electroluminescence device
JP3901127B2 (en) Electro-optical device and electronic apparatus
US6570639B1 (en) Liquid crystal display device including shield pattern and color filter coexist together in the vicinity of the inlet
JP3999205B2 (en) Active matrix organic light emitting display device and method for manufacturing the same
JP4012908B2 (en) Organic electroluminescence display
JP3915806B2 (en) Electro-optical device and electronic apparatus
JP3917132B2 (en) Organic electroluminescent device and manufacturing method thereof
US6476419B1 (en) Electroluminescence display device
US7858974B2 (en) Organic light-emitting display panel and method of manufacturing the same
JP5269291B2 (en) Thin film transistor display panel
KR100493353B1 (en) Active matrix type display device
US7952677B2 (en) Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same
US9379170B2 (en) Organic light emitting diode display device and method of fabricating the same
JP4472961B2 (en) Display device substrate, liquid crystal display device, and method of manufacturing liquid crystal display device

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20070514

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080610

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110428

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110510

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110622

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110719

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110824

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110913

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120207