JP2685079B2 - Matrix display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a matrix display device which performs interlaced scanning of 2: 1, and provides a device capable of displaying a large capacity by reducing the number of elements of a bus driver of the matrix display device. With a scan bus and a data bus arranged orthogonally,
In a matrix display device in which display elements are provided at the intersections via switching elements, two display elements arranged adjacent to each other in the extending direction of the scan bus are grouped, and the data writing terminals of the respective switching elements are the same. Connected to the data bus, the ON / OFF terminals are connected to the odd-numbered scan bus and the even-numbered scan bus, respectively, to form a scan driver for driving the scan bus and a data driver for driving the data bus by a signal from the control means. Data is alternately written to the odd-numbered scan bus and the even-numbered scan bus for each frame, and the interlaced scan driving is performed.

[Industrial applications]

The present invention relates to a matrix display device, and more particularly to a matrix display device suitable for large capacity display.

In recent years, large-sized monochrome liquid crystal displays and plasma displays have been put to practical use in portable word processors, laptop personal computers, etc., and the number of dots has reached 640 × 400. Is developing a large-sized liquid crystal display device capable of color display. In order to increase the capacity of the display device, there is a demand for a matrix display device that is large in size, has a low operating frequency, has a simple operating circuit configuration, and is inexpensive.

[Conventional technology]

FIG. 7 shows an example of the configuration of a conventional monochrome matrix display device (liquid crystal display device). The liquid crystal display device in this figure has a liquid crystal panel 70, and this liquid crystal panel 70 is composed of a first substrate 73 and a second substrate 79 with a liquid crystal 78 sealed between them. The scanning bus 71 is provided on the first substrate 73.
And a data bus 72 are provided to intersect each other, and a gate is connected to the scan bus 71, a drain is connected to the data bus 72, and a source is a thin film transistor (TFT) 76 which is a switching element connected to the electrode 77 in the vicinity of the intersection. The second substrate 79 is provided with a counter electrode (not shown). Also, the liquid crystal panel 73
A scan driver 74, a data driver 75, and a control circuit (not shown) for the scan driver 74 are provided outside. In such a liquid crystal display device, one line is sequentially selected by the scan driver 74, and the TFT 76 on that line is turned on.
Every time a line is selected, the data voltage corresponding to the display is applied from the data driver 75 to the liquid crystal 78 via the turned-on TFT 76. Then, data is written in the pixel at the intersection of the selected scan line and data line. And
One screen is displayed when sequential scanning lines are selected and writing of all lines is completed.

The data driver 75 shown in FIG. 7 has a structure as shown in FIG. The data driver 75 shifts the display data D sent serially by the shift register 81 based on the clock signal CK to fetch the display data for one row, and after converting the voltage level by the level conversion circuit 82, Data for one row is simultaneously applied to the data bus. As a result, writing of one row is performed at the same time.

[Problems to be solved by the invention]

Generally, in a display device such as a CRT, one screen needs to be rewritten at 40 to 60 Hz to prevent flicker.
Therefore, as shown in FIGS. 9A to 9C, the operation time required for one horizontal synchronizing signal is 65 μs for a liquid crystal panel of 320 × 200 dots, and a liquid crystal panel of 640 × 400 dots. For example, the liquid crystal panel of 1120 × 750 dots becomes 40 μs and becomes 30 μs, which becomes shorter as the number of dots (the number of lines) in the scanning direction increases. As a result, the transfer rate of display data increases in proportion to the increase of the display capacity. Become. Then, the dot clock in a liquid crystal panel of about 1000 × 800 dots reaches 50 MHz, which exceeds the capability of the data driver. That is, when the capacity of the liquid crystal panel increases, one conventional CMOS IC cannot operate, and the number of ICs has to be increased. As a result, the number of parts and power consumption increase. There is a problem that it is difficult to realize a display device having a capacity.

The present invention has been made to solve the above-mentioned problems in the matrix display device, and an object of the present invention is to provide a large-capacity matrix display device by reducing the number of data drivers and the operating frequency of the data drivers. I am trying.

[Means for solving the problem]

The structure of the matrix display device of the present invention which achieves the above object is shown in FIG. The matrix display device in the figure includes a scan bus and a data bus arranged orthogonally to each other, and in the matrix display device in which a display element is provided at an intersection of the scan bus and the data bus, the scan bus and the data bus are adjacent to each other in the extending direction of the scan bus 1. The display elements 7a and 7b arranged in pairs are connected to each switching element 6 with the data writing terminal connected to the same data bus 2, and the ON / OFF terminals are connected to the odd-numbered scan bus 1o and the even-numbered scan, respectively. A scan driver 4 for driving the scan bus 1 and a data driver 5 for driving the data bus 2 which are connected to the bus 1e and which are driven by a signal from the control means 3 have odd-numbered scan buses and even-numbered scan buses for each frame. It is characterized in that the interlaced scanning drive for writing data alternately is performed.

(Operation)

According to the matrix display device of the present invention, two adjacent dots arranged in one display line are connected to the common data bus and the odd-numbered and even-numbered scan buses, respectively. Either the odd-numbered bus or the even-numbered bus is alternately performed,
In one horizontal scanning period, only half the dots of one display line are written, and two frames form one screen.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2-1 shows the configuration of an embodiment of the matrix display device of the present invention. Scanning buses SO ₁ , SE ₁ , SO ₂ , SE ₂ , ... arranged orthogonally on one substrate of the liquid crystal panel 20.
SO _m , SE _m and data buses X ₁ , X ₂ , ... X _n are provided, and odd-numbered scan buses SO ₁ , SO ₁ , ... SO _m are connected to the first scan driver 21 and even-numbered The scan buses SE ₁ , SE ₂ , ... SE _m are connected to the second scan driver 22, and the data buses X ₁ , X ₂ , ... X _n are connected to the data driver 23. Scan bus SO ₁ , SE ₁ , SO
₂ , SE ₂ , ... SO _m , SE _m, and a pixel electrode is provided near the intersection of the data bus X ₁ , X ₂ , ... X _n via a TFT 25 which is a switching element. A liquid crystal cell 24 between a counter electrode (not shown) provided on the other counter substrate constitutes each pixel. Further, the odd-numbered liquid crystal cells 24a and the even-numbered liquid crystal cells 24b, which are arranged adjacent to each other in the extending direction of the scan bus, are paired and two TFTs 25 connected to the liquid crystal cells 24a and 24b, respectively. Drains connected to the same data bus, gates on odd scan bus
SOi and even-numbered scan buses SEi (i is a natural number) are separately connected.

The first scanning driver 21, the second scanning driver 22, and the data driver 23 are connected to a control circuit 26 to which a horizontal synchronizing signal and a vertical synchronizing signal are input, and from this control circuit 26, the first scanning driver 21 and the second scanning driver 21 are connected. The scan driver control signal is output to the scan driver 22, and the data driver control signal is output to the data driver 23. Further, the output control signal OE is output from the control circuit 26 to the first scan driver 21 and the clock frequency division selection circuit 27 to which the clock signal is input, and the output control signal OE is inverted by the inverter 29. It is also output to the 2-scan driver 22. Scan data Di to LCD panel 20
n is a data driver 23 via a flip-flop circuit 28
Is input to The output of the clock division selection circuit 27 is input to the flip-flop circuit 28 and the data driver 23.

Next, the operation of the apparatus of the embodiment configured as described above will be explained using the waveform chart 3-1.

The first scan driver 21 and the second scan driver 22 that scan the even lines and the odd lines are controlled by the output control signal OE, except that the control circuit 26 sequentially scans line by line in the same manner as a normal scan driver. Controlled by. The control circuit 26 generates a normal control signal for the first scan driver 21 and the second scan driver 22, and divides the vertical synchronizing signal by two to output the output control signal OE as shown in FIG. 3 (C). It is generated and input to the first scan driver 21, and the output control signal OE is inverted by the inverter 29 and input to the second scan driver 22. In this embodiment, the first scan driver 21 outputs the scan signal when the output control signal OE is at the high level, and the second scan driver 22 outputs the scan signal when the output control signal OE is at the low level. If so, the control circuit 26 causes the first scan driver 21 to output a scan signal in odd-numbered frames and the second scan driver 22 to output a scan signal in even-numbered frames, for example.

As shown in FIG. 3A, the clock division selection circuit 27 divides the clock signal to generate the signals CLK1 and CLK2 for sampling the even-numbered and odd-numbered display data. Then, the clock division selection circuit 27, for example,
The signal CLK1 is output when the output control signal OE input from the control circuit 26 is high level 1, and the signal CLK2 is output when the output control signal OE is low level 0.

Display data Din input to the flip-flop circuit 28
Is the signal CKL1 or the signal CL as shown in FIG. 3 (b).
The flip-flop circuit 28 is latched by the rise of K2. Therefore, the signal CKL1 is applied to the flip-flop circuit 28.
When is input, the data in the odd column of one display line is input to the data driver 23 as the display data Dout,
When the signal CKL2 is input to the flip-flop circuit 28, the data in the even column of one display line is input to the data driver 23 as the display data Dout.

In the input display data Din, only the odd-numbered data in the odd-numbered frame is the display data Dout.
Is sent to the data driver 23, and at this time, the first scan driver 21 scans the odd-numbered scan buses SO ₁ , SO ₁ , ..., SO _m and half the data of the display data Din is written in the liquid crystal cell 24a. Similarly, in even frames, only the even-numbered data of the display data Din is sent to the data driver 23 as the display data Dout. At this time, the second scan driver 22 causes the even-numbered scan buses SE ₁ , SE ₂ , ...... SE _m is scanned and the remaining half of the display data Din is written in the liquid crystal cell 24b. FIG. 4-1 shows the operation of the odd-numbered frame in the apparatus of FIG. 2-1. In the odd-numbered frame, the scanning signal is sequentially output from the first scanning driver 21,
No scan signal is output from the second scan driver 22. Therefore, in the liquid crystal cells arranged in one display line, data is written in every other liquid crystal cells 24a as shown by the diagonal lines, and in even frames, the data is written in the liquid crystal cells 24b not shown by the diagonal lines.

In the embodiment described above, the display panel and the peripheral circuit are provided so as to write the even-numbered and odd-numbered data of the display data for each frame, but the even-numbered and odd-numbered data may be written for each line.

An example of this case is shown in FIGS. 2-2 to 4-2. In FIG. 2-2, (1) the liquid crystal panel 20 is connected to the first and second scan drivers 21, 22 and (2) the clock frequency dividing selection circuit 27 is controlled by the signal SEL. Signal SEL
Is a signal which is inverted every time one scanning line is selected and whose polarity is inverted in odd and even frames, as shown in FIG. 3-2. The clock division selection circuit 27 selects the signal CLK1 when the signal SEL is at high level 1 and selects the signal CLK2 when the signal SEL is at low level 0. FIG. 4-2 shows the operation of the odd-numbered frame in FIG. 2-2, and the scanning signals are sequentially output from the first scanning driver 21 as in the above embodiment, but the connection with the panel is different. , SO1, SE2, SO3
.. are simultaneously scanned by the signal SEL, and the odd and even display data are sent to the data driver 23 for each line, and the data are written in the liquid crystal cells indicated by diagonal lines. In the even-numbered frame, data is written in the liquid crystal cell not shown by the diagonal lines.

FIG. 5 shows a constitutional example of a liquid crystal panel of still another embodiment of the present invention. This example is an application of the present invention to a color matrix display device. In the color display device, the RGB dots forming the three primary colors are arranged in the line direction, and the gate of the TFT 51 of each dot is connected to the upper and lower scanning buses SO and SE at every other dot, as in the above-described embodiment. Then, half the pixels may be written in one frame.

Further, in the embodiment shown in FIG. 6, the display element RG of three primary colors is used.
B is arranged in the scanning direction so that three dots in the scanning direction form one color pixel, and the number of scanning buses is as follows: the scanning bus SRO for red odd frames, the scanning bus SRE for red even frames, and green. The scan bus SGO for odd frames, the scan bus SGE for green even frames, the scan bus SBO for blue odd frames, and the scan bus SBE for blue even frames are tripled. In the apparatus of this embodiment, half the data of one color is written in one frame, and one data is written in 6 frames.
Make sure that all screen data is written. That is, 1
In the second frame, data is written in the red odd-numbered dots shown in Fig. 6, in the second frame, the data is written in the green odd-numbered dots shown in, and so on. To form a screen by writing data in the dots in, the dots in the fifth frame, and the dots in the sixth frame. In this case, the number of data drivers can be reduced to 1/6 as compared with the normal case.

〔The invention's effect〕

As described above, according to the present invention, the number of scan drivers is doubled. However, since the scan driver has a simple structure, the operating speed of the data driver is halved when the display capacity is large or in colorization. Since the matrix display device can be realized without increasing the number of drivers in monochrome display and color display, there is an effect that the device configuration is simple and the cost is low. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the matrix display device of the present invention, FIG. 2-1 is an overall block diagram of an embodiment of the matrix display device of the present invention, and FIG. 2-2 is a modification of FIG. 2-1. FIG. 3-1 is an operation waveform diagram of the apparatus shown in FIG. 2-1.
FIG. 3-2 is an operation waveform diagram of the apparatus of FIG. 2-2, FIG.
FIG. 4-2 is a diagram showing the operation of the liquid crystal panel of FIG.
2 is a diagram showing the operation of the liquid crystal panel of FIG. 2-2, FIG. 5 is a configuration diagram of another embodiment of the apparatus of the present invention, and FIG. 6 is a configuration diagram of yet another embodiment of the present invention. FIG. 7 is a configuration diagram of a conventional monochrome matrix display device, FIG. 8 is a configuration diagram of the data driver of FIG. 7, and FIG. 9 is an explanatory diagram showing a change in data transfer rate with an increase in display capacity. 1 ... Scan bus, Io ... Odd scan bus, 1e ... Even scan bus, 2 ... Data bus, 3 ... Control circuit, 4 ... Scan driver, 5 ... Data driver, 6 ...
... switching element, 7a, 7b ... liquid crystal cell, 20 ... liquid crystal panel, 21 ... first scan driver, 22 ... second scan driver, 23 ... data driver, 24, 24a, 25b ... liquid crystal cell, 25 …… TFT, 26 …… Control circuit, 27 …… Clock division selection circuit, 28 …… Flip-flop circuit.

Continuation of the front page (56) References JP-A-63-168690 (JP, A) Patent 2581796 (JP, B2)

Claims (1)

(57) [Claims] 1. A matrix display device comprising a scan bus and a data bus arranged orthogonally to each other, and a display element provided at an intersection of the scan bus and a data bus, and adjacent to each other in the extending direction of the scan bus (1). A set of two display elements (7a, 7b) arranged is connected to the data writing terminal of each switching element (6) to the same data bus (2), and the on / off terminals are odd-numbered scan buses. (1o) and an even-numbered scan bus (1e), and a scan driver (4) that drives the scan bus (1) by a signal from the control means (3) and a data driver that drives the data bus (2) (5) A matrix display device characterized in that an interlaced scan drive for writing data alternately to the odd-numbered scan bus and the even-numbered scan bus for each frame is performed.