JPH08122743A - Video display device - Google Patents

Abstract

PURPOSE: To perform the check inversion driving or column inversion driving of a display panel without applying burden on a driver. CONSTITUTION: Driver units 1, 2 perform the polarity judging processing of video signals R, G and B in a prescribed period, and output an AC video signal. The display panel 3 incorporates a row type gate line, a column type data line, a picture element provided in the cross part of them, a vertical driving circuit and a horizontal driving circuit, etc. The vertical driving circuit scans the gate line sequentially at every vertical period, and selects the picture element. The horizontal driving circuit samples the AC video signal to the data line, and writes the AC video signal on a selected picture element. A pair of driver units 1, 2 perform polarity inversion processing on common video signals R, G and B, separately. A timing generator 4 outputs plural AC video signals (R1, G1 and B1), (R2, G2 and B2) with different phases by controlling the driver units 1, 2. The horizontal driving circuit incorporated in the display panel 3 samples one of the plural AC video signals with different phases to the data line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device using an active matrix type liquid crystal display panel or the like as a display device. More specifically, the present invention relates to an AC driving technique for a liquid crystal display panel.

[0002]

2. Description of the Related Art FIG. 9 shows a general structure of a conventional active matrix type liquid crystal display panel. It has row-shaped gate lines X and column-shaped data lines Y. A pixel 101 is provided at the intersection of both lines. Each pixel 101 includes a liquid crystal cell LC, a storage capacitor CS connected in parallel with the liquid crystal cell LC, and a thin film transistor TR for switching and driving the liquid crystal cell LC. Each liquid crystal cell LC is made of liquid crystal held between the pixel electrode and the counter electrode. Each pixel electrode has a corresponding thin film transistor TR
While the opposite electrode is connected to a predetermined reference voltage VCO
M is applied. This liquid crystal display panel has a built-in drive circuit and includes a vertical drive circuit 102 and a horizontal drive circuit 103. The vertical drive circuit 102 sequentially scans the gate line X for each vertical period (one field period, 1F) to select the pixel 101. On the other hand, the horizontal drive circuit 103 sequentially samples the video signals R, G, B on the data line Y every horizontal period (1H), and writes the video signal to the selected pixel 101. The vertical drive circuit 102 sequentially transfers the externally input vertical start pulse VST according to the two-phase clock signals VCK1 and VCK2, and scans the gate line Y described above. Horizontal drive circuit 103
Performs the above-described sampling operation by sequentially transferring a horizontal start pulse HST externally input according to two-phase clock signals HCK1 and HCK2. This liquid crystal display panel is a full-color type, and video signals of RGB three primary colors are input from the outside via a video line 104. The three video lines 104 are connected to the corresponding gate lines Y via transmission gate elements TG. The individual transmission gate elements TG are sequentially controlled to be opened and closed by the horizontal drive circuit 103,
Sequential sampling of the video signals R, G, B for the data line Y described above is performed.

FIG. 10 is a block diagram showing a general structure of a video display device incorporating the liquid crystal display panel shown in FIG. A decoder 201 is provided, which decodes a video signal to generate video signals R, G, B of the three primary colors, and separates a sync signal SYNC. A driver 202 is connected to the decoder 201, which performs polarity inversion processing on an original video signal at a predetermined cycle to generate alternating video signals R, G, B.
Is output to the display panel 203. Further, it is provided with a timing generator 204, which operates in response to the synchronizing signal SYNC, and which has HST, HCK1, H for the display panel 203.
CK2, VST, VCK1 and VCK2 are supplied. Through these signals, operation timing control of the vertical drive circuit and the horizontal drive circuit built in the display panel 203 is performed. Further, the alternating signal FRP is supplied to the driver 202 to control the timing of the polarity inversion processing of the video signal described above.

Generally, when driving the liquid crystal display panel 203, AC driving is performed in order to prevent deterioration of the liquid crystal. FIG.
In the example of 1, the horizontal synchronization signal HSYN having a period of 1H is used.
According to C, the timing generator 204 supplies the AC signal FRP having a 2H cycle to the driver 202. As a result, the polarities of the video signals R, G, B are inverted every 1H with respect to the reference potential VCOM, and so-called 1H inversion driving is performed.

On the other hand, in the example shown in FIG. 12, the timing generator 204 supplies the alternating signal FRP of 2F cycle to the driver 202 in response to the vertical synchronizing signal VSYNC of 1F cycle. In response, driver 202
The polarity-inverted alternating video signals R, G, B are output for each F. In this 1F inversion drive, the polarity is inverted every 30 Hz, and 15
1H inversion drive is mainly used because the Hz component appears and causes flicker.

[0006]

FIG. 13 is a graph showing the change in pixel potential that occurs when the AC inversion drive method is used. Focusing on one pixel, the video signal is written according to the operation of the vertical drive circuit and the horizontal drive circuit,
After that, it is held for a period of 1F. In the next field, the video signal whose polarity is inverted is written and is also held only for the period of 1F. That is, in the normal case shown in (A),
The pixel potential written in a certain pixel is held until the gate line is selected in the next field.

By the way, as shown in FIG. 9, the gate line X and the data line Y have many intersections on the same plane in the liquid crystal display panel, but with the increase in size and definition of the panel, The coupling between the data line Y and the gate line X is a problem. The state in which coupling has occurred is shown in (B). As the liquid crystal display panel becomes larger and finer, in the case of 1H inversion driving, the polarity of a plurality of data lines Y intersecting the same gate line X is inverted every 1H. The potential changes of all the data lines Y jump into one gate line X all at once, and this influence further affects the pixel potential. Therefore, as shown in (B), the pixel potential is 1H.
Since it vibrates finely in a cycle and the effective voltage applied to the liquid crystal decreases, problems such as insufficient contrast occur.

In order to prevent the fluctuation of the pixel potential which changes minutely in a 1H cycle, an AC drive in which the polarity is inverted every data line has been proposed. For example, as shown in FIG. 14, a positive video signal is sampled on the data line Y1, and a negative video signal is sampled on the data line Y2.
A positive video signal is sampled on the data line Y3. A combination of this polarity inversion for each data line and the above-mentioned 1F inversion results in so-called column inversion drive, which is disclosed in, for example, Japanese Patent Publication No. 4-224486. Also, by combining the polarity inversion for each data line and the 1H inversion, so-called checkered inversion drive becomes possible. In the Kamura inversion drive and the checkered inversion drive, since the potential levels sampled in the respective data lines have opposite polarities alternately, the potential change is canceled on one gate line, and the above-mentioned coupling can be significantly suppressed.

FIG. 15 shows the polarity inversion timing of each data line Y1, Y2, Y3 in the case of checkered inversion drive or column inversion drive. In the checkered inversion drive, the polarities of the data lines Y1, Y2 and Y3 are inverted every 1H. In case of column inversion, each data line Y1, Y
The potentials of 2 and Y3 are inverted every 1F.

Generally, in a video display device for displaying a video signal, as shown in FIG. 10, a composite video signal, Y /
A video signal such as a C signal is converted by a decoder 201 into video signals R, G, B for each of the three primary colors. The driver 202 inverts and amplifies the video signals R, G, B and inputs them to the liquid crystal display panel 203. When performing column inversion or checkered inversion with such a configuration, it is necessary for the driver 202 to perform high-speed inversion processing at intervals of several ns to several hundreds of ns. That is, the polarity inversion process of the video signal must be performed in synchronization with the sampling timing of each data line. However, in reality, the load of the data line and the driver 20
Due to the driving ability of No. 2 and the like, high speed inversion with such a short period is impossible, and column inversion or checkered inversion is difficult in an image display device that displays an image signal. Although the decoder 201 and the driver 202 are configured as separate ICs in the above description, the decoder 201 and the driver 202 can be integrated into one chip.

[0011]

In view of the above-mentioned problems of the prior art, it is an object of the present invention to realize checkered inversion or column inversion in a video display device incorporating an active matrix type liquid crystal display panel or the like. The following measures have been taken in order to achieve this object. That is, the video display device according to the present invention has a driver means, a display panel, and a timing means as a basic configuration. The driver means performs polarity inversion processing of the video signal at a predetermined cycle and outputs an alternating video signal. The display panel is a line-shaped gate line,
It is provided with column-shaped data lines, pixels provided at the intersections of the two, and the like. It also has a vertical drive circuit and a horizontal drive circuit. The vertical driving circuit sequentially scans the gate line for each vertical period to select a pixel. The horizontal driving circuit sequentially samples the alternating video signal on the data line every horizontal period and writes the alternating video signal to the selected pixel.
The timing means controls the timing of the polarity reversal process of the driver means and the operation timing of the vertical drive circuit and the horizontal drive circuit.
The driver means has a plurality of driver units that individually perform polarity inversion processing on common video signals. The timing means controls each driver unit to output a plurality of alternating video signals having different phases. The horizontal driving circuit samples any one of a plurality of alternating video signals having different phases on each data line.

For example, the driver means has a pair of driver units. In this case, the timing means controls each driver unit so that the phases are 180 degrees relative to each other.
° Output a pair of different AC video signals. The horizontal driving circuit alternately samples one of the pair of alternating video signals for each data line. When performing color display, each driver unit supplies three types of alternating video signals corresponding to the three primary colors of RGB. The horizontal driving circuit simultaneously samples the three types of alternating video signals with respect to three data lines corresponding to RGB three primary colors. In one aspect of the present invention, the driver means supplies an alternating video signal whose polarity is inverted every horizontal period.
In another aspect of the present invention, the driver means supplies an alternating video signal whose polarity is inverted every vertical period.

[0013]

According to the present invention, for example, a pair of driver units are used to separately invert the polarity of a common video signal, and a pair of alternating video signals whose phases are different from each other by 180 ° are supplied to the display panel. On the display panel side, a horizontal drive circuit alternately samples alternating video signals of opposite phases for each data line. Therefore, it is possible to sample the video signal whose polarity is inverted for each data line. By combining this sampling operation with the usual 1H inversion, so-called checkered inversion drive becomes possible. Alternatively, so-called column inversion driving can be performed by combining with the normal 1F inversion. In other words, the driver unit side may perform the polarity reversal process for each 1H or 1F according to the control of the timing generator, and does not need to perform the high-speed reversal process synchronized with the sampling timing.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. As shown in the figure, the present video display device comprises a driver means composed of a pair of driver units 1 and 2, a color liquid crystal display panel 3 of an active matrix type, a timing means composed of a timing generator 4, and a decoder 5. The decoder 5 decodes the externally input video signal to generate the video signals R, G, B of the three primary colors and separates the sync signal SYNC. The driver means including a pair of driver units 1 and 2 performs polarity inversion processing of the video signals R, G, B at a predetermined cycle (1H or 1F) and outputs an alternating video signal. Display panel 3
Has row-shaped gate lines, column-shaped data lines, and pixels provided at the intersections of the two. It also has a vertical drive circuit and a horizontal drive circuit. Vertical drive circuit is 1F
The gate line is sequentially scanned every time and a pixel is selected. The horizontal drive circuit sequentially samples the alternating video signal on the data line every 1H and writes the alternating video signal to the selected pixel. The timing generator 4 uses the synchronization signal SYNC.
And supplies the alternating signal FRP to the pair of driver units 1 and 2 to control the timing of the polarity inversion process. At the same time, HST, HCK1, CHK2
VST, VCK1, VCK2, etc. are supplied to the display panel 3 to control the operation timing of the vertical drive circuit and the horizontal drive circuit.

As a feature of the present invention, the driver means has a plurality of driver units 1 and 2 for individually performing polarity inversion processing on common video signals R, G and B. The timing generator 4 controls the driver units 1 and 2 to output a plurality of alternating video signals having different phases.
The horizontal driving circuit samples any one of a plurality of alternating video signals having different phases on each data line. Specifically, the first driver unit 1 uses the original video signals R, G,
Inversion processing is performed on B to output alternating video signals R1, G1, B1. Similarly, the second driver unit 2 reverses the polarities of the original video signals R, G and B to generate the alternating video signals R2 and G.
2 and B2 are output. R1, G1, B1 and R2, G2
B2 is 180 ° out of phase with each other. In this case, the horizontal drive circuit built in the display panel 3 alternately samples the alternating video signals of opposite phases for each data line.

This example is an example in which six video lines to be input to the display panel 3 are provided and three adjacent pixels are combined to realize checkered inversion drive or column inversion drive. The original video signals R, G, B output from the decoder 5 are input to the first driver unit 1 and the second driver unit 2, and the alternating video signal R suitable for driving the polarity inversion of the liquid crystal, respectively.
1, G1, B1 and R2, G2, B2 are created. At this time, the polarity of the alternating signal FRP supplied from the timing generator 4 to the driver units 1 and 2 is inverted. That is, the FR input to the first driver unit 1
FRP input to the second driver unit 2 with respect to P
Are inverted by the inverter 6, so they are controlled to have opposite phases.

FIG. 2 is a block diagram showing a specific structural example of the active matrix type color liquid crystal display panel 3 shown in FIG. As shown in the figure, the display panel has row-shaped gate lines X and column-shaped data lines Y, and pixels 31 are provided at the intersections of the two. The pixel 31 includes a liquid crystal cell LC, a storage capacitor CS, and a thin film transistor TR. Further, it is provided with six video lines 32, and a total of six alternating video signals R1, G1, B1, R2, G supplied from the pair of driver units 1 and 2 are provided.
Accept B2 and B2 respectively. Each data line Y is connected to a predetermined video line 32 via a transmission gate element TG. In addition to the above configuration,
The display panel includes a vertical drive circuit 33 and a horizontal drive circuit 34. The vertical drive circuit 33 operates in response to VST, VCK1, VCK2, etc. supplied from the timing generator, and operates the gate line X every vertical period (1F).
Are sequentially scanned to select the pixels 31 row by row. On the other hand, the horizontal drive circuit 34 operates in response to HST, HCK1 and HCK2 supplied from the timing generator, and the transmission gate elements T are sequentially arranged every horizontal period (1H).
G is opened and closed to generate alternating video signals R1, G1, B1,
R2, G2, and B2 are sequentially sampled on the corresponding data line Y, and the alternating video signal is written in the pixels 31 for one selected row.

As shown, one of the alternating video signals R
1, G1 and B1 are sampled on the first three data lines Y. The other opposite-phase AC video signal R2, G
2, B2 are sampled on the next three data lines Y. In this way, alternating video signals R1, G1, B1 and R2, G2, B2 having 180 ° opposite phases are sampled alternately on every three data lines Y. In other words, with three pixels 31 as one group, video signals of opposite phases are written alternately for each group. By combining this with 1H inversion, checkered inversion drive is possible. Or 1F
Column inversion drive becomes possible by combining with inversion. Therefore, unlike the prior art, the coupling that occurs when the polarities of all the data lines Y are simultaneously reversed along the same gate line is canceled out, and the problem of lowering the contrast does not occur. In the above-described embodiment, the video line 32
, But the number of pixels 31 to be combined is set to three, but the present invention is not limited to this. For example, nine video lines 32 may be provided, three combinations of three pixels may be formed, and three driver units may be prepared. In this case, the timing of the polarity reversal processing in each driver unit is shifted by 120 ° and three alternating video signals with different phases are output. On the other hand, the horizontal driving circuit can obtain the same effect by sampling any one of the plurality of alternating video signals having different phases on each data line. However, since the color liquid crystal display panel includes three pixels of RGB, the above-mentioned combination of 3 dots is most easily realized. In the case of a mono-color (black and white) liquid crystal display panel, the number of pixels to be combined may be arbitrary.

FIG. 3 shows a special case of the display panel 3 shown in FIG. 2, which employs a so-called three-pixel simultaneous sampling system. As shown in the figure, the display panel 3 has a gate line X along the row direction, a data line Y along the column direction, and pixels R of three primary colors arranged at the intersections of the two.
It has G and B. The pixels R, G, B are arranged at a predetermined pitch along the row direction. In addition, horizontal switches HSW1 and HSW connected to one end of the data line Y in units of three
It has SW2, ..., HSWn-1, and HSWn. These horizontal switches HSW select three data lines Y simultaneously in units of three lines, and alternately select three types of alternating video signals (R1, G1, B1) and (R2, G2, B2) divided into three primary colors. Write to pixels R, G, B. Therefore, these horizontal switches HSW correspond to three transmission gate elements TG shown in FIG. In this example, HSW1
One of the alternating video signals R1, G1, B1 is written in the three pixels R, G, B via. The AC image signals R2, G2, B2 of the other opposite phase are written in the three pixels R, G, B via the next HSW2. In this way, 3
Alternating alternating video signals are written alternately for each group of pixels.

FIG. 4 schematically shows the polarities of the alternating video signals written in the respective pixels shown in FIG. In this example, 1H inversion is adopted, and so-called checkered inversion drive is performed in units of three pixels. Focusing on the first pixel row, a video signal of positive polarity is written in a set of three pixels, and a video signal of negative polarity is written in a set of the next three pixels. In this way, video signals of opposite polarities are alternately written in units of three sets. Similarly, in the next pixel row, video signals of opposite polarities are alternately written in units of groups of three pixels. However, since the 1H inversion drive is performed, the polarity is inverted as compared with the pixels in the first row. In this way, checkered inversion drive is performed in units of groups of three pixels. Focusing on each pixel row, the potentials of the positive and negative polarities are mixed in a plurality of data lines intersecting one gate line. The fluctuations are canceled out, the coupling via the gate line is suppressed, and the potential fluctuation of the video signal written in each pixel does not occur.

FIG. 5 shows an example in which alternating video signals of opposite phases are alternately written in units of groups of three pixels. In this case, 1F inversion driving is performed. Therefore,
In the same field, video signals of the same polarity are written in pixels of three columns. For example, the video signals of positive polarity are written in the pixels in the first three columns, and the video signals of negative polarity are written in the pixels in the next three columns. This polarity is reversed in the next field. Therefore, as shown in the figure, so-called column inversion drive is performed in units of three pixel columns. Also in this case, when focusing on one pixel row, the potentials of the plurality of data lines intersecting the same gate line are mixed with positive polarity and negative polarity, and the variation of the potential level is canceled out as a whole, Coupling can be suppressed.

FIG. 6 is a block diagram showing another embodiment of the video display device according to the present invention. Basically, it is the same as the previous embodiment shown in FIGS. 1 and 2, and corresponding parts are given corresponding reference numerals to facilitate understanding. The difference lies in the connection method of the six video lines 32. In this example, the alternating video signal R1 is supplied to the first data line Y. The video signal G2 having the opposite phase is supplied to the second data line Y. Video signal B on the third data line Y
1 is supplied. The video signal R2 having the opposite phase is supplied to the fourth data line Y. The video signal G1 is supplied to the fifth data line Y. The video signal B2 having the opposite phase is supplied to the sixth data line Y. In this way, the phase of the video signal supplied to each data line Y is reversed for each line. That is, in the previous embodiment shown in FIG. 2, video signals of opposite polarities are written in units of three pixels, whereas in the present embodiment, video signals of opposite polarities are written for each pixel. Become.

FIG. 7 schematically shows the polarities of the video signals written in the respective pixels when the checkered pattern inversion driving is carried out in the embodiment shown in FIG. As can be seen from the figure, complete checkered inversion drive is performed for each pixel.

FIG. 8 schematically shows the polarity of the video signal written in each pixel when the column inversion drive is performed in the structure shown in FIG. As shown in the figure, complete column inversion drive is performed for each column.

[0025]

As described above, according to the present invention, a plurality of driver units for separately reversing the polarity of a common video signal are provided, and a plurality of alternating video signals having different phases are supplied to the display panel. are doing. A horizontal driving circuit built in the display panel samples any one of a plurality of alternating video signals having different phases on each data line.
As a result, checkered inversion drive and column inversion drive can be realized without imposing a burden on the drive capability of the driver unit. Therefore, when driving a large, high-definition display panel,
There is an effect that it is possible to realize a high-contrast and high-quality display without causing the conventional defect that the contrast is lowered due to the coupling from the data line. In addition, since it is not subjected to coupling, it is possible to remove the residual DC component due to its variation.
It is expected that the reliability will be improved and the uniformity of the image on the entire screen will be improved.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a first embodiment of a video display device according to the present invention.

FIG. 2 is a circuit diagram showing a specific example of a display panel 3 incorporated in FIG.

FIG. 3 is a block diagram showing a special example of the display panel shown in FIG.

FIG. 4 is a diagram schematically showing checkered inversion driving performed in the video display device shown in FIG.

FIG. 5 is a diagram schematically showing column inversion driving.

FIG. 6 is a circuit diagram showing a display panel incorporated in a second embodiment of the video display device according to the present invention.

FIG. 7 is a schematic diagram showing checkered inversion driving performed in a second embodiment.

FIG. 8 is a diagram schematically showing column inversion driving.

FIG. 9 is a circuit diagram showing an example of a conventional display panel.

FIG. 10 is a block diagram showing an example of a conventional video display device.

FIG. 11 is a timing chart showing conventional 1H inversion driving.

FIG. 12 is a timing chart showing conventional 1F inversion driving.

FIG. 13 is a graph showing changes in pixel potential.

FIG. 14 is a circuit diagram for explaining the problems of the conventional driving method.

FIG. 15 is a waveform diagram for explaining the problems of the conventional driving method.

[Explanation of symbols]

 1 1st driver unit 2 2nd driver unit 3 display panel 4 timing generator 5 decoder 31 pixel 32 video line 33 vertical drive circuit 34 horizontal drive circuit X gate line Y data line

Claims (5)

[Claims] 1. A driver means for performing polarity inversion processing of a video signal and outputting an alternating video signal at a predetermined cycle, a row-shaped gate line, a column-shaped data line, a pixel provided at an intersection of both, and one vertical. A vertical drive circuit that sequentially scans a gate line for each period to select a pixel, and a horizontal drive circuit that sequentially samples the alternating video signal to a data line and writes the alternating video signal to the selected pixel every horizontal period. An image display device comprising: a display panel having: and a timing means for controlling the timing of polarity reversal processing of the driver means and the operation timing control of the vertical drive circuit and the horizontal drive circuit, wherein the driver means is common. It has a plurality of driver units for individually performing polarity inversion processing on the video signals, and the timing means controls each driver unit to mutually To output a plurality of alternating video signals having different phases, the horizontal driving circuit, a video display device, characterized in that for sampling any one of the phase of different AC video signal to the data lines. 2. The horizontal drive circuit, wherein the driver means has a pair of driver units, and the timing means controls each driver unit to output a pair of alternating video signals whose phases are different from each other by 180 °. The video display device according to claim 1, wherein one of the pair of alternating video signals is alternately sampled for each data line. 3. Each driver unit supplies three types of AC video signals corresponding to RGB three primary colors, and the horizontal drive circuit supplies the three types of AC video signals to three data lines corresponding to RGB three primary colors. The video display device according to claim 1, wherein simultaneous sampling is performed. 4. The video display device according to claim 1, wherein the driver means supplies an alternating video signal whose polarity is inverted every horizontal period. 5. The video display device according to claim 1, wherein the driver means supplies an alternating video signal whose polarity is inverted every vertical period.