CN212084637U

CN212084637U - Display screen structure capable of saving power consumption

Info

Publication number: CN212084637U
Application number: CN202020501249.1U
Authority: CN
Inventors: 熊克; 谢建峰
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2020-04-08
Filing date: 2020-04-08
Publication date: 2020-12-04
Anticipated expiration: 2030-04-08

Abstract

The utility model discloses a display screen structure of province consumption, include: the pixel structure comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, six data lines and three source lines; the pixel unit comprises a plurality of sub-pixels, the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels, the sub-pixels of each pixel unit are divided into six rows of sub-pixel pairs, each row of sub-pixel pair comprises two rows of sub-pixels, and each row of sub-pixels comprises an upper gate line and a lower gate line; a data line is arranged between each column of sub-pixel pairs, each data line is connected with a TFT switch, six TFT switches are formed in total, and the output end of each TFT switch is connected with the data line; the input ends of the TFT switches are respectively connected with the three source lines one by one; each row of sub-pixels comprises an upper gate line and a lower gate line, and each data line is used for connecting the two sub-pixels in each row of pixels. The technical scheme reduces the number of source lines and saves the power consumption of a pure color picture.

Description

Display screen structure capable of saving power consumption

Technical Field

The utility model relates to a display screen field especially relates to a display screen structure of province consumption.

Background

The design of narrow-frame and full-screen display screens has become mainstream, with the wide popularization of display screens, the ratio of the initial generation iPhone screen in 2007 is only about 50% from the aspect of screen ratio, and in the following years, the ratio of the mobile phone screen is continuously improved, but the improvement range is not large. In the existing display screen, the Y-axis length of a driving unit is an important factor influencing the overall screen or the narrow-frame screen. The existing display screen is that one Source Line (Source Line) of a driving unit (IC) corresponds to one Data Line (Data Line) in a plane, and one Data Line of the display screen controls one sub-pixel, so that the number of the Source lines is excessive, the Y axis of the driving unit cannot be reduced, the power consumption of the display screen is increased, and the manufacturing cost of the driving unit is increased.

SUMMERY OF THE UTILITY MODEL

Therefore, it is desirable to provide a display panel structure with reduced power consumption, which can greatly reduce the number of source lines and reduce the manufacturing cost of the driving unit.

To achieve the above object, the present invention provides a display screen structure capable of saving power consumption, including: the pixel structure comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, six data lines and three source lines;

the pixel unit comprises a plurality of sub-pixels, the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels, the sub-pixels of each pixel unit are divided into six rows of sub-pixel pairs, and each row of sub-pixel pair comprises two rows of sub-pixels;

a data line is arranged between each column of sub-pixel pairs, each data line is connected with a TFT switch, the total number of the TFT switches is six, the output ends of the TFT switches are connected with the data lines, all the TFT switches are divided into two groups, the TFT switches are positioned at odd number positions and divided into one group, and the TFT switches are positioned at even number positions and divided into the other group according to the column sequence;

one Demux line is connected with the grid electrodes of one group of TFT switches of each pixel unit, the other Demux line is connected with the other group of TFT switches of each pixel unit and the grid lines, and the input ends of the three TFT switches of each group are respectively connected with the three source lines one by one;

each row of sub-pixels comprises an upper gate line and a lower gate line, each data line is used for connecting the two sub-pixels in each row of pixels, and the two sub-pixels connected by each data line are respectively connected with the data line through one of the two gate lines in the row.

Further, one data line connects two subpixels in one subpixel pair, respectively.

Furthermore, the input ends of the TFT switch of the first column sub-pixel pair and the TFT switch of the fourth column sub-pixel pair are respectively connected with the first source line;

the input ends of the TFT switch of the second column of sub-pixel pairs and the TFT switch of the fifth column of sub-pixel pairs are respectively connected with a second source line;

the inputs of the TFT switches in the third column of pairs of sub-pixels and the TFT switches in the sixth column of pairs of sub-pixels are connected to a third source line, respectively.

Further, the display device further comprises a driving unit which is connected with the plurality of source lines.

Further, the plurality of sub-pixels are arranged in an array in sequence in the manner of R, G, B.

Different from the prior art, the above technical solution greatly reduces the number of source lines, provides a better solution for reducing the length of the driving unit, and this embodiment also provides a novel implementation solution for realizing a full panel. In addition, the pixel connection mode provided by the method is matched with a special time sequence, so that the purpose of saving the power consumption of the pure color picture of the display screen can be achieved.

Drawings

Fig. 1 is an internal structure diagram of a display screen structure with power consumption saving according to a first embodiment of the present invention;

fig. 2 is a timing diagram of a power-saving display screen structure according to a first embodiment of the present invention;

fig. 3 is an internal structure diagram of a display screen structure with power consumption saving according to the second embodiment;

fig. 4 is a timing diagram of the display screen structure with power saving according to the second embodiment.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1 to 4, a display panel structure with reduced power consumption of the present embodiment includes: the pixel structure comprises a plurality of pixel units and two Demux lines (Demux1 and Demux2), wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines (G1, G2, G3 and G4 …), six data lines (D1, D2 and D3 … D6) and three source lines (S1, S2 and S3). The pixel unit comprises a plurality of sub-pixels, and the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels. The sub-pixels of each pixel unit are divided into six columns of sub-pixel pairs, and each column of sub-pixel pair comprises two columns of sub-pixels. A data line is arranged between each column of sub-pixel pairs, each data line is connected with a TFT (Thin Film Transistor) switch, the total number of the TFT switches is six, and the output end of each TFT switch is connected with the data line. All TFT switches are divided into two groups, in column order, in the odd positions (on D1, D3, D5) into one group, and in the even positions (on D2, D4, D6) into another group. One Demux line is connected with the grid electrode of one group of TFT switches of each pixel unit, the other Demux line is connected with the other group of TFT switches of each pixel unit and the grid electrode line, and the input ends of the three TFT switches of each group are respectively connected with the three source lines one by one. Each row of sub-pixels comprises an upper gate line and a lower gate line, each data line is used for connecting the two sub-pixels in each row of pixels, and the two sub-pixels connected by each data line are respectively connected with the data line through one of the two gate lines in the row.

The technical scheme can reduce the number of Source lines (Source lines) of a driving unit (IC) (less than that of the conventional Demux or HSD), so that the IC becomes narrower, and the lower boundary (Border) of the display screen is reduced. In addition, the pixel connection mode provided by the method is matched with a special time sequence, so that the purpose of saving the power consumption of the pure color picture of the display screen can be achieved.

In this application (first and second embodiments), the display panel structure further includes a driving unit connected to the plurality of source lines. Because the drive unit is connected with the data line in the screen through the TFT switch, the HSD mode is used for arranging and designing the sub-pixels, and the number of the source lines is greatly reduced. Due to the fact that the number of the source lines is reduced, not only is the Y axis of the driving unit reduced, but also the manufacturing cost of the driving unit is saved, and components in the driving unit are reduced.

Referring to fig. 1, in the present application, a plurality of sub-pixels are sequentially arranged in an array in a manner of R (red), G (green), and B (blue). In some embodiments, the subpixel arrangement may be in other arrangements, such as R, B, G, R, B, G … arrangement, or may be similarly arranged with the addition of W (white).

Referring to fig. 1, in the present application, the gate lines are located at upper and lower sides of each row of sub-pixel pairs. Specifically, G1 and G2 are located at the upper and lower sides of the first row of sub-pixel pairs, G3 and G4 are located at the upper and lower sides of the second row of sub-pixel pairs, and G2n and G2n +1 are located at the upper and lower sides of the nth row of sub-pixel pairs.

Referring to fig. 1, in the first embodiment, the TFT switch of the first column sub-pixel pair (through D1) and the TFT switch of the fourth column sub-pixel pair (through D4) are respectively connected to the first source line; the TFT switch of the second column sub-pixel pair (through D2) and the TFT switch of the fifth column sub-pixel pair (through D5) are respectively connected with the second source line; the TFT switches in the third column subpixel pair (via D3) and the TFT switches in the sixth column subpixel pair (via D6) are connected to the third source line, respectively.

Specifically, S1 is connected through D1 in the display screen of Demux1, and R and G sub-pixels are connected to D1, and all the sub-pixels are on the left side of D1 (one data line is connected to each of two sub-pixels in one sub-pixel pair, but may be connected to each of two sub-pixels in two sub-pixel pairs); s1 is connected through D4 in the display screen of Demux2, and the D4 is connected with the R sub-pixel and the G sub-pixel, and the sub-pixels are both on the left side of D4, so that S1 only transmits the R/G sub-pixel data. S2 is connected through D2 in the display screen of the Demux1, and the sub-pixels B and R are connected to the D2 and are arranged on the left side of D2; s2 is connected through D5 in the display screen of Demux2, and the sub-pixels B and R are connected to D5, and the sub-pixels are on the left side of D5, so that S2 only transmits the data of the sub-pixels B/R. S3 is connected through D3 in a display screen of the Demux1, a G sub-pixel and a B sub-pixel are connected to the D3, and the sub-pixels are arranged on the left side of D3; s2 is connected through D6 in the display screen of Demux2, and the sub-pixels G and B are connected to D6, and the sub-pixels are on the left side of D6, so that S3 only transmits the data of the sub-pixels G/B. The pixel units are used as basic units, a plurality of pixel units can be arranged in order in the display screen surface of the framework, and the number of the pixel units can be selected according to the resolution ratios of different display screens.

Referring to fig. 1, in the first embodiment, taking Data transmission at S1 as an example: the Data transmission sequence is expressed by the third, the fourth, the seventh and the sixth; the first timing sequence is sequentially started according to G1 → G2 → G3 → G4. cndot. Gn, and can refer to the timing diagram of FIG. 2. For S1, when G1 is turned on and Demux1 is turned on, S1 transfers the sub-pixel R data to D1 through Demux1, as shown in FIG. 1, and when G1 remains on and Demux2 is turned on, S1 transfers the sub-pixel R data to D4 through Demux2, as shown in FIG. 1. When G2 is turned on and Demux1 is turned on, S1 transfers the sub-pixel G data to D1 through Demux1, shown as (c) in fig. 1, and when G2 is still turned on and Demux2 is turned on, S1 transfers the sub-pixel G data to D4 through Demux2, shown as (c) in fig. 1; for S1, the opening sequence of sub-pixels between G3 and G4 is one-to-one corresponding to the opening sequence of sub-pixels between G1 and G2, that is, after R +/R +/G-/G-is transmitted between G1 and G2, the sub-pixels between the next row of G3 and G4 repeat R +/R +/G-/G-data transmission, and the nth row also repeats R +/R +/G-/G-. For other Source lines, there are corresponding data transmission sequences, the data in S2 will be transmitted repeatedly with B +/B +/R-/R-as basic unit, and the data in S3 will be transmitted repeatedly with G +/G +/B-/B-/B-as basic unit.

As can be seen from the above, the data in S1 is repeatedly transmitted by using R +/R +/G-/G-as the basic unit, the data in S2 is repeatedly transmitted by using B +/B +/R-/R-as the basic unit, and the data in S3 is repeatedly transmitted by using G +/G +/B-/B-as the basic unit, so that the data transmission manner can reduce the frequency of positive and negative inversions of the Source voltage on the Source Line (Source Line). Taking S1 as an example, the voltage on the Source Line is inverted into two G sub-pixel voltages through two R sub-pixel voltages, if the voltages of the G sub-pixel and the B sub-pixel are both 0 in a pure color picture, and the R sub-pixel data is R + (assuming that the frame is positive at this time) in one frame, when the display screen displays the pure color red picture, the voltage on the Source Line does not need to be inverted from high → low → high → low, but is inverted from high → low, and the voltage inversion from high → low can reduce the high and low variation frequencies of the voltage on the Source Line, thereby reducing the power consumption of the pure color red picture. In other pure color frames, the voltage of the R sub-pixel is 0 in the green frame, and the G sub-pixel only needs to maintain positive polarity or negative polarity in one frame, and no high → low → high → low inversion is needed in one frame, so that power consumption can be saved.

Fig. 2 is a timing diagram of a first embodiment, which is a timing diagram of data transmission at S1 in fig. 1, and is explained in fig. 1, and is not repeated herein.

Referring to fig. 3 and 4, in the second embodiment, the connection manner of the pixels is the same as that of the first embodiment, the connection relationship between the Source Line and the Demux Line is the same as that of the first embodiment, and the second embodiment is characterized in that the timing of the GIP is changed to achieve the purpose of saving power consumption compared with the first embodiment. In conjunction with the timing diagram of fig. 4 of the second embodiment, in fig. 3 of the second embodiment, taking S1 as an example, the opening sequence of the GIP is G1 → G3 → G2 → G4 → G6 → G8 → G5 → G7 · · · · · · · · · · · · · · · Gn, wherein the opening sequence of G1 → G3 → G2 → G4 → G6 → G8 → G5 → G7 is taken as a group of pixel cells (Gn → Gn +2 → Gn +1 → Gn +3 → Gn +5 → Gn +7 → Gn +4 → Gn +6, N ═ 1,9,17,25 … N, N ═ N +8), and the transmission is performed according to such a rule that the next group of transmission sequence is G9 → G11G 3636 10 → G12 → G → 12 → G12 → so that the image transmission is repeated.

In FIG. 3, when G1 is turned on and Demux1 is turned on, S1 passes the sub-pixel R data to D1 via Demux1, as shown in (1) of FIG. 3; when Demux2 is turned on while G1 remains turned on, S1 passes subpixel R data to D4 via Demux2 as shown in (2) of fig. 3; when G3 is turned on and Demux1 is turned on, S1 passes the subpixel R data to D1 through Demux1 as shown in (3) of fig. 3; when Demux2 is turned on while G2 remains turned on, S1 passes subpixel R data to D4 via Demux2, as shown at (4) in fig. 3; the principle of G5/G7Data transmission is the same as that of G1/G3, and will not be described in detail. When G2 is turned on and Demux1 is turned on, S1 passes the sub-pixel G data to D1 via Demux1 as shown in (5) of fig. 3; when Demux2 is turned on while G2 remains turned on, S1 passes sub-pixel G data to D4 via Demux2 as shown at (6) in fig. 3; when G4 is turned on and Demux1 is turned on, S1 passes the sub-pixel G data to D1 via Demux1 as shown in (7) of fig. 3; when Demux2 is turned on while G2 remains turned on, S1 passes sub-pixel G data to D4 via Demux2 as shown at (8) in fig. 3; the transmission principle of G6/G8 is the same as that of G2/G4, and will not be described in detail.

In the second embodiment, for S1, the GIP is turned on according to the transmission sequence of G1 → G3 → G2 → G4 → G6 → G8 → G5 → G7, the data transmission in S1 is repeated in one frame with the basic unit of R +/G-/R +, when displaying a pure color picture such as red, the voltage on the Source Line transmits 8G sub-pixel data of 0V after transmitting 4R sub-pixel data (± 5V), so that the number of high and low voltage changes on the Source Line is smaller, i.e., the voltage change frequency on the Source Line is lower, and the power consumption is lower. If the image is a green image, the voltage on the Source Line is changed into 0V voltage after passing through the voltage data of 8G sub-pixels, so that the green image has less power consumption than the red image, and the power consumption of the blue image and the red image is basically consistent (caused by the relationship of pixel arrangement and GIP drive).

Referring to fig. 4, a timing diagram of a second embodiment of the present invention, Data transmission of the timing diagram is described in fig. 3, and will not be described in detail herein. Under the time sequence diagram, the power consumption of the pure color picture of the display screen is lower.

In some embodiments, one data line connects one sub-pixel of one sub-pixel pair and one sub-pixel of the other sub-pixel pair, respectively, so that more types of sub-pixels can be provided for the source line.

The embodiment provides a driving method of a power consumption-saving display screen structure, which applies the power consumption-saving display screen structure described in the embodiment, and includes the following steps: one gate line of a row of sub-pixels is turned on. During the period that one gate line is opened, two Demux lines are sequentially opened. During the period that one Demux line (Demux1) is turned on, the driving unit transmits signals to sub-pixels connected to data lines (D1, D3, D5) located at odd-numbered positions through the source line, and during the period that the other Demux line (Demux2) is turned on, the driving unit transmits signals to sub-pixels connected to data lines (D2, D4, D6) located at even-numbered positions through the source line. The other gate line of a row of subpixels is turned on. During the other gate line is turned on, the two Demux lines are turned on in sequence. During the opening period of one Demux line, the driving unit transmits signals to the sub-pixels connected to the data lines positioned at odd numbers through the source lines, and during the opening period of the other Demux line, the driving unit transmits signals to the sub-pixels connected to the data lines positioned at even numbers through the source lines. And driving the sub-pixels of each row by circulating the steps.

It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.

Claims

1. A power-saving display screen structure, comprising: the pixel structure comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, six data lines and three source lines;

2. The power-saving display screen structure of claim 1, wherein one data line connects two sub-pixels in one sub-pixel pair respectively.

3. The power-saving display panel structure of claim 1, wherein the input terminals of the TFT switches of the first column of sub-pixel pairs and the TFT switches of the fourth column of sub-pixel pairs are respectively connected to the first source line;

4. The power consumption-saving display screen structure according to claim 1, further comprising a driving unit connected to the plurality of source lines.

5. The power-saving display screen structure of claim 1, wherein the plurality of sub-pixels are arranged in an array R, G, B.