CN211980162U

CN211980162U - Comprehensive screen display structure

Info

Publication number: CN211980162U
Application number: CN202020500852.8U
Authority: CN
Inventors: 熊克; 谢建峰
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2020-04-08
Filing date: 2020-04-08
Publication date: 2020-11-20
Anticipated expiration: 2030-04-08

Abstract

The utility model discloses a comprehensive screen display shows structure, include: the display device comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, twelve data lines and seven source lines, and one side of the first pixel unit is provided with an initial data line; the initial data line is used for connecting one sub-pixel which is not connected by the data line in the first column of sub-pixel pairs; a data line is arranged between each column of sub-pixel pairs, each data line is connected with a TFT switch, and all the TFT switches are divided into two groups; the two Demux lines are respectively connected with the grid electrodes of one group of TFT switches of each pixel unit, the input ends of six TFT switches of each group are respectively connected with six source lines one by one, and the initial data line is independently connected with one source line; the technical scheme can reduce the number of source lines of the driving unit.

Description

Comprehensive screen display structure

Technical Field

The utility model relates to a display screen field especially relates to a comprehensive screen display shows structure.

Background

The design of narrow-frame and full-screen display screens has become mainstream, with the wide popularization of display screens, the ratio of the initial generation iPhone screen in 2007 is only about 50% from the aspect of screen ratio, and in the following years, the ratio of the mobile phone screen is continuously improved, but the improvement range is not large. In the existing display screen, the Y-axis length of a driving unit is an important factor influencing the overall screen or the narrow-frame screen. The existing display screen is that one Source Line (Source Line) of a driving unit (IC) corresponds to one Data Line (Data Line) in a plane, and one Data Line of the display screen controls one sub-pixel, so that the number of the Source lines is excessive, the Y axis of the driving unit cannot be reduced, the power consumption of the display screen is increased, and the manufacturing cost of the driving unit is increased.

SUMMERY OF THE UTILITY MODEL

Therefore, it is desirable to provide a full-screen display structure and a driving method thereof, which can greatly reduce the number of source lines and reduce the manufacturing cost of the driving unit.

To achieve the above object, the inventors provide a full-screen display structure including: the display device comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, twelve data lines and seven source lines, and one side of the first pixel unit is provided with an initial data line;

the pixel unit comprises a plurality of sub-pixels, the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels, the sub-pixels of each pixel unit are divided into twelve rows of sub-pixel pairs, and each row of sub-pixel pair comprises two rows of sub-pixels;

the starting data line is positioned on the left side of the pixel unit and is used for connecting one sub-pixel which is not connected by the data line in the first column of sub-pixel pairs of the first pixel unit;

a data line is arranged between each column of sub-pixel pairs, each data line is connected with a TFT switch, twelve TFT switches are used in total, the output ends of the TFT switches are connected with the data lines, all the TFT switches are divided into two groups, the TFT switches are positioned in the first column, the second column, the fifth column, the sixth column, the ninth column and the tenth column according to the column sequence and are divided into one group, and the TFT switches are positioned in the third column, the fourth column, the seventh column, the eighth column, the eleventh column and the twelfth column and are divided into another group;

the first Demux line is connected with the grid electrodes of one group of TFT switches of each pixel unit, the second Demux line is connected with the grid electrodes of the other group of TFT switches of each pixel unit, the input ends of the six TFT switches of each group are respectively connected with the six source lines one by one, and the initial data line is independently connected with one source line;

each row of sub-pixels comprises an upper gate line and a lower gate line, each data line is used for connecting the two sub-pixels in each row of pixels, and the two sub-pixels connected by each data line are respectively connected with the data line through one of the two gate lines in the row.

Further, one data line is respectively connected with two sub-pixels in two adjacent sub-pixel pairs in each row.

Furthermore, two adjacent sub-pixel pairs in the same row are provided, the left sub-pixel in one sub-pixel pair is connected with the right data line of the sub-pixel pair through the gate line on the upper side of the row, and the right sub-pixel is connected with the left data line of the sub-pixel pair through the gate line on the lower side of the row;

in another sub-pixel pair, the left sub-pixel is connected to the left data line of the sub-pixel pair through the gate line on the lower side of the row, and the right sub-pixel is connected to the right data line of the sub-pixel pair through the gate line on the lower side of the row.

Furthermore, the input terminals of the TFT switch of the first column sub-pixel pair and the TFT switch of the third column sub-pixel pair are respectively connected with a source line;

the input ends of the TFT switch of the second column of sub-pixel pairs and the TFT switch of the fourth column of sub-pixel pairs are respectively connected with a source line;

the input ends of the TFT switch of the sub-pixel pair in the fifth column and the TFT switch of the sub-pixel pair in the seventh column are respectively connected with a source line;

the input ends of the TFT switch of the sub-pixel pair in the sixth column and the TFT switch of the sub-pixel pair in the eighth column are respectively connected with one source line;

the input ends of the TFT switch of the sub-pixel pair in the ninth column and the TFT switch of the sub-pixel pair in the eleventh column are respectively connected with one source line;

the input terminals of the TFT switch of the sub-pixel pair in the tenth column and the TFT switch of the sub-pixel pair in the twelfth column are respectively connected with one source line.

Further, the display device further comprises a driving unit, wherein the driving unit is connected with the source lines.

Further, the plurality of sub-pixels are arranged in an array in sequence in the manner of R, G, B.

Different from the prior art, the technical scheme can reduce the number of source lines of the driving unit, so that the driving unit becomes narrower, and the lower boundary of the display screen is reduced. In addition, the pixel connection mode provided by the method is matched with a special time sequence, so that the purpose of saving the power consumption of the pure color picture of the display screen can be achieved.

Drawings

FIG. 1 is an internal structural view of a full-screen display structure according to an embodiment;

FIG. 2 is a timing diagram of the full-screen display structure according to the first embodiment;

FIG. 3 is an internal structural view of the left side of the full panel display structure according to the second embodiment;

FIG. 4 is an internal structural view of the middle portion of the full-screen display structure according to the second embodiment;

fig. 5 is an internal structure diagram of the right side of the full-screen display structure according to the second embodiment.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1 to 5, a full-screen display structure of the present embodiment includes: the pixel structure comprises a plurality of pixel units and two Demux lines (Demux1 and Demux2), wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines (G1, G2, G3 and G4 …), twelve data lines (D2, D3 and D4 … D13) and seven source lines (S1, S2 and S3 … S7), and a starting data line D1 is arranged on one side of a first pixel unit. The pixel unit comprises a plurality of sub-pixels, the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels, the sub-pixels of each pixel unit are divided into twelve rows of sub-pixel pairs, and each row of sub-pixel pairs comprises two rows of sub-pixels. The starting data line is positioned at the left side of the pixel unit, and the starting data line (the starting data line is a data line which can be separately connected with a source line without a Demux line) is used for connecting one sub-pixel which is not connected with the data line in the first column of sub-pixel pairs of the first pixel unit. A data line is arranged between each column of sub-pixel pairs, and each data line is connected with a Thin Film Transistor (TFT) switch, and twelve TFT switches in total. The output ends of the TFT switches are connected with the data lines, and all the TFT switches are divided into two groups. According to the column sequence, the positions of the first column, the second column, the fifth column, the sixth column, the ninth column and the tenth column are divided into one group, and the positions of the third column, the fourth column, the seventh column, the eighth column, the eleventh column and the twelfth column are divided into another group. The first Demux line is connected with the gates of the TFT switches of one group of each pixel unit, the second Demux line is connected with the gates of the TFT switches of the other group of each pixel unit, the input ends of the six TFT switches of each group are respectively connected with six source lines (S2-S7) one by one, and the initial data line is independently connected with one source line (S1). Each row of sub-pixels comprises an upper gate line and a lower gate line, each data line is used for connecting the two sub-pixels in each row of pixels, and the two sub-pixels connected by each data line are respectively connected with the data line through one of the two gate lines in the row.

The technical scheme saves the power consumption of the display screen, the display screen only needs 1/4 Source lines because of adopting a Demux 1:2+ HSD structure, so that a driving unit (IC) does not need more devices, the cost is saved, and meanwhile, the Y axis of the IC is narrower, so that the display screen can be applied to the design of the display screen close to a full-face screen.

In this application (first and second embodiments), the display panel structure further includes a driving unit connected to the plurality of source lines. Due to the fact that the Demux design mode is adopted after the source line is led out of the driving unit, the number of the source lines is reduced, when the source lines are connected with the initial data lines in the plane through the TFT switch, the HSD mode is used for arranging and designing the sub-pixels, and the number of the source lines is greatly reduced.

In the present application, a plurality of sub-pixels are sequentially arranged in an array in the form of R (red), G (green), and B (blue). In some embodiments, the subpixel arrangement may be in other arrangements, such as R, B, G, R, B, G … arrangement, or may be similarly arranged with the addition of W (white).

In the present application, the gate lines are located at upper and lower sides of each row of sub-pixel pairs. Specifically, G1 and G2 are located at the upper and lower sides of the first row of sub-pixel pairs, G3 and G4 are located at the upper and lower sides of the second row of sub-pixel pairs, and G2n and G2n +1 are located at the upper and lower sides of the nth row of sub-pixel pairs.

In the present application, a plurality of such pixel units repeatedly appear in the display screen, for example, between G3 and G4, and the pixel units appear in the display screens with different resolutions in different times.

Referring to fig. 1, in the first embodiment, two adjacent sub-pixel pairs in the same row are connected, a left sub-pixel in one sub-pixel pair is connected to a right data line of the sub-pixel pair through a gate line on the upper side of the row, and a right sub-pixel is connected to the left data line of the sub-pixel pair through a gate line on the lower side of the row; in another sub-pixel pair, the left sub-pixel is connected to the left data line of the sub-pixel pair through the gate line on the lower side of the row, and the right sub-pixel is connected to the right data line of the sub-pixel pair through the gate line on the lower side of the row.

Specifically, D1 to D13 are in-plane Data lines (Data lines), and S1 to S7 are Source lines (Source lines) from the driver unit (IC). The leftmost start data line D1 (the start data line is a data line not connected to the source line by a Demux line) of the display panel connects the R sub-pixel and the G sub-pixel, and D1 does not connect the Demux switch. Fig. 1 shows a pixel unit, and a plurality of pixel units can be arranged in order in the display screen of the structure, and the number of the pixel units can be selected according to the resolution of different display screens. When the pixel units are arranged in a plurality of arrays, the rightmost side (D13) of fig. 1 is connected to the leftmost side of fig. 2, i.e. the Data lines are actually the same root. The left side of the first pixel unit is provided with a start data line D1 (only one single start data line), the start data line D1 is arranged in a non-array mode, and the data lines (D2, D3 and D4 … Dm) are arranged in an array mode. It should be further noted that the first data line of the pixel unit located in the middle of the display area and the last data line of the previous pixel unit are the same data line. The connection mode of the first data line in the middle pixel unit and the sub-pixel in the pixel unit is the same as the connection mode of the initial data line and the sub-pixel.

S2 would pass Demux1 and Demux2 before connecting to in-plane D2 and D4, S3 would pass Demux1 and Demux2 before connecting to in-plane D3 and D5, S4 would pass Demux1 and Demux2 before connecting to in-plane D6 and D8, S5 would pass Demux1 and Demux2 before connecting to in-plane D7 and D9, S6 would pass Demux1 and Demux2 before connecting to in-plane D10 and D12, S7 would pass Demux1 and Demux2 before connecting to in-plane D11 and D13, respectively.

That is, the TFT switch of the first column sub-pixel pair (through D2) and the TFT switch of the third column sub-pixel pair (through D4) are respectively connected to the second source line (S2); the TFT switches in the second column of sub-pixel pairs (via D3) and the TFT switches in the fourth column of sub-pixel pairs (via D5) are connected to a third source line (S3), respectively; the TFT switch of the sub-pixel pair in the fifth column (through D6) and the TFT switch of the sub-pixel pair in the seventh column (through D8) are respectively connected with the fourth source line (S1); the TFT switch of the sub-pixel pair in the sixth column (through D7) and the TFT switch of the sub-pixel pair in the eighth column (through D9) are respectively connected with the fifth source line; the TFT switch of the sub-pixel pair in the ninth column (through D10) and the TFT switch of the sub-pixel pair in the eleventh column (through D12) are respectively connected with the sixth source line; the TFT switch of the sub-pixel pair in the tenth column (through D11) and the TFT switch of the sub-pixel pair in the twelfth column (through D13) are respectively connected to the seventh source line (S7).

Referring to fig. 1 and fig. 2, in the first embodiment, Data transmission of S2 is taken as an example: when G1 is turned on and Demux1 is turned on, S2 is connected to D2 in the plane through Demux1, and the sub-pixel connected to both D2 and G1 is R sub-pixel (R), so that S2 first transmits R sub-pixel (R) data; when G1 is still opened and Demux2 is opened, S2 is connected with D4 in the plane through Demux2, and the sub-pixel connected with G1 and D4 is G sub-pixel (II), and at the moment, S2 transmits G sub-pixel (II) data; when G2 is turned on and Demux1 is turned on, S2 is connected with D2 in the plane through Demux1, and the sub-pixel connected with both D2 and G2 is B sub-pixel (c), so that S2 transmits B sub-pixel (c) data; when G2 remains open and Demux2 is open, S2 is connected to D4 in-plane through Demux2, and the sub-pixel connected to both G2 and D4 is the R sub-pixel (R), at which time S2 transfers the R sub-pixel (R) data.

Referring to fig. 2, in the first embodiment, Data transmission of other Source lines in fig. 2 is similar to S2, except that the Data transmission sequence is different (i.e. the connection sequence of the sub-pixels is different), but the transmission waveforms of the Gate lines (Gate lines) and Demux are the same, and the transmission principle is the same as S2, which is not described herein in detail.

Referring to fig. 2, in the first embodiment, due to the particularity of S1, the Data transmission timing of S1 is particularly shown, when G1 is turned on and Demux1 is turned on, there is no sub-pixel connection on S1 (i.e., D1), and Data is not transmitted, i.e., Data is empty; when G1 is still open and Demux2 is open, there is no sub-pixel connection on S1(D1), and Data is not transmitted, i.e., Data is empty; when G2 is turned on and Demux1 is turned on, the sub-pixel connected to both S1(D1) and G1 is the G sub-pixel, and the G sub-pixel data is transmitted; g2 is still kept open, and when Demux2 is open, only one sub-pixel is connected because S1 does not pass through the TFT switch of Demux, and G sub-pixel data is still transmitted.

Referring to fig. 2, (1) the Data is used to wrap the falling edge time of the Gate, which is necessary to prevent the Data of the next row from being erroneously filled when the Gate is trailing, and (2) the Data is used to wrap the falling edge time of Demux, which is necessary to prevent the Data transmitted when Demux2 is turned on from affecting the turn-on of Demux 1. For example, S2 transmits G sub-pixel Data when G1 is turned on and Demux2 is turned on, and if Demux1 is trailing, that is, Demux1 is not yet completely turned off, but R sub-pixel (R) is not transmitting (i.e., the trailing of Demux1 is not covered), G sub-pixel Data is also transmitted to Data Line controlled by Demux1, i.e., color mixing occurs.

Referring to fig. 3, in the second embodiment, when the sub-pixels in the same row are sequentially driven by the gate lines, the sub-pixels in different colors are on the same source. Therefore, the same data line is connected with the sub-pixels in different columns in the sub-pixel pairs of two adjacent rows and the same column. For example, D4 is connected to the sub-pixel (2) in the first row, D4 is connected to the sub-pixel (8) in the second row directly below the sub-pixel (2) in the first row, and D4 is connected to the source line to transmit more types of sub-pixels. Other data lines may also be varied similarly to this.

Specifically, D1 to D13 are also in-plane Data lines (Data lines), and S1 to S7 are Source lines (Source lines) from the driver unit (IC). The leftmost start data line D1 (source line S1) of the display screen is connected with the R sub-pixel and the G sub-pixel, and D1 is not connected with the Demux switch; s2 is connected to in-plane D2 through the TFT switch of Demux1, S2 is connected to in-plane D4 through the TFT switch of Demux 2; s3 is connected to in-plane D3 through the TFT switch of Demux1, S3 is connected to in-plane D5 through the TFT switch of Demux 2; s4 is connected to in-plane D6 through the TFT switch of Demux1, S2 is connected to in-plane D8 through the TFT switch of Demux 2; s5 is connected to in-plane D7 through the TFT switch of Demux1, S5 is connected to in-plane D9 through the TFT switch of Demux 2; s6 is connected to in-plane D10 through the TFT switch of Demux1, S2 is connected to in-plane D12 through the TFT switch of Demux 2; s7 is connected to in-plane D11 through the TFT switch of Demux1, and S7 is connected to in-plane D13 through the TFT switch of Demux 2.

Referring to fig. 3 and 4, in a second embodiment, fig. 3 shows a pixel unit, a plurality of pixel units can be arranged in order in the display screen of the structure, and the number of the pixel units can be selected according to the resolutions of different display screens. When the pixel units are arranged in a plurality of arrays, the rightmost side of fig. 3 is connected with the leftmost side of fig. 4, i.e. the Data lines are actually the same root. The left side of the first pixel unit is provided with a start data line D1, the start data line D1 is not arranged in an array (a single line), and the data lines (D2, D3, D4 … Dm) are arranged in an array.

Referring to fig. 3, in the second embodiment, the polarities of the adjacent pixels are opposite, that is, the display effect is a Dot display effect, and the Dot display effect can optimize the visual effect of the display screen. In the display screen, the display effect of Dot is realized by adopting a Column Inversion driving mode, and the power consumption of the display screen is saved. And because of adopting the Demux 1:2+ HSD structure, the display screen only needs 1/4 Source lines, thus the IC does not need more devices, the cost is saved, and the Y axis of the IC is narrower.

Referring to FIG. 3, in the second embodiment, for S1, when G1 is turned on, since the sub-pixel of S1 is not connected to G1 and Demux1/Demux2 is turned on, S1 does not transmit the sub-pixel data, i.e. is empty; when G2 is turned on and Demux1 is turned on, G sub-pixel data (i) is transmitted in S1, and G sub-pixel data (i) is still transmitted in S1 when Demux2 is turned on; when G3 is opened and Demux1 is opened, R sub-pixel data is transmitted on S1, and when Demux2 is opened, R sub-pixel data is transmitted on S1; when G4 is turned on, Demux1/Demux2 turn on because the sub-pixel on S1 is not connected to G4, and S1 does not transmit the sub-pixel data. The Data at S1 will repeatedly transmit Data on the display screen in the manner described above.

Referring to fig. 3, in the second embodiment, the Data transmission of S2 is used to describe the process of Data transmission of Demux + HSD, and the Data transmission of other Source lines (except for the Source Line at the far left and right sides of the display screen) is similar to S2: when G1 is on and Demux1 is on, S2 transfers R sub-pixel data (1) to D2 in-plane, Demux1 is off, Demux2 is on, S2 transfers G sub-pixel data (2) to D4 in-plane; when G2 is on and Demux1 is on, S2 transfers B sub-pixel data (3) to D2 in-plane, Demux1 is off, Demux2 is on, S2 transfers R sub-pixel data (4) to D4 in-plane; when G3 is on and Demux1 is on, S2 transfers R sub-pixel data (5) to D2 in-plane, Demux1 is off, Demux2 is on, S2 transfers G sub-pixel data (6) to D4 in-plane; when G4 is on and Demux1 is on, S2 transfers G sub-pixel data (7) to D2 in-plane, Demux1 is off, and Demux2 is on, S2 transfers B sub-pixel data (8) to D4 in-plane. By analogy, the Data transmission process of S3-S7 is similar to S2, except that the Data is transmitted in different order.

Referring to FIG. 4, in a second embodiment, a right side Dm-12 of FIG. 4 is connected to a left side of FIG. 5. in FIG. 4, only the repeating sequence of FIG. 3 is shown, and a plurality of pixel units of FIG. 3 appear in a display panel. Fig. 5 is also a repeating sequence of fig. 3, and the pixel connections of fig. 5 are the same as those of fig. 3.

The embodiment provides a driving method of a full-screen display structure, which applies the full-screen display structure described in the embodiment, and includes the following steps: one gate line of a row of sub-pixels is turned on. During the period that one gate line is opened, the driving unit transmits signals to the sub-pixels connected with the initial data line through the source line, and sequentially opens the two Demux lines. During the opening period of the Demux line of the first row, the driving unit transmits signals to the sub-pixels connected to the data lines at the positions of the first column, the second column, the fifth column, the sixth column, the ninth column and the tenth column through the source lines, and during the opening period of the Demux line of the second row, the driving unit transmits signals to the sub-pixels connected to the data lines at the positions of the third column, the fourth column, the seventh column, the eighth column, the eleventh column and the twelfth column through the source lines. The other gate line of a row of subpixels is turned on. During the other gate line is turned on, the two Demux lines are turned on in sequence. During the opening period of the Demux line of the first row, the driving unit transmits signals to the sub-pixels connected to the data lines at the positions of the first column, the second column, the fifth column, the sixth column, the ninth column and the tenth column through the source lines, and during the opening period of the Demux line of the second row, the driving unit transmits signals to the sub-pixels connected to the data lines at the positions of the third column, the fourth column, the seventh column, the eighth column, the eleventh column and the twelfth column through the source lines. And driving the sub-pixels of each row by circulating the steps.

It should be noted that the start data line is connected to only one gate line in a row of sub-pixels and controls one sub-pixel of the first sub-pixel pair of the first pixel unit of the plurality of pixel units. When the turned-on gate line is connected to the start data line, the driving unit transmits a signal to the sub-pixel connected to the start data line through the source line S1 and also transmits a signal to the sub-pixel connected to the data line through the source lines (S2 to S7); when the opened gate line is not connected with the initial data line, the driving unit does not transmit signals to the sub-pixel connected with the initial data line through the source line, and directly drives the sub-pixel corresponding to the data line.

It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.

Claims

1. A full-screen display structure, comprising: the display device comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, twelve data lines and seven source lines, and one side of the first pixel unit is provided with an initial data line;

2. A full screen display structure according to claim 1, wherein a data line connects two sub-pixels in two adjacent sub-pixel pairs in each row respectively.

3. A full-screen display structure according to claim 1 or 2, wherein two adjacent sub-pixel pairs in the same row are arranged, the left sub-pixel in a sub-pixel pair is connected to the right data line of the sub-pixel pair through the gate line on the upper side of the row, and the right sub-pixel is connected to the left data line of the sub-pixel pair through the gate line on the lower side of the row;

4. A full screen display structure according to claim 1, wherein the input terminals of the TFT switches of the first column of sub-pixel pairs and the TFT switches of the third column of sub-pixel pairs are respectively connected to a source line;

5. A full screen display structure according to claim 1, further comprising a driving unit, wherein said driving unit is connected to a plurality of said source lines.

6. A full screen display structure according to claim 1, wherein the plurality of sub-pixels are arranged in an array R, G, B.