CN110333632B

CN110333632B - Array substrate, display panel and display device

Info

Publication number: CN110333632B
Application number: CN201910580865.2A
Authority: CN
Inventors: 傅炯樑; 金慧俊; 秦丹丹; 夏志强; 简守甫; 钟本顺; 秦锋
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2019-06-29
Filing date: 2019-06-29
Publication date: 2022-04-12
Anticipated expiration: 2039-06-29
Also published as: CN110333632A

Abstract

The invention discloses an array substrate, a display panel and a display device. In the array substrate, each row of sub-pixels is electrically connected with three scanning lines, the scanning lines are intersected with a plurality of data lines, one column of sub-pixels is electrically connected with one data line, and for one row of sub-pixels, any two sub-pixels with the same light-emitting color and the same signal polarity in the same frame of picture form a sub-pixel group; for a sub-pixel group, two sub-pixels are electrically connected to different scanning lines adjacent to the sub-pixels from the same side, and two data lines electrically connected with the two sub-pixels in the same sub-pixel group are electrically connected to the same data port. The technical scheme provided by the embodiment of the invention reduces the power consumption of the display panel when the display panel displays the pure-color picture and improves the display effect of the display panel.

Description

Array substrate, display panel and display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

The dual gate pixel structure has the advantages of low production cost and low power consumption, is widely applied to various display devices, and is popular with users.

In the prior art, in an array substrate having a column-inversion pixel structure, a plurality of sub-pixels are arranged in a matrix, the light emitting colors of the sub-pixels in the same column are the same, the light emitting colors of the sub-pixels in adjacent columns are different, and each data line is electrically connected with two columns of sub-pixels arranged adjacently. When the display panel displays a pure color picture, the data signals input on the data lines need to be continuously changed within the display time of the same frame picture, so as to achieve the purpose of controlling the sub-pixels with the same luminous color as the color to be displayed to normally display and the sub-pixels with the different luminous color from the color to be displayed to not emit light. In the above-mentioned image display process, the data signal inversion frequency of the data line is very high, which results in high power consumption when the display panel displays a pure color image. In addition, in order to ensure normal display of the sub-pixels, the sub-pixels in the same row, which have the same light emission color and different signal polarities in a frame of picture, are respectively and electrically connected with different adjacent scanning lines, so that when a process error exists in the preparation process of the array substrate, the variation trend and the variation quantity of the coupling capacitance between the pixel electrode in each sub-pixel and the scanning line electrically connected with the sub-pixel are different, and further, the luminance of each sub-pixel is greatly influenced by the coupling capacitance, so that the display effect of the display panel is poor.

Disclosure of Invention

The invention provides an array substrate, a display panel and a display device, which are used for reducing the power consumption of the display panel when the display panel displays a pure-color picture and improving the display effect of the display panel.

In a first aspect, an embodiment of the present invention provides an array substrate, including: the plurality of sub-pixels are arranged in a matrix, the light-emitting colors of two adjacent sub-pixels in the same row of sub-pixels are different, the light-emitting colors of the sub-pixels in the same row are the same, the signal polarities of the sub-pixels in the same row are the same, and the signal polarities of the sub-pixels in two adjacent rows are different in the same frame picture;

the sub-pixels in each row are electrically connected with the three scanning lines;

a plurality of data lines intersecting the plurality of scan lines, the plurality of data lines extending in a column direction of the matrix; one column of the sub-pixels is electrically connected with one data line;

for a row of sub-pixels, any two sub-pixels with the same light-emitting color and the same signal polarity in the same frame picture form a sub-pixel group; for a sub-pixel group, two sub-pixels are electrically connected to different adjacent scanning lines from the same side, and two data lines electrically connected with the two sub-pixels in the same sub-pixel group are electrically connected to the same data port.

In a second aspect, an embodiment of the present invention further provides a display panel, where the display panel includes the array substrate according to the first aspect.

In a third aspect, an embodiment of the present invention further provides a display device, where the display device includes the display panel described in the second aspect.

In the array substrate provided by the embodiment of the invention, a plurality of sub-pixels are arranged in a matrix, the adjacent two sub-pixels in the same row of sub-pixels have different light emitting colors, the light emitting colors of the sub-pixels in the same column are the same, the signal polarities of the sub-pixels in the same column are the same in the same frame, the signal polarities of the sub-pixels in two adjacent columns are different, each row of sub-pixels is electrically connected with three scanning lines, the scanning lines are intersected with the data lines, the data lines extend along the column direction of the matrix, one column of sub-pixels is electrically connected with one data line, for one row of sub-pixels, any two sub-pixels which have the same light emitting color and have the same signal polarity in the same frame form a sub-pixel group, for one sub-pixel group, two sub-pixels are electrically connected to the adjacent different scanning lines from the same side, and two data lines which are electrically connected with the two sub-pixels in the same sub-pixel group are electrically connected with the same data port, in addition, each sub-pixel is electrically connected with the scanning lines on the same side, process errors occur in the process of preparing the array substrate, when the position of the pixel electrode moves, the relative displacement between the pixel electrode and the corresponding scanning line in all the sub-pixels is the same, the difference generated by the coupling influence of the pixel electrode and the corresponding scanning line on the brightness of each sub-pixel is the same, the influence of the coupling on the display effect of the display panel is reduced, and the display effect of the display panel is favorably improved.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;

FIG. 9 is a schematic sectional view along the broken line LM in FIG. 8;

fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description will be given to specific embodiments, structures, features and effects of an array substrate, a display panel and a display device according to the present invention with reference to the accompanying drawings and preferred embodiments.

An embodiment of the present invention provides an array substrate, including: the plurality of sub-pixels are arranged in a matrix, the light-emitting colors of two adjacent sub-pixels in the same row of sub-pixels are different, the light-emitting colors of the sub-pixels in the same row are the same, the signal polarities of the sub-pixels in the same row are the same, and the signal polarities of the sub-pixels in two adjacent rows are different in the same frame picture;

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other embodiments that depart from the specific details disclosed herein, and it will be recognized by those skilled in the art that the present invention may be practiced without these specific details.

Next, the present invention is described in detail with reference to the schematic drawings, and in the detailed description of the embodiments of the present invention, the schematic drawings showing the structure of the device are not partially enlarged in general scale for convenience of description, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and height should be included in the actual fabrication.

Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. It should be noted that, in fig. 1, the color is indicated by filled shading, the light emitting colors of the sub-pixels 110 filled with different shading are different, and "+" or "-" is used to indicate the signal polarities of the sub-pixels 110 in the same frame, the signal polarity of the sub-pixel 110 indicated with "+" in the frame is positive, and the signal polarity of the sub-pixel 110 indicated with "-" in the frame is negative. As shown in fig. 1, the array substrate includes a plurality of sub-pixels 110, a plurality of scan lines 120, and a plurality of data lines 130. The sub-pixels 110 are arranged in a matrix, the light emitting colors of two adjacent sub-pixels 110 in the same row of sub-pixels 110 are different, the light emitting colors of the sub-pixels 110 in the same column are the same, and in the same frame, the signal polarities of the sub-pixels 110 in the same column are the same, and the signal polarities of the sub-pixels 110 in two adjacent columns are different. The sub-pixels 110 in each sub-pixel row are electrically connected by three scan lines 120, the scan lines 120 intersect with data lines 130, the data lines 130 extend in the column direction Y of the matrix, and a column of the sub-pixels 110 is electrically connected to one data line 130. For a row of sub-pixels, any two sub-pixels 110 with the same light-emitting color and the same signal polarity in the same frame form a sub-pixel group 400, for a sub-pixel group 400, two of the sub-pixels 110 are electrically connected to different scan lines 120 adjacent thereto from the same side, and two data lines 130 electrically connected to two sub-pixels 110 in the same sub-pixel group 400 are electrically connected to the same data port 140.

It should be noted that fig. 1 only illustrates the sub-pixel 110 including three sub-pixels 110 with different colors, but is not limited thereto, and in other embodiments of the embodiment of the present invention, the types of the light emitting colors of the sub-pixels 110 may also be two or more, and the embodiment of the present invention is not limited thereto. It should be noted that, since the light emitting colors of the adjacent sub-pixels 110 in the same row are different, the light emitting colors of the sub-pixels 110 are not only one. In addition, according to the principle of image display, the signal polarities of the same sub-pixel 110 in the adjacent frames are opposite, for example, the sub-pixel 110 with the signal polarity of positive polarity in the first frame is the sub-pixel 110 with the signal polarity of negative polarity in the second frame, and fig. 1 shows the setting of the polarity of each sub-pixel 110 in the same frame.

It should be further noted that each sub-pixel 110 is electrically connected to one scan line 120, and in the same sub-pixel row, the first part of sub-pixels 110 is electrically connected to one scan line 120, the second part of sub-pixels 110 is electrically connected to another scan line 120, and the third part of sub-pixels 110 is electrically connected to the third scan line 120, in the embodiment of the present invention, specific positional relationship between the three scan lines 120 electrically connected to each row of sub-pixels 110 and the row of sub-pixels 110 is not limited, and the number of sub-pixel rows corresponding to each scan line 120 is not limited, for example, all sub-pixels 110 electrically connected to each scan line 120 are located in the same row, or all sub-pixels 110 electrically connected to some scan lines 120 are distributed in two adjacent sub-pixel rows, as shown in fig. 1.

It should be noted that the data lines 130 electrically connected to the two sub-pixels 110 in any sub-pixel group 400 are respectively a first data line and a second data line, which are electrically connected to the first data line and the second data line, and any two sub-pixels 110 in the same row form a sub-pixel group 400. It is understood that any sub-pixel row includes a plurality of sub-pixels 110 with the same light-emitting color and the same signal polarity in the same frame, and the embodiment of the present invention does not specifically limit the positional relationship between two sub-pixels 110 forming the sub-pixel group 400, for example, in the plurality of sub-pixels 110 with the same light-emitting color in the same row and the same signal polarity in the same frame, two adjacent sub-pixels 110 form one sub-pixel group 400, or two sub-pixels 110 disposed at an interval of at least one sub-pixel 110 form one sub-pixel group 400.

In addition, the essential meaning of "two of the sub-pixels 110 are electrically connected to different adjacent scan lines 120 from the same side" is: it is noted that the two sub-pixels 110 forming a sub-pixel group 400 are a first sub-pixel and a second sub-pixel, the first sub-pixel is electrically connected to a first scan line, the second sub-pixel is electrically connected to a second scan line, the first scan line and the second scan line are both located on the same side of the sub-pixel row where the sub-pixel group 400 is located, and no other scan line 120 is disposed between the first sub-pixel and the first scan line, and no other scan line 120 is disposed between the second sub-pixel and the second scan line, i.e. here, "adjacent" means that no other scan line 120 is disposed between the two, and based on the structural features of the sub-pixels 110, other structures than the scan lines 120, such as thin film transistors, may be disposed between the sub-pixels 110 and the corresponding scan lines 120.

In order to implement the above connection manner, in the embodiment of the present invention, the related scan lines 120 are processed in a winding manner as shown in fig. 1, such an arrangement can meet the above connection requirement, and at the same time, the intersection between different scan lines 120 is avoided, and it is ensured that each scan line 120 can be arranged on the same layer, so that the thickness increase of the array substrate is avoided, which is beneficial to thinning the display panel. It can be understood that, in the embodiment of the present invention, the specific winding manner of each scan line 120 is not limited, and the operator can perform reasonable setting according to actual needs as long as each sub-pixel 110 can normally display.

In the array substrate provided by the embodiment of the invention, the plurality of sub-pixels 110 are arranged in a matrix, the adjacent two sub-pixels 110 in the same row of sub-pixels 110 have different light emitting colors, the light emitting colors of the sub-pixels 110 in the same column are the same, the signal polarities of the sub-pixels 110 in the same column are different in the same frame, the sub-pixels 110 in the two adjacent columns are electrically connected with each sub-pixel 110 in each sub-pixel row through three scanning lines 120, the plurality of scanning lines 120 are intersected with the plurality of data lines 130, the plurality of data lines 130 extend along the column direction Y of the matrix, one column of sub-pixels 110 is electrically connected with one data line 130, for one row of sub-pixels, any two sub-pixels 110 having the same light emitting color and the same signal polarity in the same frame form a sub-pixel group 400, for one sub-pixel group 400, two sub-pixels 110 on the same side are electrically connected to the different scanning lines 120 adjacent to the same side, in addition, when the position of the pixel electrode moves, the relative displacement between the pixel electrode in all the sub-pixels 110 and the corresponding scanning line 120 is the same, so that the brightness of each sub-pixel 110 is the same due to the coupling influence of the pixel electrode and the corresponding scanning line 120, the influence of the coupling on the display effect of the display panel is reduced, and the display effect of the display panel is improved.

With continued reference to fig. 1, the data lines 130 electrically connected to the sub-pixel columns are located on the same side of the sub-pixel columns along the row direction X of the matrix. Specifically, in the structure shown in fig. 1, each column of sub-pixels 110 is electrically connected to the data line 130 on the left side thereof.

It should be noted that the sub-pixel 110 includes a pixel electrode, and after the data line 130 is inputted with a signal, the coupling between the pixel electrode in the sub-pixel 110 and the corresponding data line 130 may affect the brightness of the sub-pixel 110. The arrangement mode that each row of sub-pixels 110 are electrically connected with the data lines 130 positioned on the same side of the sub-pixels 110 can cause process errors in the process of preparing the array substrate, and when the positions of the pixel electrodes move, the relative displacement between the pixel electrodes in all the sub-pixels 110 and the corresponding data lines 130 is the same, so that the difference generated by the coupling influence of the pixel electrodes and the corresponding data lines 130 on the brightness of each sub-pixel 110 is the same, and the influence of the coupling on the display effect of the display panel is reduced.

Alternatively, referring to fig. 1, for a row of sub-pixels 110, every two adjacent sub-pixels 110 with the same light-emitting color and the same polarity in the same frame form a sub-pixel group 400.

It should be noted that the two data lines 130 electrically connected to the two sub-pixels 110 in the sub-pixel group 400 are electrically connected through a connection line, the arrangement can enable the connection lines corresponding to the plurality of sub-pixel groups 400 formed by the plurality of sub-pixels 110 having the same emission color and the same emission color in the same frame to be non-overlapped in the extending direction of the data lines 130, the connection lines can be sequentially arranged on the same straight line along the row direction X of the sub-pixel matrix, only the connection lines corresponding to the sub-pixel groups 400 having different emission colors and/or different signal polarities in the same frame can be overlapped in the column direction Y of the sub-pixel matrix, so that the number of the overlapped connection lines is small, the length of the non-display area of the array substrate occupied by the connection lines in the column direction Y of the sub-pixel matrix is reduced, and the narrow frame of the display panel is facilitated.

With continued reference to fig. 1, in a sub-pixel row, the sub-pixels 110 of three different colors form a pixel unit 300, and each sub-pixel 110 in the same pixel unit 300 is electrically connected to the same scan line 120.

It should be noted that, the sub-pixels 110 in the same pixel unit 300 are continuously arranged in the extending direction of the sub-pixel row (the row direction X of the sub-pixel matrix), and the way of electrically connecting each sub-pixel 110 in the same pixel unit 300 with the same scanning line 120 can enable the same scanning line 120 to continuously extend the length of at least one pixel unit 300 in the row direction X of the sub-pixel matrix without winding, the number of winding times of the same scanning line 120 is small, which is beneficial to the reduction of the length of the scanning line 120, and the phenomenon that the signal attenuation is obvious due to the overlarge length of the scanning line 120 is avoided.

When the pixel unit 300 includes an odd number of sub-pixels 110, for example, as shown in fig. 1 and 2, the pixel unit 300 includes a red sub-pixel 111, a green sub-pixel 112, and a blue sub-pixel 113, and each adjacent four pixel units 300 in one sub-pixel row form one pixel unit group 200. The pixel unit group 200 includes a first sub-unit 210 and a second sub-unit 220, the first sub-unit 210 includes two adjacent pixel units 300, the second sub-unit 220 includes two adjacent pixel units 300, each sub-pixel 110 in the same first sub-unit 210 is electrically connected to the same scan line 120, each sub-pixel 110 in the same second sub-unit 220 is electrically connected to the same scan line 120, wherein the first sub-unit 210 and the second sub-unit 220 are respectively electrically connected to any two scan lines 120 of the three scan lines 120 correspondingly connected to the sub-pixel row.

Since red, green, and blue are three primary colors of light, and red, green, and blue with different intensities can be mixed to obtain light of various colors, the arrangement of the pixel unit 300 including the red sub-pixel 111, the green sub-pixel 112, and the blue sub-pixel 113 can make the display panel display various colors, thereby enriching the display colors of the display device. It is understood that, in other embodiments of this embodiment, the number and color of the sub-pixels included in the pixel unit 300 may be other situations, and this embodiment is not limited in this respect.

It should be noted that, each sub-pixel 110 in the first sub-unit 210 belongs to a different sub-pixel group 400, and is electrically connected to a different data line 130 respectively to receive different data signals, so that the same scan line 120 can be electrically connected without the problem of being incapable of being controlled independently, and similarly, each sub-pixel 110 in the second sub-unit 220 belongs to a different sub-pixel group 400, and is electrically connected to a different data line 130 respectively to receive different data signals, so that the same scan line 120 can be electrically connected without the problem of being incapable of being controlled independently. In addition, each sub-pixel 110 in the second sub-unit 220 and one sub-pixel group 400 in the first sub-unit 210 form a sub-pixel group 400, so each sub-pixel 110 in the first sub-unit 210 and each sub-pixel 110 in the second sub-unit 220 need to be electrically connected to different scan lines 120, so as to ensure that each sub-pixel 110 can be controlled independently to realize normal display. In addition, as long as the first sub-unit 210 and the second sub-unit 220 are ensured to be electrically connected to different scan lines 120, no particular limitation is required, so that the sub-pixel 110 in the first sub-unit 210 can be electrically connected to any one of the three scan lines 120 corresponding to the sub-pixel row where the sub-pixel is located, and the sub-pixel 110 in the second sub-unit 220 can be electrically connected to any one of the remaining two scan lines 120.

In addition, the specific arrangement manner of each scan line 120 is not specifically limited in the embodiment of the present invention, for example, as shown in fig. 1, one scan line 120 shared by an adjacent sub-pixel row exists in three scan lines 120 correspondingly connected to a sub-pixel row, and all sub-pixels electrically connected to the one scan line 120 are distributed in the adjacent two sub-pixel rows. Further, according to different arrangement sequences of the scan lines 120, the specific method for realizing the adjacency of each sub-pixel 110 in the first sub-unit 210 and the second sub-unit 220 and the corresponding scan line 120 by a winding manner includes a plurality of methods, as long as it is ensured that the three scan lines 120 are electrically connected with each sub-pixel 110 in one sub-pixel row, and the first sub-unit 210 and the second sub-unit 220 in the same pixel unit group 200 are electrically connected with different scan lines 120.

For example, fig. 1 provides a specific winding manner of the scan lines 120, and it is noted that the input end of each scan line 120 is located at the left side of the scan line, and the output end of each scan line 120 is located at the right side of the scan line. As shown in fig. 1, in the column direction Y of the sub-pixel matrix, the input end of one scan line 120 is disposed at the upper side of the sub-pixel row, and the input ends of the other two scan lines 120 are sequentially arranged at the lower side of the sub-pixel 110 row, among the three scan lines 120 corresponding to each sub-pixel row. Specifically, the three scan lines 120 are periodically wound, and fig. 1 only illustrates a structure of one period. Continuing to refer to fig. 1, every two pixel unit groups 200 that are continuously arranged correspond to a winding cycle, and the scan line 120 with the input end arranged on the upper side of the sub-pixel row is taken as the scan line a, the scan line 120 with the input end arranged on the lower side of the sub-pixel row and arranged adjacent to the sub-pixel row is taken as the scan line B, and the remaining scan line 120 is taken as the scan line C, in the same winding cycle, the scan line a is wound from the upper side of the sub-pixel row to the lower side thereof with the input end thereof as the starting point, and after the length of the first sub-unit 210, is wound from the lower side of the sub-pixel row back to the upper side of the sub-pixel row, and then continuously extends to the output end of the winding cycle; the scanning line B is routed from the lower side of the sub-pixel row to the upper side of the sub-pixel row after passing through the length of one pixel unit 300 by using the input end thereof as a starting point, and then is routed back to the lower side of the sub-pixel row from the upper side of the sub-pixel row after passing through the length of one first sub-unit 210, and then continuously extends to the output end of one routing period; the scan line C starts at its input end, winds from the lower side of the sub-pixel row to the lower side of the next sub-pixel row, winds back from the lower side of the next sub-pixel row to the lower side of the sub-pixel row after passing through the length of the first sub-unit 210, and then continues to extend to the output end of one winding cycle. Each sub-pixel 110 is electrically connected to the adjacent scan line 120 from the lower side thereof, which satisfies the requirement that the first sub-unit 210 and the second sub-unit 220 are electrically connected to different scan lines 120 in the same pixel unit group 200.

It should be noted that, in the above winding manner, each scan line 120 only winds along the column direction Y of the sub-pixel matrix twice in one period, and the increase amount of the length of the corresponding scan line 120 is small, so that on the premise of ensuring the normal display of each sub-pixel 110, the reduction of the length of the scan line 120 is facilitated, and the problem of obvious signal attenuation caused by the overlong length of the scan line 120 is avoided.

Optionally, fig. 2 is a schematic structural diagram of another array substrate provided in an embodiment of the present invention. Note that the input end of each scan line 120 is located at the left side of the scan line, and the output end of each scan line 120 is located at the right side of the scan line. As shown in fig. 2, along the extending direction of the data line 130 (the column direction Y of the sub-pixel matrix), of the three scanning lines 120 corresponding to each sub-pixel row, the input end of one scanning line 120 is disposed at the upper side of the sub-pixel row, and the input ends of the other two scanning lines 120 are sequentially arranged at the lower side of the sub-pixel row. The three scanning lines 120 are periodically wound, and fig. 2 only shows the structure of one period. Continuing to refer to fig. 2, every four pixel unit groups 200 that are continuously arranged correspond to a winding cycle, and with the scan line 120 whose input end is disposed at the upper side of the sub-pixel row as the scan line D, the scan line 120 whose input end is disposed at the lower side of the sub-pixel row and disposed adjacent to the sub-pixel row as the scan line E, and the remaining scan line 120 as the scan line F, in the same cycle, the scan line D starts from its input end, winds from the upper side to the lower side of the sub-pixel row after passing through a length of the first sub-unit 210, winds from the lower side to the upper side of the sub-pixel row after passing through a length of the second sub-unit 220 and the first sub-unit 210, and then continuously extends to the output end of a winding cycle; the scanning line E is wound from the lower side to the upper side of the sub-pixel row after the length of the first sub-unit 210 and the length of the two pixel units 300 from the input end of the scanning line E, and is wound from the upper side to the lower side of the sub-pixel row after the length of the second sub-unit 220 and the length of the first sub-unit 210, and then continuously extends to the output end of one winding period; the scan line F starts at its input end, goes through a first subunit 210 length, and then goes from the lower side of the sub-pixel row to the lower side of the next sub-pixel row, goes through a second subunit 220 and a first subunit 210 length, and then goes from the lower side of the next sub-pixel row back to the lower side of the sub-pixel row, and then continues to extend to the output end of one routing period.

It should be noted that, in the above winding manner, each scan line 120 is also wound along the column direction Y of the subpixel matrix only twice in one period, and the period length is longer, so that the increase amount of the length of the corresponding scan line 120 is smaller, on the premise of ensuring normal display of each subpixel 110, the length of the scan line 120 is further reduced, and the problem of obvious signal attenuation caused by the overlong length of the scan line 120 is avoided.

Optionally, fig. 3 is a schematic structural diagram of another array substrate provided in an embodiment of the present invention. Fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. When the pixel unit 301 includes an even number of sub-pixels 110, for example, as shown in fig. 3 and 4, the pixel unit 301 includes a red sub-pixel 111, a green sub-pixel 112, a blue sub-pixel 113, and a white or yellow sub-pixel 114, each adjacent two pixel units 301 in a sub-pixel row form a pixel unit group 200, the pixel unit group 200 includes a third sub-unit 230 and a fourth sub-unit 240, the third sub-unit 230 includes one pixel unit 301, and the fourth sub-unit 240 includes one pixel unit 301, wherein the third sub-unit 230 and the fourth sub-unit 240 are electrically connected to any two scanning lines 120 of the three scanning lines 120 correspondingly connected to the sub-pixel 110 row, respectively.

It should be noted that, on the basis of the advantages of the red subpixel 111, the green subpixel 112, and the blue subpixel 113, the arrangement of the white or yellow subpixel 114 can also improve the brightness and the color expression of the display panel, and particularly, the increase of the transmittance improves the gray scale and the brightness expression of the display panel, which is beneficial to further improving the display effect of the display panel. It is understood that, in other embodiments of this embodiment, the number and color of the sub-pixels included in the pixel unit 301 may be other situations, and this embodiment is not limited in this respect.

It should be noted that, different from the scheme that the pixel unit 301 includes odd-numbered sub-pixels 110, when the pixel unit 301 includes even-numbered sub-pixels 110, the sub-pixels 110 in each pixel unit 301 having the same emission color have the same signal polarity in the same frame, so that on the premise that two adjacent sub-pixels having the same emission color and the same signal polarity in the same frame form one sub-pixel group, the maximum number of the sub-pixels 110 that can be electrically connected in each scan line 120 and are continuously arranged can only be the total number of the sub-pixels 110 in one pixel unit 301, and therefore the third sub-unit 230 and the fourth sub-unit 240 each include one pixel unit 301. The rest of the settings are the same as the setting modes associated with the pixel unit 301 including the odd number of sub-pixels 110, and are not repeated here, and the specific structure is shown in fig. 3 and 4.

Fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. As shown in fig. 5, on the basis of the array substrate shown in fig. 1, the plurality of scan lines 120 in the array substrate shown in fig. 5 include a first scan line 121, a second scan line 122 and a plurality of third scan lines 123, and the first scan line 121 and the second scan line 122 are respectively disposed on two opposite sides of the plurality of third scan lines 123 along the column direction Y of the matrix. The number of sub-pixels 110 electrically connected to the first scan line 121 and the second scan line 122 is less than the number of sub-pixels 110 electrically connected to the third scan line 123. The array substrate further comprises a plurality of first virtual sub-pixels 510 and a plurality of second virtual sub-pixels 520, the first virtual sub-pixels 510 and the second virtual sub-pixels 520 are equal to the sub-pixels 110 in size, the first virtual sub-pixels 510 and the second virtual sub-pixels 520 are respectively arranged in non-display areas on two opposite sides of the sub-pixel matrix along the column direction Y of the matrix, the first virtual sub-pixels 510 are electrically connected with the first scanning lines 121, the second virtual sub-pixels 520 are electrically connected with the second scanning lines 520, and the number of the sub-pixels 110 electrically connected with each scanning line 120 is equal.

It should be noted that, the arrangement mode makes the loads on each scan line 120 equal, and avoids the problem that the luminance of the corresponding sub-pixels 110 is different due to different loads on the scan lines 120.

Further, fig. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. As shown in fig. 6, in addition to the array substrate shown in fig. 5, the array substrate shown in fig. 6 may further include a plurality of third dummy sub-pixels 530 and a complementary scan line 124, the complementary scan line 124 is disposed on a side of the plurality of scan lines 120 away from the plurality of first dummy sub-pixels 510, and the plurality of third dummy sub-pixels 530 are electrically connected to the complementary scan line 124. Such an arrangement enables the total number of scan lines 120 to be even, corresponding to the dual gate structure of the related art. With reference to fig. 6, the total number of all the dummy sub-pixels may be equal to the number of the sub-pixels 110 in each row of the sub-pixels 110 in the display area, and the arrangement manner and the position relationship of the scan lines 120 electrically connected to the dummy sub-pixels are the same as the related arrangement of the sub-pixels 110 in each row in the display area, so that the overall structure of the array substrate is neat and beautiful.

It should be noted that the above-mentioned arrangement manner of adding the dummy sub-pixels to make the load of each scan line the same is applicable to the array substrate structures shown in fig. 2, fig. 3 and fig. 4, and details thereof are not repeated here.

Illustratively, the length of each scan line 120 is h times the length of a row of the matrix, and h is in a range of 1 or more and 1.5 or less.

It should be noted that, in order to reduce the winding complexity and ensure that each sub-pixel 110 can normally display, it is usually configured that every two pixel units arranged in series are electrically connected to the same scan line 120, and the same scan line 120 is disturbed twice in the column direction Y of the sub-pixel matrix in each winding period, at this time, compared with the case of not performing the winding process, the increased winding length a is 2b, and b is the distance from the first side to the second side of the sub-pixel row in the column direction Y of the sub-pixel matrix. In this case, the routing cycle at least includes four pixel units, and the number of the sub-pixels 110 in the pixel unit is greater than or equal to 3 in the conventional arrangement, so that when the routing cycle takes the minimum length in the row direction X of the sub-pixel matrix, the routing cycle includes four pixel units, and each pixel unit includes 3 sub-pixels 110. It is understood that, in the case where the increased winding length in the winding period is a certain value, the smaller the length of the winding period in the row direction X of the subpixel matrix, the larger h is, and based on the above analysis, the winding period includes four pixel units, and h takes the maximum value when each pixel unit includes 3 subpixels. On the other hand, for a structure in which one pixel unit is configured for every three sub-pixels, the length of the pixel unit in the conventional setting is equal to the distance from the first side to the second side of the sub-pixel row in the column direction Y of the sub-pixel matrix, so that when the length of the pixel unit is 1 and h is the maximum value, the length of the winding period is 4, and the increased winding length is 2, where h is (4+2)/4 is 1.5. In addition, for the winding scheme, the scan line needs to be wound from one side to the other side of the corresponding sub-pixel row, the length of the scan line must be increased, namely the length of the winding period is 4, and the length of the scan line after winding is more than 4, namely h >4/4 is 1.

Fig. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. On the basis of the array substrate shown in fig. 1, the array substrate shown in fig. 7 further includes a plurality of touch signal lines 600. Illustratively, as shown in fig. 7, the pixel unit in the array substrate includes a red sub-pixel 111, a green sub-pixel 112, and a blue sub-pixel 113 arranged in sequence along a row direction X of the matrix, and a touch signal line 600 is disposed between adjacent red sub-pixels 111 and blue sub-pixels 113.

It should be noted that the touch signal line 600 is used for transmitting a touch signal to the touch electrode, and the touch signal line 600 with the touch signal interferes with an electric field formed by the pixel electrode and the common electrode in the display panel, and the electric field is used for controlling the rotation of the liquid crystal molecules, so that the normal rotation of the liquid crystal molecules is affected, and the display effect of the display panel is affected. The recognition degree of human eyes to green is higher than that to red and blue, and the touch signal line 600 is arranged between the red sub-pixel 111 and the blue sub-pixel 113, so that the influence of the touch signal line 600 on the green sub-pixel 112 is smaller than that of the red sub-pixel 111 and the blue sub-pixel 113, and the influence of the touch signal line 600 on the display effect of the display panel is further reduced in the aspect of visual effect.

It is understood that the array substrate in any other embodiments provided in the present invention may be provided with touch signal lines, when the pixel arrangement is the same as that in fig. 7, the touch signal lines may be provided in the same manner as in fig. 7, and when the pixel arrangement is different from that in fig. 7, the touch signal lines may be provided at suitable positions according to specific application requirements.

Fig. 8 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. On the basis of the array substrate shown in fig. 1, the array substrate shown in fig. 8 further includes a driving chip 150, the driving chip 150 is disposed in the non-display region 12 on one side of the matrix, and the data port 140 is electrically connected to an output end of the driving chip 150.

As shown in fig. 8, the array substrate further includes a display area 11, a non-display area 12 disposed around the display area 11, a plurality of sub-pixels 110 disposed in the display area 11, the display area 11 for displaying images, and the non-display area 12 for disposing peripheral circuits.

It should be further noted that the driving chip 150 is used for providing driving signals to the data lines 130 and the scan lines 120 to drive the sub-pixels 110 to emit light, and in order to avoid the driving chip 150 from affecting normal display, the driving chip 150 is disposed in the non-display region 12.

With reference to fig. 8, the two data lines 130 electrically connected to the two sub-pixels 110 in the same sub-pixel group 400 are electrically connected to the same data port 140 through the cross-line structure 160, and the cross-line structure 160 and the driving chips 150 are located in the non-display region 12 on the same side of the matrix.

Illustratively, it is noted that any two electrically connected data lines 130 are electrically connected through a connecting line, as shown in fig. 8, a vertical projection of any connecting line on a substrate in the array substrate intersects a vertical projection of at least one data line 130 on the substrate, and a cross-line structure 160 is used as a different-layer connecting line to electrically connect two data lines 130, so that the problem of cross electrical connection between the connecting line and the data line 130 on the same layer can be avoided, thereby avoiding mutual interference of signals and ensuring normal display of the display panel.

Fig. 9 is a schematic sectional view along a broken line LM in fig. 8. As shown in FIG. 9, the cross-line structure 160 is disposed in a different layer from the data line 130.

It should be noted that, as shown in fig. 9, the sub-pixel 110 may include a thin film transistor 101 and a pixel electrode 102 electrically connected to the drain electrode 211 of the thin film transistor 101, the scan line 120 is disposed on the same layer as the gate electrode 213 of the thin film transistor 101, and the data line 130 is disposed on the same layer as the source electrode 212 and the drain electrode 211 of the thin film transistor 101. In a region not shown in fig. 9, the gate electrode 213 of the thin film transistor 101 is electrically connected to the scan line 120 corresponding to the sub-pixel 110, and the source electrode 212 of the thin film transistor 101 is electrically connected to the data line 130 corresponding to the sub-pixel 110.

Illustratively, with continued reference to FIG. 9, the flying lead structure 160 may be disposed in layer with the scan lines 120. It is understood that, in other embodiments of the embodiment of the present invention, the crossover structure 160 may also be disposed in the same layer as the other structures, or may occupy a film layer independently, as long as it is ensured that the crossover structure is disposed in a different layer from the data line 130, which is not specifically limited in this embodiment of the present invention.

Fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 10, the display panel 20 includes the array substrate 10 according to any embodiment of the present invention. Since the display panel 20 provided by the present invention includes the array substrate 10 according to any embodiment of the present invention, the same or corresponding advantages of the array substrate 10 included therein are provided, and details are not repeated herein.

Fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 11, the display device includes the display panel provided in any embodiment of the present invention. Since the display device 30 provided by the present invention includes the display panel 20 according to any embodiment of the present invention, and has the same or corresponding advantages as the display panel 20 included therein, the description thereof is omitted here.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An array substrate, comprising: the plurality of sub-pixels are arranged in a matrix, the light-emitting colors of two adjacent sub-pixels in the same row of sub-pixels are different, the light-emitting colors of the sub-pixels in the same row are the same, the signal polarities of the sub-pixels in the same row are the same, and the signal polarities of the sub-pixels in two adjacent rows are different in the same frame picture;

the sub-pixels in each row are electrically connected with the three scanning lines; in one sub-pixel row, at least two sub-pixels with different colors form a pixel unit, and each sub-pixel in the same pixel unit is electrically connected with the same scanning line; each adjacent multiple pixel units form a pixel unit group; each pixel cell group comprises two sub-cells; each sub-unit comprises at least one pixel unit, and each sub-pixel in the same sub-unit is connected with the same scanning line; different sub-units in one pixel unit group are connected with different scanning lines;

for a row of sub-pixels, any two sub-pixels with the same light-emitting color and the same signal polarity in the same frame picture form a sub-pixel group; the positions of the scanning lines are set in a winding mode, so that two sub-pixels in one sub-pixel group are electrically connected to different adjacent scanning lines from the same side, and two data lines electrically connected with the two sub-pixels in the same sub-pixel group are electrically connected with the same data port.

2. The array substrate of claim 1, wherein the data lines electrically connected to the sub-pixel columns are located on the same side of the sub-pixel columns along the row direction of the matrix.

3. The array substrate of claim 1, wherein when the pixel unit comprises an odd number of sub-pixels, every adjacent four pixel units in a sub-pixel row form a pixel unit group;

the pixel unit group comprises a first sub-unit and a second sub-unit, the first sub-unit comprises two adjacent pixel units, the second sub-unit comprises two adjacent pixel units, each sub-pixel in the same first sub-unit is electrically connected with the same scanning line, each sub-pixel in the same second sub-unit is electrically connected with the same scanning line, and the first sub-unit and the second sub-unit are respectively electrically connected with any two scanning lines in three scanning lines correspondingly connected with the sub-pixel row.

4. The array substrate of claim 1, wherein when the pixel unit comprises an even number of sub-pixels, every two adjacent pixel units in a sub-pixel row form a pixel unit group;

the pixel unit group comprises a third sub-unit and a fourth sub-unit, the third sub-unit comprises one pixel unit, the fourth sub-unit comprises one pixel unit, and the third sub-unit and the fourth sub-unit are respectively and electrically connected with any two scanning lines of the three scanning lines correspondingly connected with the sub-pixel row.

5. The array substrate according to claim 3 or 4, wherein the plurality of scan lines comprise a first scan line, a second scan line and a plurality of third scan lines, and the first scan line and the second scan line are respectively disposed on two opposite sides of the plurality of third scan lines along a column direction of the matrix; the number of the sub-pixels electrically connected with the first scanning line and the second scanning line is less than that of the sub-pixels electrically connected with the third scanning line;

the array substrate further comprises a plurality of first virtual sub-pixels and a plurality of second virtual sub-pixels, the first virtual sub-pixels and the second virtual sub-pixels are equal to the sub-pixels in size, the first virtual sub-pixels and the second virtual sub-pixels are respectively arranged in non-display areas on two opposite sides of the matrix along the column direction of the matrix, the first virtual sub-pixels are electrically connected with the first scanning lines, and the second virtual sub-pixels are electrically connected with the second scanning lines; the number of the sub-pixels electrically connected to each scanning line is equal.

6. The array substrate of claim 1, wherein the length of each scan line is h times the length of a row of the matrix, and the range of h is less than or equal to 1.5.

7. The array substrate of claim 1, further comprising a driving chip disposed in the non-display region on one side of the matrix, wherein the data port is electrically connected to an output terminal of the driving chip.

8. The array substrate of claim 7, wherein two data lines electrically connected to two subpixels of a same subpixel group are electrically connected to a same data port through a cross-line structure, and the cross-line structure and the driving chip are located in a non-display region on a same side of the matrix.

9. The array substrate of claim 8, wherein the cross-line structure is disposed in a different layer from the data lines.

10. A display panel comprising the array substrate according to any one of claims 1 to 9.

11. A display device comprising the display panel according to claim 10.