JPH0654420B2 - Interface circuit of liquid crystal display device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit of a liquid crystal display device, and more particularly, to a liquid crystal display using only a separate video signal of a CRT display device which is widely used in personal computers and the like. The present invention relates to an interface circuit which generates display data and timing signals necessary for operating the device and can supply a light, thin, short and small display terminal by replacing a CRT display device with a liquid crystal display device.

[Outline of Invention]

The present invention utilizes a display data synchronization signal of a CRT display device or a separate video signal in which a composite signal is separated to display input data without storing the display data in a frame buffer memory (RAM). Real-time processing converts the display data into a mixture of red, green, and blue display data, and with the same drive circuit configuration as before, the interface of a liquid crystal display device that has an interface function capable of color display and an interface function capable of monochrome display. It is about circuits.

[Conventional technology]

Since liquid crystal display devices have characteristics of thinness, low voltage, and low power consumption, they have recently been put into practical use as display terminals for personal computers, word processors, etc. by means of large dot matrix panels. Today, C
A liquid crystal interface circuit that can be directly connected to a CRT control circuit has been developed for use as a display terminal of a portable personal computer instead of the RT.

However, the interface circuit of the conventional liquid crystal display device is designed by the idea of driving the liquid crystal panel even during the blanking period of the CRT display device. Therefore, for display data, a frame buffer memory is prepared, the display data is once written into the frame buffer memory, and then read sequentially. Further, since the conventional interface circuit is dedicated to monochrome display, the amount of display information is insufficient, such as in the case of graphic display. That is, since one or two of red, green, and blue color display data are used for a simple matrix liquid crystal panel to simply perform ON / OFF display, the display device is compared to a CRT display device. It wasn't attractive enough. However, on the other hand, the technology of color coloring filter was established on the surface of the transparent electrode of the liquid crystal panel,
A panel with a built-in active element such as a TFT (thin film transistor) and a non-linear element such as MIM and MSI, or
Despite the development of a new liquid crystal panel having a memory function such as a smectic liquid crystal, an interface circuit of a color liquid crystal display device has not yet been developed. Therefore, it is necessary to install the interface circuit of the monochrome liquid crystal display device which requires the frame buffer memory for red, green and blue.

[Problems to be solved by the invention]

As described above, in the interface circuit of the conventional liquid crystal display device, it is necessary to prepare a frame buffer memory as an external circuit and write and read data under the control of the interface circuit. Therefore, the cost of the circuit configuration becomes high, the circuit configuration becomes complicated, and it is difficult to combine them into a small display terminal. Further, it is an interface circuit dedicated to monochrome display, and in order to configure an interface circuit of a color liquid crystal display device, it is necessary to prepare three sets of the monochrome display interface circuit, which is simply three times higher. There was price and complexity of configuration.

The present invention has been made to solve the above problems, and has a function of directly interfacing display data and timing signals to a liquid crystal display device by real-time processing of a video signal of a CRT display. It is an object of the present invention to provide an interface circuit applicable to a liquid crystal display device.

[Means for solving problems]

In order to solve the above problems, the present invention provides an interface circuit for a liquid crystal display device, which receives a separate video signal for a CRT display device and converts it into a display data signal and a timing signal for operating the liquid crystal display device. S / P conversion circuit for converting G and B color display data in parallel, and a color mixture color scheme for converting the output of the S / P conversion circuit into R, G, B bit-wise regular color mixture data Means, and the color display data processing circuit section comprising a first switching circuit group for switching the mixed color data in a time division manner, and R, G,
A monochrome display data processing circuit section having a second switching circuit group for switching the output of at least one display data S / P conversion circuit of B is provided.

〔Example〕

 Next, an embodiment of the present invention will be described.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.
The figure is a timing diagram for supplementing the explanation of the operation of the circuit of FIG.

In FIG. 1, Hsyc is a horizontal synchronizing signal, Vsyc is a vertical synchronizing signal, CK is a dot clock signal, RD, GD,
BD is display data of red, green, and blue, respectively. These Hsyc, Vsyc, CK, RD, GD and BD are equivalent to interface signals to the CRT display device. 1 is an X-axis display position adjustment circuit that counts the dot clock CK and adjusts the display position in the X-axis direction.
The Y-axis display position adjusting circuit 3 which counts the horizontal synchronizing signal Hsyc and adjusts the display position in the Y-axis direction is the output of the X-axis and Y-axis display position adjusting circuit 1.4 and the dot clock CK.
AND circuit which receives as input, 6 is a 1/8 frequency divider circuit for dividing the clock signal P ₁ output from the AND circuit 3 by 1/8, and 7 is an output of the 1/8 frequency divider circuit 6. further dividing the P _2, the X-axis display position adjusting circuit frequency dividing circuit for generating a reset signal P ₃ reset, 10, 11, 12, red,
Shift register circuits for shifting green / blue display data, 13, 14, 15 are latch circuits for temporarily latching the display data of the shift registers 10, 11, 12 41-46
Is a switching circuit for time-divisionally switching the display data of the latch circuits 13 to 15 and outputting the display data to the X electrode drive circuit (X driver) of the liquid crystal display device, and 28 is the switching circuit 41 to It is a shift register for switching 46 in a time division manner.

24 and 25 are D-type flip-flop circuits for receiving the clock signal P ₂ and generating a latch signal P ₄ .
(D type F / F circuit). 21 is the latch signal P ₄
Is a set-reset flip-flop circuit for setting by the occurrence of. Reference numerals 16 and 17 are a D-type flip-flop circuit and a NOR circuit for generating the set pulse signal P ₉ when the output T _{2 of the} Y-axis display position adjusting circuit 4 rises to "H". Reference numeral 18 is a flip-flop circuit for generating a set output by the set pulse signal P ₉ , and 47 and 48 are D-type flip-flop circuits for delaying the output of the flip-flop circuit 18. The output FRM of the D-type flip-flop circuit 48 is
It is a frame signal. Reference numeral 20 is a flip-flop circuit for dividing the signal of the frame signal FRM by 1/2. The output of the flip-flop circuit 20 is a liquid crystal alternating drive signal M. In addition, LK is a latch signal of a latch circuit that has the display data transferred to the X-axis drive circuit built in the X-axis drive circuit. Reference numeral 31 is a 1/4 frequency divider circuit for dividing the clock signal P ₁₀ by 1/4. Reference numeral 33 is a flip-flop circuit that divides the output P ₁₃ of the frequency dividing circuit 31 into 1/2. Reference numerals 39 and 40 are switching circuits for switching the display data of the latch circuit 15. Reference numerals 35, 36 and 37 are AND circuits and OR circuits, and select gates for selecting the shift clock SK of a 4-bit parallel shift register incorporated in the X electrode drive circuit for display data in the case of monochrome or color display. It constitutes the circuit.

Next, the operation of the first embodiment of the present invention shown in FIG. 1 will be described.

The X-axis display position adjustment circuit 1 starts counting the dot clock CK when the horizontal synchronization signal Hsyc is input. When this count value matches the set value of the blanking period of the display data, the output T _{1 of the} X-axis display position adjustment circuit ₁
Rises to "H". This blanking period setting is
It can be adjusted in 1-dot units by an external setting means such as a digital switch. The Y-axis display position adjustment circuit 4
When the vertical synchronizing signal Vsyc is input, the horizontal synchronizing signal Hsyc starts counting. This count value is Y of the display data.
To match the set value of the blanking period in the axial direction, the output T ₂ of the said Y-axis display position adjusting circuit 4 rises to "H". The setting of the blanking period can be adjusted in 1-dot units by an external setting means such as a digital switch as described above. When the outputs T ₁ and T _{2 of the} X-axis and Y-axis position adjusting circuits both rise to "H",
It becomes the display starting point (home position) and AND circuit 3
As a result, the clock signal P ₁ is output. The clock signal P ₁ is input to the 1/8 frequency divider circuit 6 and the shift registers 10, 11, 12. The display data RD, GD, BD are shifted to the shift registers 10, 11, 12 for each clock in order to use the clock signal P ₁ as a shift clock. The output P ₂ of the 1/8 frequency divider circuit 6 is the D-type flip-flop circuit 24 and N.
The OR circuit 25 generates a latch signal P ₄ each time 8 clock signals P ₁ are input, and the parallel display data of the shift registers 10, 11 and 12 is transferred to the latch circuits 13 and 1.
Latch to 4,15 and perform S / P conversion. The latch signal P ₄ is
Inverted by inverter 26, flip-flop circuit
Since 21 is set, the AND circuit 22 outputs the clock signal P
_The clock signal P ₁₀ for starting the output of ₁₀ is the 1/2 frequency dividing circuit 2
It is divided by 7 and input as the shift clock of the shift register 28. The shift register 28 is a NOR circuit
Since the output of 29 is used as shift data, it operates as a quaternary ring counter, and the switching control signals P ₅ , P ₆ , P
₇ is generated and the switching circuits 41 and 42, 43 and 44, 45 and 46 are time-divisionally switched on to display data (UD _{0 to} U
D ₃ ) and (LD _{6 to} LD ₃ ) are output in parallel.
The clock signal P ₁₀ is output by the flip-flop circuit 23.
It is divided into 1/2 and outputs the clock signal P ₈ .

Further, the flip-flop circuit 23 is a shift register.
Since the shift data of 28 is reset by the signal inverted by the inverter 30, 8 clocks of the clock signal P ₁₀ are input, the clock signal P ₈ is output for 3 clocks, and the shift clock SK is passed through the AND circuit 36 and the OR circuit 37.
To occur. The outputs of the latch circuits 15, 14, 13 are R, G, B.
In order to obtain mixed color display data of (red, green, blue), it is input to the switching circuits 41 to 46 as follows. The switching circuits 41 to 46 are composed of 4-bit parallel transmission gates, and their inputs are latch circuits 1.
When from the first bit of the 5,14,13 and 8 bits of _{R 1, G 1, B 1} ~R 8, G 8, B 8, the switching circuit 41 to 46 is connected as in the table below.

As described above, the switching circuits 41, 43, 45 and 42, 44, 46 have the upper display data UD _{0 to} UD ₃ and the lower display data LD _{0 to} L, respectively.
D ₃ is grouped and color display data RD,
The display data of GD and BD are alternately separated from the first bit and input. Therefore, the display data UD ₀ ~
UD ₃ generates an output of (R ₁ , B ₁ , G ₂ , R ₃ ) (B ₃ , G ₄ ...), and the display data LD _{0 to} LD ₃ are (G ₁ , R ₂ , B ₂ , G ₃ ) (R ₄ , B
₄ ...)) is generated.

Next, the timing signal to the liquid crystal display device will be described.

Output T ₂ of the Y-axis display position adjusting circuit 4 is inverted by the inverter 5 rises to "H", the generating a set pulse P ₉ by D-type flip-flop circuit 16 and the NOR circuit 17, sets a flip-flop circuit 18 To do. And
The clock signal P ₂ of the 1/8 frequency divider circuit 6 is supplied to the frequency divider circuit 7
Is counted, the display data in the X-axis direction is counted until it is input (for example, 700 counts), and then D
The flip-flop circuit 9 and the NOR circuit 8 generate the reset signal P ₃ , and the X-axis display position adjusting circuits 1 and 1/8
Frequency divider circuit 6, frequency divider circuit 7, and flip-flop circuit 18
To reset. The reset signal P _3, the X electrode driving circuit latch signal of the latch circuit built in the (X driver) LK and the shift clock YSCL in the shift register built in the Y electrode drive circuit (Y driver). The output of the flip-flop circuit 18 is delayed by the D-type flip-flop circuits 47 and 48 to output the frame signal FRM, which becomes the scanning start data of the Y electrode drive circuit (Y driver). The frame signal FRM
Is divided by the 1/2 divider circuit 20, and for each frame,
The alternating drive signal M is generated so that the polarity of the drive voltage is inverted, and is output to the X electrode and Y electrode drive circuits.

The above is the description of the operation for color display. next,
The case of monochrome display will be described.

The clock signal P ₁₀ is input to the 1/4 frequency dividing circuit 31, outputs a 1/4 frequency dividing output P ₁₃ , is further frequency divided by 1/2 by the 1/2 frequency dividing circuit 33, and the switching circuits 39, 40. Output the switching control signals P ₁₄ and P ₁₅ . The inverted output of the frequency-divided output P ₁₃ of the 1/4 frequency-dividing circuit 31 is output to the monochrome shift clock SK of the X-electrode drive circuit (X driver) via the AND circuit 35 and the OR circuit 37. . Exclusive OR circuit 4
Reference numerals 7, 48 and 49 denote polarity switching circuits for inverting or normal rotating the display data RD, GD, BD.
_{When 1} is ON, the display data RD, GD, BD are inverted, and when OFF, the display data is normally rotated.
GA / Posi switching display is possible. The switch is SW ₂
Is for selecting color display or monochrome display. When the switch SW ₂ is OFF, the inverted output of the output P ₁₃ of the 1/4 frequency divider circuit 31 is the selection gate circuit 35, O.
At the same time as generating the shift clock SK for monochrome display through the R circuit 37, the outputs of the switching circuits 39 and 40 are activated and the outputs of the switching circuits 41 to 46 are set to the high impedance state. Conversely, switch SW ₂
When is ON, the clock signal P ₈ of the flip-flop circuit 23 passes through the AND circuit 36 and the OR circuit 37 to generate the shift clock SK for color display, and at the same time, activates the outputs of the switching circuits 41 to 46, It operates so as to switch the outputs of the switching circuits 39 and 40 to high impedance.

As described above, the display mode of color display or monochrome display can be switched by the voltage level of the selection terminal S ₂ . Also, the selection of NEGA / Posi display can be switched by setting the voltage level of the selection terminal S ₁ .

In the timing chart of FIG. 2, (A) shows the X-axis and the Y-axis.
The timing of outputs T ₁ and T ₂ of the axis display position adjusting circuit is shown. (B) is the timing of the clock signals P ₁ and P ₃ , and (C) is the switching control signals P ₅ , P ₆ , P.
₇ and display data _{UD 0 ~UD 3, LD 0 ~LD} 3 timing, (D), the display data LD ₀ to Ld ₃ monochrome display
(E) shows the timing of the shift clock CK, the latch clock LK, the frame signal FRM, and the AC drive signal M, which are the timing signals to the drive circuit of the liquid crystal display device.

FIG. 3 shows an embodiment of the electrode configuration of the color liquid crystal panel in the case of color display according to the present invention. The order in which the electrodes are colored is not limited to this embodiment. FIG. 4 shows the system configuration of an embodiment of the present invention. (A) is a system configuration of monochrome display, (B)
Shows an example of system configuration of color display,
This allows a deeper understanding of the present invention.

〔The invention's effect〕

As described above, according to the present invention, since the display signal and the timing signal of the liquid crystal display device are converted in real time using the interface signal of the CRT display device, the frame buffer memory is not required. A small, low-priced liquid crystal display terminal can be manufactured by using a gate array IC.
The interface circuit for color display, which did not exist in the past, can now be supplied, and the liquid crystal display device can be made more attractive. With one interface circuit, it is possible to select a display mode of monochrome display or color display. Since the same conventional drive circuit can be used, there is no need to develop a drive circuit dedicated to color, which is a great effect.

The present invention also relates to an active matrix including a non-linear resistance element such as MSI and MIM, an active matrix including a switching transistor such as a TFT panel, and a ferroelectric liquid crystal panel having a memory property such as a smectic liquid crystal panel. In addition, even in the blanking period, it is particularly effective for these new type liquid crystal panels that utilize the memory characteristics of the device.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing the timing of FIG. 1, FIG. 3 is an electrode configuration diagram of an embodiment of a color liquid crystal panel, and FIGS. 4 (A) and 4 (B) are diagrams showing a system configuration. 1 …… X axis display position adjustment circuit 2 …… Y axis display position adjustment circuit 3 …… AND circuit 10,11,12 …… Shift register 13,14,15 …… Latch circuit 39 to 46 …… Switching circuit 6 ・ ・ ・… 1/8 divider circuit 7 …… divider circuit 9,16,24,47,48 …… D-type flip-flop circuit 18,21,23 …… flip-flop circuit 20,27,33 …… 1/2 minute Frequency circuit 31 …… 1/4 frequency divider circuit

Claims (2)

[Claims] 1. An interface circuit of a liquid crystal display device, which receives a separate video signal and converts it into a display data signal for operating the liquid crystal display device, wherein each of R, G and B inputs serial color display data. , R, G, B each have a S / P conversion circuit for converting and outputting parallel color display data, and a color mixture color scheme for making the R, G, B parallel color display data mixed color data. Means, a display data processing circuit section including a first switching circuit group including a plurality of switching circuits for inputting the color mixture data, and each output bit of the switching circuit is electrically connected to each output bit of the other switching circuit. To form an output terminal composed of a plurality of bits, and switching the plurality of switching circuits in time series to connect each of the output terminals. An interface circuit for a liquid crystal display device, which outputs a serial display data signal composed of mixed color data for each bit. 2. The interface circuit according to claim 1, wherein the display data processing circuit has a second switching circuit group for inputting monochrome data from the S / P conversion circuit, and the first switching circuit. Display mode switching means for outputting a switching signal for switching a display mode to the circuit group and the second switching circuit group is provided, and each output bit of the second switching circuit group and the first switching circuit. Each output bit of the switching circuit included in the circuit group is electrically connected to form an output terminal composed of a plurality of bits, and the mixed color data and the monochrome data are switched according to the switching signal to display the data as a display data signal. An interface circuit for a liquid crystal display device, which outputs to an output terminal.