JPS62203131A - Color liquid crystal display device - Google Patents

Abstract

PURPOSE:To increase the amount of display information and to obtain an attractive display device by making a color liquid crystal display by using the interface signal of a CRT display device. CONSTITUTION:The device consists of a color liquid crystal panel, an X- electrode driving circuit 32 which drives X-axial electrodes, a Y-electrode driving circuit 30 which drives Y-axial electrodes, S/P converting circuits 8-10 which convert red, blue, and green serial display data into parallel data, storage circuits which store those parallel-converted display data, P/S conversion circuits 14-16 which convert the parallel display data into serial data, a selecting gate circuit which outputs the output signals of the P/S conversion circuits 14-16 selectively, and an S/P conversion circuit which converts the serial signal of the selecting gate circuit into a parallel signal. Then the device is further provided with an interface circuit where three independent serial display data of red, blue, and green are converted into one mixed display data of red, blue, and green and the data is converted into the parallel signal and inputted to an X-electrode driving circuit.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an interface circuit for a color liquid crystal display device, and in particular to a light, thin, short, and small interface circuit using interface signals of a CRT display device often used in personal computers. The present invention relates to a color liquid crystal display device having an interface circuit that can replace a liquid crystal display device.

(Summary of the Invention) The present invention uses interface signals of a CRT display to independently store independent color display data in a RAM, and when reading data, red and green data are stored independently.

This is an interface circuit that converts display data into mixed blue color and can be used as an interface for color display with the same drive circuit configuration as the conventional one.

(Prior Art) Liquid crystal display devices are thin, low voltage, and have low power consumption characteristics, so recently, large dot matrix panels have been used in personal computers.

It has come to be put into practical use as display terminal devices such as word processors. Today, as an alternative to CRTs, LSI circuits that can be directly connected to CRT interfaces have been developed for portable personal computers, and OA equipment manufacturers are producing interface circuits exclusively for liquid crystal display devices using gate arrays. This has led to a significant demand for LCDs. However, these liquid crystal display devices are
Although it is necessary to have display capacity to replace RT, since it is a monochrome display, it is insufficient in terms of the amount of display information, such as when displaying graphics.

Using one or two of the red, green, and blue color display data on the simple matrix display panel, you can simply turn ON or O.
Because of the FF display, the display device was not as attractive as a CRT display.

(Problems to be Solved by the Invention) As mentioned above, the interface circuits of conventional liquid crystal display devices were monochrome displays, which made them less attractive, but in recent years color liquid crystal display devices have been developed. Therefore, it is an object of the present invention to provide an interface circuit that is applicable to a liquid crystal display device and is capable of color display using interface signals of a color CRT.

(Means for solving problems) Next, specific examples of the present invention will be described.

The figure is an overall configuration diagram showing the entire color liquid crystal display device of the present invention. In the figure, ll5yC is a horizontal synchronization signal, vsycs;t, and vertical synchronization signals, DR and DG.

DB are red, green, and blue display data signals, respectively.

CK is a clock signal.

The Y-axis display area control circuit 1 is a control circuit that counts the horizontal synchronization signal H3yC and determines the display area in the Y-axis direction.
@Road. The X-axis display area control circuit 3 outputs the OFF signal GK.
A control circuit that counts and determines the display area in the X-axis direction. The sampling pulse generation circuit 5 is a circuit for dividing the frequency of the clock signal OK to sample and capture data during the display area period, and S/P conversion circuits 8 and 9.1.
0 is a conversion circuit for converting red, green, and blue serial display data into parallel data, RAM11゜12
．． 13 is a storage circuit for storing red, green, and blue parallel data; The P/S conversion circuit 14.15.16 is a conversion circuit that converts each parallel data of the memory circuit RAM11.12.13 into serial data, and an AND circuit 17.16.
18, 19 and the OR circuit 20 selectively take out the outputs of the respective P/S conversion circuits 14, 15° 16, red,
A selection gate circuit that generates mixed serial data of green and blue.

The S/P conversion circuit 31 is a conversion circuit that converts serial mixed display data into parallel. The write address counter 21 counts the addresses of the storage circuit RAM 11, 12, and 13 after being reset by the vertical synchronization signal vsyc. circuit. The latch pulse generation circuit 6 generates 8 sampling pulses from the sampling pulse generation circuit.
This circuit generates a latch pulse every count and latches the register of the S/P conversion circuit 8.9.10. Further, the latch pulse of the latch pulse generation circuit 6 becomes a counter input of the Write address counter.

The read address counter 24 is connected to the memory circuit RAM 11.
．． 12.13 read address counter circuit. The selection circuit 33 writes or reads the address of the memory circuit RAMI 1.12°13.
) select circuit for switching address lines. The frequency dividing circuit 7 is a circuit that divides the clock signal GK to reduce the frequency. The ring counter 22 is constituted by a ternary ring counter, and includes the P/S conversion conversion circuit, 15.
16 red and green.

A read address counter 24 is included in the 1/8 conversion counter 23, which is a circuit that generates a selection pulse to sequentially take out blue display data and obtain mixed serial display data from the selection gate circuit 17.18.19.20. counter input signal and memory circuit RAM11.12.13
This circuit generates a latch signal for latching display data to the P/S conversion circuits 14, 15, and 16, and generates a 1-pulse signal every 8 pulses of the input signal of the ring counter 22. A circuit that outputs.

The 1/4 counter 25 is a circuit for supplying a latch signal to the S/P conversion circuit 31 every time four output pulses from the frequency dividing circuit 7 are input. The shift clock generator 26 is a circuit that generates a shift clock signal for a 4-bit parallel shift register built in the X electrode drive circuit 32.

The latch clock generator 27 is connected to the X electrode drive circuit 3
2. and a circuit that generates a latch signal for latching data of the Y electrode drive circuit 30. The frame signal generation circuit 28 is Y
A circuit that generates a frame signal Pt (data for the Y electrode) to the ffi pole drive circuit 30.

The AC signal circuit 29 connects the X electrode drive circuit 32 . A circuit for switching the polarity of the drive signal of the Y electrode drive circuit 30. The color liquid crystal panel 34 is a liquid crystal panel in which red, green, and blue filters are attached to the transparent electrode of the X-axis electrode. The X electrode drive circuit 32 is a circuit for driving the X-axis electrode of the color liquid crystal panel 34.

The Y electrode drive circuit is a circuit for driving the Y-axis electrode. Next, the operation of the present invention will be explained.

The Y-axis display area control circuit 1 inputs Hsyc and outputs a Y-axis effective display area time signal to the AND circuit 2.

The clock signal output from the AND circuit 2 is input to the X-axis display area control circuit 3, and the X-axis display area tiIIt11 circuit 3 ANDs the signal of the X-axis effective display area time.
Output to circuit 4. Here, since both the Y@display area control circuit 1 and the X-axis display area control port 3 are constructed by a variable pull counter, the effective display area on the color liquid crystal panel in the X-axis and Y-axis directions is , can be set arbitrarily. Next, since the output of the AND circuit 4 is a clock signal in the valid display area, the display data OR, DG, and DB are valid.

The sampling pulse generation circuit 5 divides the output of the AND circuit 4 into 1/4, generates a sampling pulse, and generates an S/
A data sampling pulse is generated as a shift clock for the P conversion circuit 8.9.10. The latch pulse generation circuit 6 divides the sampling pulse of the sampling pulse generation circuit 5 by 1/8, and generates the S/P conversion circuit 8.9.1.
Outputs a latch signal to 0.

Furthermore, this latch pulse is applied to the write address counter 210 selection circuit 33 . Memory circuit RAM11゜12.1
It is input to the -rtte control signal of No. 3. Therefore, the above, S/P
The 8-bit parallel signal from the conversion circuit is sampled at a predetermined address and stored simultaneously in storage circuits 11, 12, and 13. Each time data is stored, the wr t tc address counter 21 is incremented by a latch pulse from the latch pulse generating circuit 6, and the display data is successively stored at a predetermined address.

Next, the read operation will be explained. When the latch pulse generation circuit 6 does not output a latch pulse, the selection circuit 33 selects the count output of the read address counter 24, and the memory circuit RAM 11, 12, 13 performs a read operation. Therefore, the display data in the memory circuit RAM 11, 12, 13 is addressed by the output of the read address counter 24 and input to the P/S conversion circuits 14, 15, 16. Display data is latched by the output of the 1/8 counter 23 into the P/S conversion circuits 14, 15, and 16.

The ring counter 22 is constituted by a ternary ring counter as described above, and this output signal is a shift clock signal for each of the P/S conversion circuits 14, 15.16, so that the P/S conversion circuit The serial signals of 14, 15, and 16 are input regularly and in order to the AND circuits 17, 18, and 19 of each selection gate circuit.
It is input together with each signal of the leading ring counter.

Therefore, the output of the OR circuit 20 of the selection gate circuit is
Red, n, blue, red... Outputs serial data in which blue display data is mixed. This mixed red,
The green and blue serial data are sent to the S/P conversion circuit 31.
Powered. The output frequency-divided by 1/4 by the 1/4 counter 25 is input as a touch signal to the S/P conversion circuit 31, so the S/P conversion circuit 31 (red, green, blue,
Red-green.

blue, red, green), (blue, red, green, blue), (red, green.

Convert display data to parallel data (blue, red)...

The shift clock generator 26 delays the output signal of the 1/4 counter 25 in order to supply the display data of the S/P conversion circuit 31 with a shift clock of the 4-bit parallel shift register of the X electrode drive circuit 32. to generate a shift clock.

Furthermore, the latch clock generator 27 is a circuit that generates a latch signal for latching the display data of the Xff1 electrode drive circuit 3204-bit parallel shift register, and when the display data of the X01l electrode is shifted to the terminal end, the latch signal is generated. A clock is generated, display data is latched at the same time, and the X electrodes are driven at the same timing.

Furthermore, the display data of Y @m pole is shifted and the next Y
This becomes a shift clock signal that drives the shaft electrode. The frame signal generation circuit 28 is a circuit that generates a frame signal that becomes the display data of the Y electrode drive circuit 28, and divides the output of the latch clock generator 27 to generate the first Y
@Outputs display data for selecting group electrodes. Furthermore, this frame signal generation circuit 28 clears the output of the read address counter 24 to O, and clears the output of the read address counter 24 to the memory circuit RA.
A reset pulse is generated to set the address of M11, 12, and 13 to address O. As described above, the present invention can directly replace the red, green, and blue display data of a conventional CRT display with a color liquid crystal panel, and the red, green, and stomach display data can be directly replaced with a color liquid crystal panel. display data, RA
By adding a P/S conversion circuit and a selection gate circuit, the system configuration can be treated in the same way as a conventional monochrome liquid crystal display system configuration.

(Effects of the Invention) As described above, according to the present invention, color display on a liquid crystal can be easily performed using interface signals of a CRT display, which increases the number of display information providers and makes the display device attractive. It can be done. Furthermore, the same drive circuit as for monochrome can be used, and there is no need to develop a drive circuit exclusively for color, which has great effects.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. 1... Y-axis display area control circuit 2... AND circuit 3... X-axis display area control circuit 5... Sampling pulse generation circuit 6... Latch pulse generation circuit 7... Frequency division circuit 8 ~10...S/P conversion circuit 11
~13...RAM 14-16...P/S conversion circuit 17-19...AND circuit 20...OR circuit 21
...-Rite address counter 22...Ring counter 23...1/8 counter 24...Read address counter 25...1/4 counter 26...Shift clock generator 27... Latch clock generator 28...Frame signal generation circuit 29...AC conversion signal circuit 30...Y electrode drive circuit 31...S/P conversion circuit 32...X electrode drive circuit 33...Selection Circuit 34...Color liquid crystal panel 35...AND circuit

Claims (1)

[Claims] The X-axis electrodes and Y-axis electrodes are arranged in a matrix, and the X-axis electrodes are colored with red, blue, and green filters to drive the color liquid crystal panel, the X-electrode drive circuit that drives the X-axis electrodes, and the Y-axis electrode. Y-axis electrode drive circuit, each S/P conversion circuit that converts red, blue, and green serial display data into parallel, each storage circuit that stores the parallel-converted display data, and the stored parallel display data Each P/S conversion circuit for converting into serial, a selection gate circuit for selectively outputting the output signal of each P/S conversion circuit, and a selection gate circuit for converting the serial signal of the selection gate circuit into a parallel signal. In a color liquid crystal display device configured with an S/P conversion circuit, three independent serial display data of red, blue, and green are converted into one serial mixed red, blue, and green data by the selection gate circuit. After converting to display data,
The color liquid crystal display device further includes an interface circuit that converts the signal into a parallel signal and inputs the signal to the X electrode drive circuit.