CN1009134B - Interface for thin display - Google Patents
Interface for thin displayInfo
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- CN1009134B CN1009134B CN87101705A CN87101705A CN1009134B CN 1009134 B CN1009134 B CN 1009134B CN 87101705 A CN87101705 A CN 87101705A CN 87101705 A CN87101705 A CN 87101705A CN 1009134 B CN1009134 B CN 1009134B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
- G09G5/008—Clock recovery
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0606—Manual adjustment
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0666—Adjustment of display parameters for control of colour parameters, e.g. colour temperature
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3681—Details of drivers for scan electrodes suitable for passive matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
- G09G5/022—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using memory planes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Nonlinear Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
An interface for a thin colour display panel 111 receives a clock signal CK, horizontal and vertical synchronisation signals Hsyc and Vsyc, and serial colour display data DR, DG and DB. An X-axis display area control circuit 101 receives Hsyc signals which are clocked by CK signals to a pulse generator 103. A Y-axis display area control circuit 102 receives both Hsyc and Vsyc signals and provides an output to generator 103. The generator 103 is clocked by CK signals to give an output to an RAM control circuit 104 when outputs from circuits 101 and 102 are present simultaneously. The RAM control circuit 104 is clocked by CK signals and by timing signals from a generator 109 to introduce the colour display data into RAM memories 105, 106 and 107. Colour display data stored in the RAM memories is extracted by a colour data treating circuit 108 to generate desired mixed colour data for an X-axis electrode driver 112. The timing signal generator 109 clocked by CK signals generates timing signals necessary for operating the driver 112 and a Y-axis electrode driver 110 for the thin colour display panel 111.
Description
The present invention relates to the interface circuit used such as thin displays such as LCD, electroluminescent display, plasma display or light-emitting diodes optical display units.In more detail, the present invention relates to a kind of color monitor with a kind of like this interface circuit, the interface signal of the cathode-ray tube display that this interface circuit utilization particularly is used widely in personal computer can be used as small-sized display device and uses.
The present invention relates to a kind of like this interface circuit, this interface circuit utilizes the interface signal of cathode-ray tube display, independently storing independent colored video data in some random access memory, and convert video data the mixed display data of red, green, blue in readout time, with the driving circuit of the driving circuit same structure of each device of prior art in can play colored display interface.
Therefore the characteristics that liquid crystal indicator has is thin, operating voltage is low and power consumption is little adopt large-scale dot matrix type panel to utilize them to show the terminal device of personal computer, word processor etc. in actual applications recently.Developed at present the various large scale integrated circuits that can be directly connected to the cathode ray interface tube that resembles hand-held computer and so on, various automatic office equipment manufacturing firm has produced the interface circuit of liquid crystal indicator special use with various gate arrays.Therefore current demand to liquid crystal indicator increases rapidly.Though these liquid crystal indicators have reached 640 * 200 display capabilities that can replace cathode-ray tube (CRT), they are normally monochromatic to show, during in order to display graphics, and deficiency aspect the display message amount.In addition, they only utilize one or two red, green, blue display to the display panel of simple matrix, and can only carry out on/off and show, thereby also not too attractive.
Therefore the purpose of this invention is to provide a kind of interface that supplies thin display to use through improvement.Another object of the present invention provides a kind of colour that can carry out and shows, utilizes the interface signal of color cathode ray tube to can be applicable to the interface circuit of panel display apparatus.
Fig. 1 is the block scheme of one embodiment of the invention.
Fig. 2 is the block scheme of another embodiment of the present invention.
Fig. 3 is the planimetric map of color liquid crystal (LC) panel electrode structure.
Fig. 4 is the time layout of video data.
Fig. 5 is the time layout that is added to the interface signal of driver.
Fig. 6 is the block scheme of embodiment that comprises a part of some deserializers, some select gates and a ring counter.
Fig. 7,8 and 9 is respectively the block scheme of other embodiment of the present invention.
Figure 10 is the block scheme of 924 1 embodiment of control circuit.
Figure 11 is the time layout of control circuit.
Figure 12 is the block scheme of another embodiment of the present invention.
Figure 13 is the time layout of circuit shown in Figure 12.
Figure 14 is the block scheme of X-axis driving circuit.
Figure 15 is drive waveforms figure.
Introduce one embodiment of the present of invention below.
Fig. 1 is the total block diagram of colour liquid crystal display device of the present invention.Among the figure, Hsyc represents horizontal-drive signal; Vsyc represents vertical synchronizing signal; DR, DG and DB are respectively the red, green, blue display data signal.CK represents clock signal.
The control circuit of viewing area on Y direction is counted and determined to Y-axis viewing area control circuit (Y-axis original position regulating circuit) the 102nd to horizontal-drive signal Hsyc, X-axis viewing area control circuit (X-axis original position regulating circuit) the 101st, to clock signal C K count and definite X-direction on the control circuit of viewing area.
Pulse producer 103 is that (after blanking interval) writes the circuit that the required clock signal of video data is used for producing when above-mentioned X-axis and Y-axis original position regulating circuit 101 and 102 boths are worked.The RAM(random access memory) control circuit 104 is to write or read the circuit that all memory RAM 105,106 and 107 needed address signals, write signal and read signal are used for producing.These memory RAM 105,106 and 107 itself are again the circuit that storage color video data DR, DG and DB use.Colo(u)r-mixture data processor 108 is that the sense data of the described memory RAM order by red, green, blue is rearranged so that they are transformed into the circuit that colo(u)r-mixture data is used.Timing generator 109 is the circuit that produce the timing signal that drives X-axis driving circuit 112 required usefulness.Introduce principle of work below.
When the output terminal of X-axis original position regulating circuit 101 and Y-axis original position regulating circuit 102 all was in " H " level, promptly when having passed through level and vertical synchronization blanking cycle, pulse producer 103 was with clock signal φ
1Be input in the RAM control signal, and in memory RAM 105,106 and 107, be that a unit writes clock video data DR, DG and DB with eight.The video data that order is write has readability in the cycle beyond write cycle, and they are input in the colo(u)r-mixture data processor 108.This colo(u)r-mixture data processor 108 becomes the colo(u)r-mixture data of a unit with the red, green, blue data conversion, and they are input into X-axis driving circuit 112 to drive each X electrode of color panel 111.Timing generator 109 not only produces the timing signal that drives above-mentioned X-axis driving circuit 112 and Y-axis driving circuit 110 required usefulness, and produces the reading timing signal that reads storer 105,106 and 107 usefulness.X-axis driving circuit 112 can drive each X electrode of color panel 111 according to the demonstration output data of colo(u)r-mixture data processor 108, and Y-axis driving circuit 110 can drive the Y electrode of color panel 111 with displayed image or character simultaneously.
Fig. 2 is one embodiment of the present of invention.
The effect of sampling pulse generation circuit 205 is the frequencies of dividing the clock signal C K in viewing area cycle, and data are taken a sample and received data.Serial-parallel convertor 208,209 and 210 is the change-over circuits that respectively red, green, blue serial video data converted to parallel data.RAM211,212 and 213 is respectively the memory circuitry that storage red, green, blue parallel data is used, and 214,215 and 216 of deserializers convert memory circuitry RAM211,212 and 213 parallel data to serial data respectively."AND" circuit 217,218 and 219 and OR circuit 220 be that the select gate of selecting and in turn the output of deserializer 214,215 and 216 being taken out and produce with the red, green, blue mixed form respectively serial data is respectively arranged.
Serial-parallel convertor 231 becomes parallel data with serial mixed display data-switching.Write address counter 221 is counted memory circuitry RAM211,212, each address of 213 after vertical synchronizing signal Vsyc resets.Circuit 206 takes place lock pulse takes place when counting down to eight sampling pulses of sampling pulse generation circuit in lock pulse (latch pulse), and each register of locking serial-parallel convertor 208,209 and 210.In addition, the lock pulse of lock pulse generation circuit 206 system is input in the write address counter.
Read address counter 224 is counter circuits that readout memory circuit RAM211,212,213 each address are used.Selecting circuit 233 is that 207 frequencies with clock signal C K of frequency dividing circuit are divided into lower frequency with the circuit of the mode reference address line that writes or read memory circuitry RAM211,212, each address of 213.Ring counter 222 is made up of a three-shift ring counter, and it sends strobe pulse so that obtain the mixed serial video data by the red, green, blue video data that takes out deserializer 214,215,216 successively from select gate 217,218,219,220.1/8 counter 223 sends a locking signal in order to the video data of the counter input signal of locking read address counter 224 and the video data that memory circuitry RAM211,212,213 is added to deserializer 214,215,216, also produces a pulse signal when the eight pulses input that ring counter 222 each carry signal are arranged at every turn.
1/4 counter 225 provides a locking signal for serial-parallel convertor 231 when four output pulse inputs of frequency dividing circuit 207 are arranged, 226 in shift clock generator sends the shift clock signal for parallel four bit shift register that are contained in the X electrode drive circuit 232.The locking signal that the data that locking X-axis electrode drive circuit 232 and Y-axis electrode drive circuit 230 take place locked clock generator 227 are used, 228 in frame signal generation circuit sends frame signal (data of Y electrode) for Y electrode drive circuit 230.
Interchange-switching signal circuit 229 changes the polarity of X and Y electrode drive circuit 232 and 230 drive signals, so that with AC driving color liquid crystal panel 234.Color liquid crystal panel 234 adds the red, green, blue color filter toward each transparency electrode of X-axis electrode and makes.X electrode drive circuit 232 drives each X-axis electrode of liquid crystal panel 234, and the Y electrode drive circuit drives the Y-axis electrode simultaneously.
Introduce principle of work of the present invention below.
Y-axis viewing area control circuit 201 receives Hsyc and imports as it, and toward the "AND" circuit signal of 202 output Y-axis effective viewing area times.
Clock signal is input to X-axis district control circuit 203 as the output of "AND" circuit 202, and this control circuit 203 outputs to "AND" circuit 204 with the signal of X-axis active zone viewing area time.Here, because Y-axis viewing area control circuit 201 and X-axis viewing area control circuit 203 all be made up of some adjustable counters, thereby effective indication range of directions X and Y direction color liquid crystal panel can be set arbitrarily.Secondly, the output of "AND" circuit 204 is the clock signals in effective viewing area, thereby video data DR, DG and DB are effective.
Sampling pulse generation circuit 205 is divided into 1/4 with the generation sampling pulse with the output frequency of "AND" circuit 204, and sends the shift clock of data sampling pulse as serial-parallel convertor 208,209,210.Lock pulse generation circuit 206 is divided into 1/8 with the sampling pulse frequency of sampling pulse generation circuit 205, and produces the locking signal that is added to serial-parallel convertor 208,209,210.
In addition, this lock pulse system is input in write control signal, selection circuit 233 and the memory circuitry 211,212,213 of write address counter 221.Therefore eight bit parallel samples of signal with serial-parallel convertor become presumptive address, are stored in simultaneously in the memory circuitry 211,212,213.When these signals of storage, the lock pulse of lock pulse generation circuit 206 increases the counting of write address counter 221, and video data is stored in each presumptive address successively.
Introduce readout below again.When lock pulse generation circuit 206 does not have lock pulse output, select circuit 233 to select the counting output of read address counter 224, memory circuitry RAM211,212,213 is in and reads under the working method.So these memory circuitries RAM211,212,213 video data are subjected to the visit of read address counter 224 outputs and are imported in the deserializer 214,215,216.The output of 1/8 divider 223 is locked in video data in the deserializer 214,215,216.
Fractional frequency signal C
1Be to use the frequency of frequency dividing circuit 207 division points clock signal C K to produce, at this moment it is imported in the ring counter 222.
As previously mentioned, ring counter 222 is made up of the three-shift ring counter, and this output is to use as the shift clock signal of each deserializer 214,215,216.Therefore the serial signal of deserializer 214,215,216 is imported in each "AND" circuit 217,218,219 of select gate successively regularly with the signal of each three-shift ring counter.Just because of this, thus the output of the OR circuit 220 of each select gate by red, green, blue, red ..., blue video data mixes the serial data of forming.The red, green, blue serial data of having mixed is input in the serial-parallel convertor 231.This output is imported into serial-parallel convertor 231 as locking signal after 1/4 counter 225 is divided into 1/4 with frequency, thereby this change-over circuit 231 is converted video data such as (red, green, blue, red), (green, blue, red, green), (blue, red, green, blue), (red, green, blue, red) to ... or the like parallel data.
Serial-parallel convertor 231 outputs four bit parallel mixed colors video datas 0
1-0
4, as shown in Figure 4.
Shift clock generator 226 sends shift clock by the output signal that postpones 1/4 counter 225, so that provide shift clock for the video data of serial-parallel convertor 231 for the four bit parallel type shift registers be connected to X electrode drive circuit 232.
Locked clock generator 227 sends locking signal, so that the video data of locking X electrode drive circuit 232 4 bit parallel shift registers.When the video data of X-axis electrode was displaced to its terminal, locked clock generator 227 sent locked clock, thereby made the video data locking simultaneously, and each X electrode is driven at same timing.In addition, the displacement of the video data of each Y-axis electrode produces and drives the shift clock signal that next Y-axis electrode is used.Frame signal generation circuit 228 sends the frame signal of the video data that becomes Y electrode drive circuit 230, and produces the video data of selecting the first Y-axis electrode to use by the frequency of dividing locked clock generator 227.In addition, frame signal generation circuit 228 is scavenged into zero with the output of read address counter 224, and sends the reset pulse that becomes zero-address to use memory circuitry RAM211,212,213 address mapping.
Fig. 3 is the electrode structural chart of the used color liquid crystal panel of the present invention.Among Fig. 3, Y
1, Y
2... and Y
nThe electrode of Y in groups of expression color liquid crystal panel.Letter r
1, G
1And B
1, R
2, G
2And B
2... and R
n, G
nAnd B
nRepresent to be added with by the order of red, green and blue look on it electrode of X in groups of color filter, the intersection point between above-mentioned each X electrode and each the Y electrode forms colored display dot.
Fig. 4 be output deserializer 214,215,216 four bit parallel red, green, blue data in the colour mixture video data time time layout.Among Fig. 2, the output R of ring counter 222
CL, G
CL, and B
CLBe output C from divider 207
1Obtain, video data is then extracted by select gate with the form of timesharing.So output D of OR circuit 220
1It is red to export R(in turn), G(is green) and B(indigo plant) video data of look, as shown in time layout.Above-mentioned video data D
1If shift clock C by serial-parallel convertor 231
1Be shifted 4 (to D
SC), then by the output signal C of 1/4 counter 225
2Locking.As a result, the output of four bit parallels of serial-parallel convertor 231 0
1To 0
4Exportable colour mixture video data, this promptly can find out from Fig. 4, thereby make output 0
1Press the order output of R, G and B, output O
2Press the order output of G, B and R, output 0
3Press the order output of B, R and G, output 0
4Press the order output of R, G and B.
Fig. 5 is the time layout that is added to each interface signal of liquid crystal display drive circuit.Among Fig. 5, alphabetical O
1To 0
4The colour mixture video data of expression serial-parallel convertor 231, alphabetical S
CLExpression is contained in the shift clock of four bit parallel shift registers in the X-axis driving circuit 232, alphabetical L
CLExpression is contained in the locking signal of the lock-in circuit in the X-axis driving circuit 232 and is contained in the shift clock of the shift register in the Y-axis driving circuit 230.Letter FRM represents to start the scanning starting data of Y-axis driving circuit 230 scanning usefulness, and these data are that the frame signal generator 228 by Fig. 2 produces.
Symbol M represents by dividing the signal that above-mentioned FRM signal draws equally, is the output signal of interchange-switching signal generation circuit shown in Figure 2.
Fig. 6 is the structural drawing of deserializer 614,615 and 616, select gate and the ring counter 622 of the specific embodiment of the invention.
Among Fig. 6, switch 645 is the switches that convert binary value or ternary values in order to the count value with ring counter 622 to.Resistor 646 is pull-down-resistors.Memory RAM 611,612 and 613 parallel data are by serializer 614,615 and 616 lockings.The output of three-shift that ring counter counts out produces the shift clock of deserializers 614,615 and 616 usefulness through each "AND" circuit 640,641 and 642, so that the data of deserializer 614,615 and 616 serial successively are sent to OR circuit 620 by each "AND" circuit 617,618 and 619.The output of above-mentioned ring counter is input to 1/9 counter 623, so that at each nine output CL to ternary counter
1, pulse of output during counting.So under the situation that is not having output, each "AND" circuit 640,641,642 is opened so that shift clock is sent in deserializer 614,615 and 616, but the 9th time when counting closure.Simultaneously, the output CL of 1/9 counter
2Be input in memory RAM 611,612 and 613, thereby these storeies 611,612 and 613 are outputed in serializer 614,615 and 616 simultaneously.Delay circuit 644 makes the output CL of 1/9 counter
2Postpone to be added to output CL
3On.This exports CL
3Impel the parallel data of above-mentioned memory RAM 611,612 and 613 that new data is locked in the serializer.Therefore memory RAM 611,612 and 613 parallel data all are eight bit data, and new data can be transmitted when finishing shifting process in each eight shift clock of being launched input, last three-shift ring counter CL
1Cycle length.Though what up to the present introduced is example about the three-shift ring counter, when connecting switch 645, as the course of action of the ring counter 622 of binary counter with aforesaid the same.
Among Fig. 2, the output of the OR circuit 220 of select gate is the serial data that the video data by the red, green, blue video data mixes.These serial datas are input in the staticizer 231.Because this is exported its frequency and is divided into after 1/4th as the locking of staticizer 231 is imported through 1/4 counter, therefore this converter 231 is transformed into parallel data with video data, thus become (red, green, blue, red), (green, blue, red, green), (indigo plant, red, green, blue), (red, green, blue, red) ... or the like.
Fig. 7 is an alternative embodiment of the invention.Among Fig. 7, ring counter 722 is in order to produce the senary ring counter of tandem signal with the timesharing form.Lock-in circuit 714,715 and 716 be store temporarily RAM711,712 and 713 read the circuit that video data is used.When on-off circuit 740 to 745 is work in order to from the video data of lowest order input lock-in circuit 714,715 and 716 with as colour mixture video data input red, green, blue data, so that they are transferred with the timesharing form, thereby make them have the function that converts the colour mixture video data with the serializer 214,215 and 216 shown in Fig. 2, select gate 217,218,219 and 220, staticizer and ring counter 222 to.
In Fig. 7, AND gate 731 is to be used to show that for carrying out individually the purposes of essential horizontal-drive signal is provided with.Have only when Vsyc be that Hsyc is input to Y-axis viewing area control circuit 701 when being in " H " state.
Delay circuit 735 is for the output pulse that postpones 1/8 counter 723 and provides the purpose that the pulse that postponed delivers to lock-in circuit 714,715 and 716 as locking signal and be provided with.The pulse signal of 1/8 counter 723 is to be counted by read address counter 724.RAM711,712 and 713 video data are read out the output addressing of address counter 724.The video data of addressing is imported into lock-in circuit 714,715 and 716.When data when displaced condition enters steady state (SS), video data that must the locking addressing.The 735 delay lock time limits of delay circuit, thus when video data be during in steady state (SS), locking signal just is sent to lock-in circuit.
Phase inverter 737 is to stop the purpose of clock signal C K output to be provided with by AND gate 736 when importing write address counter 721 into when lock pulse.When the lock pulse signal is transfused to into write address counter 721, promptly when signal be that the output of phase inverter 737 becomes " L " state when being in " H " state so that AND gate 736 does not allow clock signal C K to pass through.
Therefore, just might control one of them time limit of visit write address counter and read address counter.
Fig. 8 is the circuit diagram of another embodiment.Among Fig. 8, thereby another X-axis original position regulating circuit 801 is in order to receive horizontal-drive signal Hsyc to provide predetermined delay time with colored video data circuit regularly.Thereby Y-axis original position regulating circuit 802 is in order to receive vertical synchronizing signal Vsyc so that provide predetermined delay time with colored video data circuit regularly from signal Vsyc.Adjustable some counter 803 is so that calculate the circuit of the number of level point clock in order to the number that calculates clock signal C K.Flip-flop circuit 815 is the circuit in order to the output of frequency of dividing clock CK or "AND" circuit 807.PLL(phase-locked loop of the common formation of phase comparator 816, integrator 817, voltage-controlled oscillator 818,1/3 counter 819 and flip-flop circuit) circuit is three times a signal of above-mentioned "AND" circuit 807 clock signal frequencies in order to produce frequency.Ring counter 821 is three-shift ring counter circuit, in order to export the control signal of colour annalyzer from the oscillator signal of above-mentioned PLL circuit.Memory circuitry 825 to 830 is the storeies in order to storage color video data DR, DG and DB.The circuit that color data separation vessel 841 is made up of "AND" circuit 831 to 836 and OR circuit 837 and 838, during work in order to separate the upper/lower electrode color data.Staticizer 839 and 840 is to convert parallel data to so that the color separation data are outputed to the circuit of LCD in order to the serial data with above-mentioned OR circuit 837 and 838.Present embodiment promptly is made up of the foregoing circuit element.
Introduce principle of work below.
When horizontal-drive signal Hsyc is input to the one shot multivibrator 804 of X-axis original position regulator 801, singly to move the output of attitude multivibrator 804 and reduce to level "0", its time delay, CR was determined by capacitor and variohm.Because flip-flop circuit 808 is set up by signal Hsyc, the output of NOR circuit 805 rises to level"1".Y-axis original position regulating circuit 802 also has similar structure, and its a period of time of delaying time after receiving vertical synchronizing signal Vsyc is input to "AND" circuit 807 with numerical value " 1 " then.
As a result, the output of "AND" circuit 807 in X-axis and Y-axis original position regulating circuit 801 and 802 overlaps back clock signal CK with level"1".If adjustable point counter 803 is set up 640, then the 640th clock signal C K sends carry signal CL in addition
1This carry signal CL
1" 1 " is set up in the output of flip-flop circuit 808, make the output of "AND" circuit 807 interrupt clock signal CK.
The clock signal C K of above-mentioned "AND" circuit 807 is input to flip-flop circuit 815, and making its frequency be divided into duty ratio is 1: 1 square-wave signal, and is input in the phase comparator 816.This phase comparator 816 compares the phase place of flip-flop circuit 815 and 820, makes its output carry out integration by integrator 817.Voltage behind the integration outputs to voltage-controlled oscillator 818, thereby produces and the proportional oscillator signal of integral voltage.1/3 counter 819 is divided into 1/3 with the frequency of the oscillator signal of voltage-controlled oscillator 818, it is 1: 1 square-wave signal that signal after so dividing further is divided into duty ratio again, and be input in the phase comparator 816, in this phase comparator, compare with the output of flip-flop circuit 815 once more.In view of the course of work of above-mentioned PLL circuit is promptly introduced as top, thereby signal with the frequency resonance that is three times in clock signal C K frequency of voltage-controlled oscillator 818 outputs is given ring counter 821.
On the other hand, red, green, blue vision signal DR, DG and DB system is stored in the storer 825 to 830.These storeies 825 to 830 are made of some shift registers, and the shift clock signal then utilizes the output of above-mentioned flip-flop circuit 815, makes data to the displacement respectively in this all storer of each clock.More particularly, video data DR, DG and DB displacement also are stored in when the odd number clock in each storer 825,827 and 829, are stored in when the even number clock in each storer 826,828 and 830.The output data that storer 825,827 and 829 was shifted is input in the "AND" circuit 831,833 and 835 of color data separation vessel 841.In view of other inputs of "AND" circuit 831,833 and 835 is each output signal of ring counter 821, so the data of storer 825,827 and 829 are input in staticizer 839,840 and 839 with the form of timesharing respectively.Secondly, storer 826,828 and 830 data (these data systems are stored in the clock signal of even number order) equally also are input in deserializer 839 and 840 with time-sharing format.More particularly, storer 826,828 and 830 data are input to respectively in staticizer 840,839 and 840.Staticizer 839 and each shift clock signal of 840 are the output of "AND" circuit 844 and 845.Staticizer 839 and 840 is by locking signal CL
3Locking, locking signal CL
3Then be the output CL of delay circuit 824 from voltage-controlled oscillator 818
2And the carry signal of 1/4 counter 823 postpones.As a result, staticizer 839 and 840 generals colored video data afterwards convert the colored video data of upper electrode and lower electrode respectively to, to produce output UD
0To UD
3And LD
0To LD
3Specifically, staticizer 839 is output as ((terminal UD
0) DR, (UD
1) DB, (UD
2) DG, (UD
3) DR, (UD
0) DB, (UD
1) DG ... or the like).On the other hand, staticizer 840 is output as ((terminal LD
0) DG, (LD
1) DR, (LD
2) DB, (LD
3) DG, (LD
0) DR, (LD
1) DB ... or the like).Therefore each output is regularly to produce for each upper and lower electrode simultaneously.The order that produces for upper electrode be red, blue, green, red ... or the like, the order that produces for lower electrode be green, red, blue, green ... or the like.The above-mentioned data UD that outputs to colour liquid crystal display device
0To UD
3And LD
0To LD
3Be it to be postponed in above-mentioned locking signal CL by delay circuit 842
3Shift clock SC export as the data shift clock signal of liquid crystal drive circuit.
The carry signal CL of above-mentioned adjustable point counter 803
1Make its delay by delay circuit 810,810 of delay circuits are made up of the D flip-flop circuit, in order to locking signal LD is outputed to the liquid crystal drive circuit as the data interlock signal of a line.
Input vertical synchronizing signal Vsyc or when starting the data that the driver of first sweep trace uses, that is to be input on the NOR circuit 813, the output set that makes NOR circuit 813 is in " 1 ".In addition, the locking signal LD of above-mentioned liquid crystal drive circuit is postponed by delay circuit 811 that the D flip-flop circuit is formed, postpone to last time semiperiod of clock signal, locking signal LD is input to NOR circuit 812 so that the output of NOR circuit 812 resets in " 0 " simultaneously.
The output signal FRM of this NOR circuit 812 outputs to the liquid crystal drive circuit as the data (or frame signal) of starting liquid crystal driver circuit common edge scanning usefulness.On the other hand, the frequency of the output FRM of above-mentioned NOR circuit 812 is divided by flip-flop circuit 814 so that output AC drive control signal M, this signal M then in order to reversing polarity so that alternate liquid crystal drive voltage at every turn.
Fig. 9 is another embodiment of the present invention.
Among Fig. 9, lock pulse generator 903 is to produce the circuit that expendable locked pulse is used for each pulse from "AND" circuit 933 outputs.Staticizer 904,905 and 906 is to convert the red, green, blue video data to circuit that parallel signal is used.Memory circuitry 907,908 and 909 is circuit that the video data of the above-mentioned staticizer 904,905 of storage and 906 is used.Serializer 910,911 and 912 is that the parallel data of reading with storer 907,908 and 909 converts the circuit that serial data is used to."AND" circuit 934,935 and 936 and OR circuit 937 be in order to extract the select gate of serial data in order.Staticizer 922 is in order to convert serial data to parallel data so that parallel data is sent to the circuit of LCD.On-off circuit 913,914 and 915 is to disconnect and connect circuit with their switchings in order to the bus line with the parallel data of above-mentioned staticizer 904,905 and 906.Memory circuitry 916,917 and 918 is another Lower Half when above-mentioned memory circuitry 907,908 and 909 is the first half of demultiplexing matrix.Serializer 919,920 and 921 is in order to will convert the circuit of serial data from the parallel data that each memory circuitry is read in the same way."AND" circuit 938,939 and 940 and OR circuit 941 be the Lower Half select gate.Staticizer 923 is in order to parallel data is transferred to the circuit of the driver circuit of Lower Half liquid crystal panel.Ring counter 929 is the circuit that selected pulse sent to successively serializer (910,919), (911,920) and (912,921) usefulness.Thereby 1/9 counter 928 is to become 1/9 to send the circuit of using from the read pulse of storer 907,908,909,916,917 and 918 each data to produce carry signal frequency partition.Reading address timer 927 is circuit of respectively reading address number in order to calculate.Write address counter 925 is to calculate to write the circuit that address number is used.Selector switch 926 is in order to select to write or read the circuit of address.Control circuit 924 is circuit that write and read of control store 907,908,909,916,917 and 918.Liquid crystal panel timing generator 931 is to produce toward the liquid crystal drive circuit to send the circuit of data with the timing signal that drives liquid crystal and need use.
Present embodiment promptly is made of above all circuit of enumerating.
Secondly, introduce the principle of work of Fig. 9 below.The output that makes clock signal C K be easy to received Y-axis original position regulating circuit 901, X-axis original position regulating circuit 902 and "AND" circuit 933 be one in order to transmit the clock signal L of video data in effective viewing area.Therefore lock pulse generator 903 is calculating the number of video transmission clock L.Vision signal DR, DG and DB are input to respectively in the shift register of staticizer 904,905 and 906 in addition, thereby above-mentioned video transmission clock is imported as shift clock.When eight pulses of the above-mentioned video transmission clock of input, have lock pulse P to produce and be stored in storer 907,908 and 909 or storer 916,917 and 918 in.These lock pulses P is input to write address counter 925 increases the address, is input to selector switch 926 simultaneously so that passage is transferred in the mode of selecting to write the address, thereby by exporting write signal W from above-mentioned control circuit 924
1Or W
2(this point is understandable) storage first half storer 907,908 and 909 or 916,917 and 918.
Introduce readout below.Clock signal C K is input in the ring counter 929 after frequency divider 930 is divided in its frequency.The structure of three-shift ring counter becomes from select gate the output of ring counter 929 and extracts the strobe pulse that red, green and blue data DR, DG and DB use successively with time-sharing format.The frequency of output M is divided into after 1/3 through ring counter 929, further is divided into 1/9 by 1/9 counter 928.Output carry signal when this 1/9 counter 928 is nine times at the counting of each above-mentioned ring counter 929.This carry signal increases the address of read address counter 927, is imported into simultaneously in the control circuit 926 with output read signal R.As a result, storer 907,908 and 909 and the data of storer 916,917 and 918 when response readings signal R, be transferred to serializer 910,911 and 912 and serializer 919,920 and 921.Because serializer 910,911,912,919,920 and 921 is to be made of lock-in circuit and eight bit shift register, thereby when the shift clock that the three-shift ring counter of the above-mentioned ring counter 929 of response is exported, extract each position from each select gate 934,935,936 and 937 and 938,939,940 and 941.As a result, OR circuit 937 and 941 output are as the mixed colors data serial output of red, green, blue, and this point is understandable.
These serial output data are input to staticizer 922 and 923 respectively, so that be reduced to the transfer rate of liquid crystal display driver circuit, thereby convert them to parallel signal, and as first half video data UD
0To UD
3With Lower Half video data LD
0To LD
3Export.
Timing signal such as the data transmission clock that is added to liquid crystal panel drive circuit, frame signal or data interlock signal all is the output of frequency divider 930 by liquid crystal panel timing generator 931.Figure 10 is the circuit diagram of an embodiment of control circuit 924 of the present invention.
Y-axis original position regulating circuit 901 is worked in the following manner.When the input of response vertical synchronizing signal Vsycn, the output Q of one shot multivibrator 1050
1Descend by predetermined delay time.The output of result's NOR circuit 1051 after time-delay rises to " 1 ", thereby makes "AND" circuit 1053 output horizontal-drive signal Hsycn.
1054 pairs of these horizontal-drive signals of adjustable counter Hsycn counts.If the number of scanning lines of cathode-ray tube (CRT) interface signal is 400, then count value is transferred to 200.Therefore when the emission number of horizontal-drive signal be 200 or when being less than 200, the output Q of flip-flop circuit 1057
2Be in level"1", thereby make NAND circuit 1058 toward above-mentioned storer 907,908 and 909 output write signal W
1With storage first half video data.If the emission number of horizontal-drive signal Hsycn is 201 or greater than 201, then the output Q of flip-flop circuit 1057
3Get level"1", simultaneously the Lower Half video data is stored, thereby make write signal W
2Can output in storer 916,917 and 918.The output K of adjustable counter 1054
1When counting 200 times, write address counter 925 is resetted at every turn.Therefore when reading storer 907,908,909,916,917 and 918, can read the video data of same address.Introduce the readout of video data below again.The output K of 1/9 counter 928
2Output carry signal when each three-shift ring counter 929 sends the 9th output M.This exports K
2Present by two-stage D flip-flop 1062 and 1061, make NOR circuit 1060 output output valve Q and Q.Control clock CK makes NOR circuit 1060 output R can be used as read signal to carry out work and need not in timing and above-mentioned write signal W
1Or W
2Identical.Figure 11 is the time layout of above-mentioned control circuit.
Figure 12 is the synoptic diagram that can be used as the video interface circuit of another embodiment that can carry out the LCD that the classification color video shows.Among Figure 12, Hsyc represents horizontal-drive signal, and Vsyc represents vertical synchronizing signal, RD, and GD and BD are respectively the signal of red, green and blue Visual Display Data.CK represents clock signal.
Y-axis viewing area control circuit 1202 is number control circuits to determine that the Y direction viewing area is used of calculated level synchronizing signal Hsyc.X-axis viewing area control circuit 1204 is control circuits that the number of calculating clock signal C K is used with the viewing area of determining X-direction.Analog-to-digital converter circuit 1206,1207 and 1208 is the converters that convert digital value in order to the aanalogvoltage with the red, green, blue vision signal to.On-off circuit 1209 to 1211 is the circuit that the numeral output of above-mentioned analog-to-digital converter circuit 1206 to 1208 are forwarded to memory circuitry RAM1212 to 1214 usefulness.These RAM1212 to 1214 are storeies of the output usefulness of storage said switching circuit 1209 to 1211.Address counter 1224 is circuit of the address of RAM 1212 to 1214 being counted usefulness.On-off circuit 1215 to 1217 is in order to the data that RAM1212 to 1214 stored are input to the on-off circuit of lock-in circuit 1218 to 1220.D/A circuit 1221 to 1223 is that the digital value with above-mentioned lock-in circuit 1218 to 1220 converts the converter that aanalogvoltage is used to.X electrode driver circuit 1231 is the drivers in order to the X-axis electrode that drives color liquid crystal panel 1230.Keeping clock generator circuit 1226 is to produce the shift clock of shift register so that displacement is stored in the circuit that the scan-data in the Y electrode drive circuit 1229 is used.Frame signal generator circuit 1227 is to impel Y electrode drive circuit 1229 to produce the circuit that the starting sweep signal is used.AC signal generator circuit 1228 is in order to the polarization tandem signal so that drive the circuit of LCD with alternating current.Colour liquid crystal display device of the present invention promptly is made of the above-mentioned circuit of enumerating.
Have a talk the again below course of work of Figure 12.Figure 13 is the time layout of Figure 12 circuit diagram.Among Figure 12, Y-axis viewing area control circuit 1202 is in order to setting the circuit of effective display cycle in Y direction, is equipped with in this circuit vertical flyback period is counted the counter of usefulness and in order to the counter of calculated level synchronizing signal number during working in the viewing area.Horizontal-drive signal Hsyc is input to Y-axis viewing area control circuit 1202 as clock.The output T of Y-axis viewing area control circuit 1202
1(for example 400 * Hs) become output signal when " H " level during working in the Y direction viewing area.
So output φ of "AND" circuit 1203
1During working in the Y direction viewing area, horizontal signal Hsyc is input to X-axis viewing area control circuit 1204.This X-axis viewing area control circuit 1204 is made structurally identically with above-mentioned Y-axis display control circuit, and a counter and a counter of Dot Clock CK being counted usefulness of horizontal flyback time being counted usefulness after horizontal-drive signal Hsyc has imported are equipped with in the inside.These Dot Clocks CK imports as clock.The output T of X-axis viewing area control circuit 1204
2(for example, 640 * Tck) become the output signal at " H " level, as shown in figure 13 during working on the X-direction in the viewing area.Therefore "AND" circuit 1205 is in Dot Clock signal psi of effective viewing area output
2The aanalogvoltage of red, green, blue vision signal RD, GD and BD is input to on- off circuit 1209,1210 and 1211 after its crest voltage value converts digital signal to respectively by analog-to-digital converter circuit 1207 and 1208.
Analog-to-digital converter circuit 1206 to 1208 through the sampling after by Dot Clock φ
2Keep.
When each control signal R/ W of memory circuitry 1212 to 1214 is in " L " level, the video data of while write switch circuit 1209 to 1211.The address of memory circuitry RAM 1212 to 1214 is by address counter 1224 accesses, this address counter 1224 Dot Clock φ
2As its clock input, use vertical synchronizing signal Vsyc as its reset signal.
The readout of having a talk below.When the control signal R/ W of memory circuitry RAM 1212,1214 was in " H " level, the video data of being stored was read by RAM 1212 to 1214 and is locked by lock-in circuit 1218 to 1220 by on-off circuit 1215 to 1217.These lock-in circuit 1218 to 1220 outputs that locked are input to D/A circuit 1221 to 1223 respectively, so that convert digital value to aanalogvoltage, output in the X electrode drive circuit 1231 again.
Dot Clock φ
2Be subjected to the effect of delay circuit 1225 and postpone, output in the X electrode drive circuit 1231 as the shift clock that is contained in the shift register in the X electrode drive circuit 1231 then.In addition, Dot Clock φ
3Be input to and keep in the clock generator circuit 1226 so that produce the holding signal φ of data in the one-period time of horizontal-drive signal
4Thereby, keep aanalogvoltage.Above-mentioned holding signal φ
4System outputs in the Y electrode drive circuit 1229 as the shift clock that is contained in the shift register in the Y electrode drive circuit 1229.The frame signal φ of frame signal generator circuit 1227
5System is input in the Y electrode drive circuit 1229 as the scan-data of starting Y electrode drive circuit 1229.Frame signal generator circuit 1227 has such structure can be undertaken it by vertical synchronizing signal Vsyc synchronously.Specifically, frame signal generator circuit 1227 when response vertical synchronizing signal Vsyc with frame signal φ
5Bring up to " H " level, at holding signal φ
4Make it return to " L " level after descending for the first time.The output φ of AC signal generator circuit 1228 usefulness flip-flop circuits
6It is above-mentioned frame signal φ that the driving voltage of switching X electrode drive circuit 1231 and Y electrode drive circuit 1229 makes the polarity of liquid crystal drive voltage
4Each frame and reverse.
In addition, the shifted data generator circuit is to send for producing the pulse signal φ that data are used in order to the first order of the shift register in being contained in X-axis driving circuit 1231
7Circuit, its structure is similar to above-mentioned frame signal generator circuit 1227, thereby can make pulse signal φ when level of response synchronizing signal Hsyc
7Be promoted to " H " level, at Dot Clock φ
2Descend for the first time and afterwards it is returned to " L " level.Figure 14 is the synoptic diagram of the employed X electrode drive circuit of colour liquid crystal display device of the present invention.Among Figure 14, letter r A represents the output signal of above-mentioned red video signal D/A circuit 1221, the amplifier of numbering 1440 expression operate as normal, the amplifier of numbering 1441 expression paraphase work, the transmission gate circuit that numbering 1442 and 1443 expressions are made up of some analog switching circuits, numbering 1445 to 1447 expression shift-register circuits, numbering 1464 expression level shift circuits, 1451 to 1453 expression analog switching circuits, the holding circuit that numbering 1454 to 1456 expressions are made up of some capacitors, numbering 1458 to 1460 expression analog switching circuits, the holding circuit that numbering 1461 to 1463 expressions are made up of some capacitors.The X electrode drive circuit is made of above-named circuit.Letter r X
1To RX
3Expression is fed to the output signal with the drive circuit of the painted X-axis electrode of red color filter.The simulating signal of vision signal is amplified to produce normal amplifying signal R by operation amplifier circuit 1440 and 1441
PWith paraphase amplifying signal R
NThe signal R that these have amplified
PAnd R
NVision signal be input to transmission gate circuit 1442 and 1443, and by AC signal φ
6Each frame is transferred.Transmission gate circuit 1442 and 1443 output R
SBe input in the on-off circuit 1451 to 1453.Shift register 1445 to 1447 impels the gate signal of on-off circuit 1451 to 1453 to connect on-off circuit 1451 to 1453 at each Dot Clock, and uses shifted data φ
7As their data, use Dot Clock φ
3As their shift clock, keep the aanalogvoltage in the holding circuit 1454 to 1456 successively.In addition, when keeping clock φ
4When being input to the control utmost point of on-off circuit 1458 to 1460, these circuit 1458 to 1460 are connected simultaneously so that keep vision signal in holding circuit 1461 to 1463, thereby drive the X-axis electrode of the red color filter of liquid crystal panel together with those simulating signals.Because it is a kind of that the Y electrode drive circuit can be made that of prior art sequential lines scan-type, therefore can use liquid crystal driver circuit same as before according to the voltage method of average.Figure 15 is an example of drive waveforms of the present invention.Drive waveforms system is added to the RX of liquid crystal
1-Y
1Between, make with vision signal corresponding driving voltage in an alternating manner by X-axis driving voltage RX
1With Y-axis driving voltage Y
1Apply.
The front is talked about, and in the present embodiment, colour-video signal system converts digital signal to and is stored in and converts the simulating signal of using for video display in the memory circuitry then to.Therefore, can be easily selectively with the mode display video signal of active images or still image.Another outstanding effect is that large-scale LCD or other display that always can only be used in the business automation equipment such as personal computer or monochromatic character processor and on/off display can be extensively in order to replace the video display terminal equipment such as Computer Graphic Display or metope television equipment.
Claims (10)
1, the interface that a kind of slim display panel is used, it is characterized in that, this interface comprises timing device, memory storage, color data treating apparatus and timing signal generator, timing device is in order to carry out timing, so that in the memory storage of effective colored video data introducing corresponding to synchronizing signal, memory storage is in order to store described effective colored video data, the color data treating apparatus produces desirable colo(u)r-mixture data in order to the colored video data that utilizes described storage, and timing signal generator is in order to produce the timing signal of the required usefulness of driver of controlling slim color display panel.
2, interface according to claim 1, it is characterized in that, described timing device comprises X-axis viewing area control circuit, Y-axis viewing area control circuit and pulse producer, X-axis viewing area control circuit in order to control regularly, so that the effective colored video data of level is introduced in the memory storage, Y-axis viewing area control circuit in order to control regularly, so that vertical effective colored video data is introduced in the memory storage, pulse producer is in order to produce pulse when level and vertical color video data all work.
3, interface according to claim 1, it is characterized in that, described color data treating apparatus comprises locking device and switchgear, the colored video data that locking device is read from memory storage in order to interim storage, the colored video data that switchgear is stored in order to transfer with the timesharing form is so that convert colo(u)r-mixture data to.
4, interface according to claim 1, it is characterized in that, described memory storage comprises some in order to red, blue, green serial data converts the serial-parallel convertor of corresponding parallel data and some in order to storing the memory circuitry of described parallel video data to, and described color data treating apparatus comprises and somely converts the parallel video data of being stored to deserializer that serial data is used, some select gate and serial signals with described some select gates in order to the signal of exporting described some deserializers selectively respectively convert the serial-parallel convertor that parallel signal is used to.
5, interface according to claim 4 is characterized in that, three red, blue, green serial video data systems convert red, blue, green serial mixed display data to, convert a parallel signal then to.
6, interface according to claim 4 is characterized in that, described some select gates are controlled by a ring counter.
7, a kind of interface of using with the slim display panel of the first and second dot matrix electrode structures, it is characterized in that, described interface comprises timing device, first memory storage, second memory storage, first and second color data treating apparatus and the timing signal generators, timing device is in order to timing, so that effective colored video data is introduced in the memory storage by synchronizing signal, first memory storage is in order to store the effective colored video data of the first dot matrix electrode structure, second memory storage is in order to store the effective colored video data of the second dot matrix electrode structure, the first and second color data treating apparatus produce the first and second desirable colo(u)r-mixture datas in order to the colored video data that adopts described storage, and timing signal generator is in order to produce the timing signal of the required usefulness of the slim color display panel driver of control.
8, interface according to claim 7 is characterized in that, described interface circuit comprises that the control device that writes or read usefulness and a selection of control first and second memory storages write the address or read the selecting arrangement that the address is used.
9, according to claim 1 or 7 described interfaces, it is characterized in that, described memory storage comprises in order to the red, green, blue video display signal is converted to some analog-to-digital converter circuits of digital signal corresponding, in order to some memory circuitries of the video data of storing mould/number conversion respectively, and the some D/A circuit that convert simulating signal in order to each output signal with described memory circuitry to.
According to claim 1 or 7 described interfaces, it is characterized in that 10, described slim display panel adopts the electrooptic cell that is selected from liquid crystal, electroluminescence, plasma and light emitting diode.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP45880/86 | 1986-03-03 | ||
| JP61045880A JPS62203131A (en) | 1986-03-03 | 1986-03-03 | Color liquid crystal display device |
| JP61150922A JPS636597A (en) | 1986-06-27 | 1986-06-27 | Color liquid crystal display unit |
| JP150922/86 | 1986-06-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN87101705A CN87101705A (en) | 1987-09-09 |
| CN1009134B true CN1009134B (en) | 1990-08-08 |
Family
ID=26385974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN87101705A Expired CN1009134B (en) | 1986-03-03 | 1987-03-02 | Interface for thin display |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5153574A (en) |
| EP (1) | EP0236111A3 (en) |
| KR (1) | KR940008177B1 (en) |
| CN (1) | CN1009134B (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7212181B1 (en) * | 1989-03-20 | 2007-05-01 | Hitachi, Ltd. | Multi-tone display device |
| JPH03201788A (en) * | 1989-12-28 | 1991-09-03 | Nippon Philips Kk | Color display device |
| KR940004138B1 (en) * | 1990-04-06 | 1994-05-13 | Canon Kk | Display apparatus |
| US5668568A (en) * | 1992-11-13 | 1997-09-16 | Trans-Lux Corporation | Interface for LED matrix display with buffers with random access input and direct memory access output |
| JPH07219508A (en) * | 1993-12-07 | 1995-08-18 | Hitachi Ltd | Display controller |
| US5642129A (en) * | 1994-03-23 | 1997-06-24 | Kopin Corporation | Color sequential display panels |
| US5606348A (en) * | 1995-01-13 | 1997-02-25 | The United States Of America As Represented By The Secretary Of The Army | Programmable display interface device and method |
| US5635988A (en) * | 1995-08-24 | 1997-06-03 | Micron Display Technology, Inc. | Apparatus and method for maintaining synchronism between a picture signal and a matrix scanned array |
| US5610667A (en) * | 1995-08-24 | 1997-03-11 | Micron Display Technology, Inc. | Apparatus and method for maintaining synchronism between a picture signal and a matrix scanned array |
| US5854615A (en) * | 1996-10-03 | 1998-12-29 | Micron Display Technology, Inc. | Matrix addressable display with delay locked loop controller |
| JP3660126B2 (en) * | 1998-05-18 | 2005-06-15 | 株式会社ルネサステクノロジ | Data transfer circuit and liquid crystal display device |
| US7230600B1 (en) * | 2000-09-28 | 2007-06-12 | Intel Corporation | Repairable memory in display devices |
| KR100977217B1 (en) * | 2003-10-02 | 2010-08-23 | 엘지디스플레이 주식회사 | Apparatus and method driving liquid crystal display device |
| US7714851B2 (en) * | 2004-09-08 | 2010-05-11 | Intersil Americas Inc. | Single supply video line driver |
| JP2006094256A (en) * | 2004-09-27 | 2006-04-06 | Nec Electronics Corp | Parallel/serial conversion circuit and electronic apparatus |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54109722A (en) * | 1978-02-16 | 1979-08-28 | Sony Corp | Flat-type picture display device |
| US4342029A (en) * | 1979-01-31 | 1982-07-27 | Grumman Aerospace Corporation | Color graphics display terminal |
| JPS59138184A (en) * | 1983-01-28 | 1984-08-08 | Citizen Watch Co Ltd | Driving circuit of matrix color television panel |
| JPS59181880A (en) * | 1983-03-31 | 1984-10-16 | Toshiba Electric Equip Corp | Video display device |
| US4642628A (en) * | 1984-06-22 | 1987-02-10 | Citizen Watch Co., Ltd. | Color liquid crystal display apparatus with improved display color mixing |
| FI73325C (en) * | 1985-03-05 | 1987-09-10 | Elkoteade Ag | FOERFARANDE FOER ALSTRING AV INDIVIDUELLT REGLERBARA BILDELEMENT OCH PAO DESSA BASERAD FAERGDISPLAY. |
| CA1233282A (en) * | 1985-05-28 | 1988-02-23 | Brent W. Brown | Solid state color display system and light emitting diode pixels therefor |
-
1987
- 1987-03-02 CN CN87101705A patent/CN1009134B/en not_active Expired
- 1987-03-02 EP EP87301804A patent/EP0236111A3/en not_active Withdrawn
- 1987-03-03 KR KR1019870001870A patent/KR940008177B1/en not_active IP Right Cessation
-
1990
- 1990-01-08 US US07/463,932 patent/US5153574A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0236111A2 (en) | 1987-09-09 |
| EP0236111A3 (en) | 1989-07-19 |
| KR870009250A (en) | 1987-10-24 |
| US5153574A (en) | 1992-10-06 |
| CN87101705A (en) | 1987-09-09 |
| KR940008177B1 (en) | 1994-09-07 |
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