JPS61169893A - Display circuit for liquid crystal display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to a circuit for receiving data from a data source such as a computer and displaying the data on a display device.

[Background of the invention]

Information generated by a computer is usually stored on a cathode ray tube (CR).
T) Shown above is disgusting. Signals from the computer deflect an electron beam that writes information on the CRT screen. CRT screens are raster scanned to create images.

Raster scanning technology creates a series of parallel, horizontal beams that move from left to right across the screen from top to bottom.

As cabins became more common, computers became more portable and are now made to run on batteries. However, there are two drawbacks to CRT displays that have limited the portability of computers. First of all,
The size required by the OT display device may become large when used for administrative work, for example. The second is that CRTs cannot be operated with infertile batteries that would satisfy the computer's complete portability.

As one solution to these problems, liquid crystal display devices (
LCDs) are used. Compared to CRT display devices, liquid crystal display devices have thinner, lighter screens and consume less power, making them ideal portable display devices.

A problem with liquid crystal displays as computer display devices is that computer video output devices made for CRT displays cannot be applied to liquid crystal displays. The response time of a liquid crystal display is longer than that of a CRT display.
Therefore, the reproduction ratio (rate at which display data can be updated) is also CR.
This is different from that of the T display device.

The present invention solves the above problems and does so by using a circuit that allows the output from a computer for a CRT display to also be used for a liquid crystal display.

[Summary of the invention]

The present invention relates to a circuit that divides a video signal from a computer into four parts, each of which drives one quadrant of a liquid crystal display screen.

Raster scanning is performed separately in each quadrant. This circuit allows the liquid crystal display to be performed with low power and can also be operated with a battery. Independent input and output counters control the reception and transmission of information.

[Embodiments of the invention]

The driving circuit used for computer display is as follows. This circuit utilizes video signals from computers and is particularly useful for liquid crystal displays. In the following description, numerical specifications, such as clock cycles and memory sizes, are detailed in order to provide a thorough understanding of the invention. However, it will be apparent to those familiar with the technology that the present invention can be practiced without these detailed specifications.

In other instances, well-known circuits and structures have not been described in detail in order to avoid unnecessarily obscuring the present invention.

The present invention utilizes a liquid crystal display screen.

According to one embodiment, the screen has 192 lines, each line having 560 pixels. This structure allows it to display the same amount of information as a standard computer CRT display. The number of pixels also determines the clarity and sharpness of the displayed information.

Information prepared by a computer is in serial form. A continuous stream of data is provided to the display device. In order to adapt this information to a liquid crystal display, the information is multiplexed. However, in today's electronics,
The multiplexing is also about 100 pieces of information per line. Since the video source provides 192 lines of data, the driver circuit must first divide the data. This division is carried out according to the invention by electronically dividing the screen into two parts.

This would require only 96 to 1 multiplexing within the current circuit margins.

The invention then subdivides the screen into four quadrants. The set of information from the data source can then be split into four data lines, one for each quadrant. Each quadrant is then scanned individually with information from its own data line. □ Figure 1 shows an example of screen division. screen 1
0 is subdivided into an upper left section 11, an upper right section 12), a lower left section 13, and a lower right section 14. This subdivision is done electronically, not physically, and the impact of any one boundary between each division is minimized.When the screen is in use, too,
The lines dividing each quadrant are invisible. Each quadrant is fed by its own data line and is raster scanned in a manner similar to full screen. The first vixel of each scan, indicated by pixels 15, 16, 17, and 18, appears simultaneously or nearly simultaneously in each quadrant.

Next, FIG. 2 shows another method of dividing the screen.

In this embodiment, the screen 20 is divided into an upper half 21 and a lower half 22. All odd numbered rows, i.e. rows 23, 25, etc. of the upper half 21 define one quadrant, - all even numbered rows of the sumo wrestler half 21, i.e. rows 24, 26, etc. define two quadrants. Determines the quadrants of the eye. This division is also visible in the lower half 22.

Data created by a computer or other data source is a single stream of data.

These data are buffered in the screen drive circuit before being transferred to the screen. By utilizing the present invention, the data can be divided into four quadrants as it enters the buffer, as it exits the buffer, or a combination of the two.

A preferred embodiment of the invention splits the data as it enters the buffer.

Outline of the invention A block diagram of a preferred embodiment of the invention is shown in FIG.

Two counters, namely input counter 61 (fifth
) and the output counter 62 (details shown in FIG. 4) are connected to the memory 6 through a multiplexer 63.
4 (details of each are shown in FIG. 31).

These counters use memory in a time-divided manner and operate independently of each other. In this example, both counters each have a frame rate of approximately 60)tzO.

Address information is provided by multiplexer 63 and memory 64.
It can be input through an address bus 66 connected to the address bus 66.

Data is input through a data bus 67 connected to a multiplexer register 65. By passing through multiplex T-63, input counter 61 places address information and data into memory 64 located at locations corresponding to the four quadrants of the display screen.

Output counter 62 also extracts data from memory 64 via multiplexer 63 and transfers it to shift register 65. This shift register 65
buffers the data one byte at a time for each quadrant. Data lines 71-74 each have 1
It supports two quadrants and transfers data to the appropriate screen location. A clocking and control unit 70 is coupled to each block to synchronize the circuitry and control read/write operations.

Data Input In embodiments of the present invention, information from a data source (computer) is transmitted to the circuit sequentially on separate pit clocks, synchronized both vertically and horizontally on the same line. For example, in the embodiment described above, the pit clock is 14 MHz. The output of the data source '5IROUT', shown in FIG. Register 76 is sent to data bus 3.
Connected to 6. In this way, the driver circuit processes the video output from the computer one byte at a time.

In the computer utilized in the preferred embodiment, the video signal is provided in a 40 or 80 column format for a CRT. In order to buffer that data, the liquid crystal display driving circuit must know in what mode it is being used. The 40/80 column signal is used as the LDPS input of the drive circuit of FIG. This circuit determines whether the input signal is in 40 or 80 column mode. The LDPS signal is input to counter 77 along with a 0.14 MHz clock signal from the data source. The output signal of the counter 77 is converted and inputted to the P terminal of the tree flop 78. The output signal of this flip-flop is input to the flip-flop 7S, and the two output signals from this flip-flop 79 are in the 40th column and the 80th column.

M4OW is a signal from the data source and is a composite horizontal and vertical synchronization signal. LC60 is the main clock signal from the data source and is the input clock signal to counter 69. The HWNDW keeps its output low despite the influence of the input signal of the counter 69 and other signals. The output signal of counter 69 passes through the inverter via line 19. Converted signal (line 10
3, top) is VSync 40, a timing signal which controls the vertical synchronization of data input through the input counter (shown in FIG. 5). Also, VSy
nc40 is also supplied to the enable input of counter 69.

HWNDW is also used to generate a valid data signal that tells the input counter shown in FIG. 5 when to start counting. ff
1DW is also input to a clip-flop 110, which is connected to a flip-flop 111 to form a shift register. The output signal of flip-flop 110 is input to data selector 80 along with the output signal of clip-flop 111.

This selector 80 receives a selector signal 40eott.

The output signal of data selector 80 is transferred to flip-flop 68 where a valid data signal 90 is created.

The HWNDW decoding from the control signal data source is also an input to the control circuit shown in FIG. This signal is flip 7
There is an input bribe to 0tsubu 112. This clip-flop 112 is connected to a flip-flop 113 to form a shift register.

The output signal of each of these flip-flops is N
The output signal of this NAND gate is the source of the input signal of the counter 114. The input signal to counter 114 is also comprised of the 80Cot signal and signal SS shown in FIG.

The signal SS is a signal containing a constant having a large value.

The output signal of counter 166 is signal Q. -Q.

The signal Q is passed through three 7-lip-flops at CCLK29, and the output signals of each of these 7-lip-flops are CCLKl and CCLK2.

Melt it with CCLK3. These three signals are the signals Lj that control the operation of the four parallel-series registers shown in Figure 3b.
), these registers create the data that is transferred to the four quadrants for display.

CCLK is a clock signal used as a timing signal for the input/output counter portion.

Further, CCLK is inverted and inputted to the counter 115, which outputs the main clock signal LC60, while the output signal of this counter is input to the parallel-series registers 41 to 41 shown in FIG. LOAD 89, which is used to enable LOAD 89.

The signal Q, is inverted and sent to the NAND gate 1 along with the optical signal Qo.
16. The output signal of this gate is Qll and l
), this QEl is the enable signal for the RAM 38 shown in FIG. 3a.

The output signal of the NOR gate of signal Q and signal Q3 is NA
It is input to the ND gate 117 together with the signal Q0.

The output signal of gate 117 is Qm (14), which is the enable signal for RAM 39 shown in FIG. 3a.

Also, the output signal νW of the OR gate of the signal Q0 and the signal Q
stands for a read/write signal, which is the signal that operates the register 37 shown in FIG. 3a. Also, this signal is signal Q. tQlt and Q.

NANO gate 11 along with the output signal of the NAND gate of
It can also be determined by the input signal to 8. The inverted output signal of this gate 11B is V/L, and this signal V/L is the selector manual signal to the multiplexer T-31 to T-34 shown in FIG. 3a, and the information from the input counter or output counter. It can also be used as a signal to determine whether or not to transfer data to the memory of the drive circuit.

Now, referring to FIG. 9, this figure shows a selection method for selecting either RAM3B or RAM39 shown in FIG. 3a. The two counters 119 and 120 are connected in cascade fashion.

Output signal 124 of counter 119 and counter 120
The output signal 123 is input to the NANO gate 121, and the output VLOADIN30 of this gate controls the input counters 51-53 shown in FIG. The output signals 124 and 125 of the counter 119 are also input to the NAND gate 122 along with the output signal 123 of the counter 120 and the signal CCLKI from FIG. The output signal P of this gate becomes the P input of the clip clock 126. The output signals of this clip clock 126 are V13 and V13'. Signal V13 is input to OR gate 128, and signal v13' is input to OR gate 129.

The other input signal to each gate is the combination of the signal R/W from FIG. 10 and the valid signal 90 from FIG. 8 which has passed through OR gate 127. gate 1
The output signal of 28 is R/'wO.

This is a read/write signal for the RAM 39, and the output signal R/'Wl of the gate 129 is the RA signal shown in FIG.
This is a read/write signal for M38. The higher the value of R/WO, the lower the value of R/Wl, and vice versa. The switch occurs every 35 counts.

Input Counter FIG. 5 is a schematic diagram of the input counter. The role of the input counter is to control the timing of inputting data from the computer source to the circuit's memory.

Counters 51, 52, and 53 are each 4-bit binary data synchronous counters. The countable input of each counter must be high enough to allow the counter to count. A valid data signal 90 generated by the control circuit of FIG. 8 enters amplifier 51 via line 91. is connected to the countable input terminal of this chip, and when valid data is received, it is raised to a level high enough to be counted.The output signal of chip 51 is passed through line 92 to the countable input terminal of chip 52. The output signal of chip 52 is connected through line 93 to the countable input of amplifier 53.

Therefore, chip 52 can be counted when the output signal of chip 51 is high, and chip 53 can be counted when the output signal of amplifier 52 is high.

CCLK29 is a clock signal for each chip. This signal was created by the control circuit shown in Figure 10,
It is also a signal split from the data source. Counting or loading is performed when CCLK pulse 29 becomes a positive value.

When the VLoaden signal 30 is low, the input signal of each counter is also shifted to the output of each counter when the next clock becomes a positive value. The output signal of the amplifier 51 is V. -■8, chip 52 is V.

~V9, and the amplifier 53's is v8~V engineering.

The VLoadsn signal 30 must always satisfy the cent amplifier requirement and time maintenance requirement of the CCLK signal 29.

The output signals of these counters are sent to the multiplexer shown in FIG. 3a, the latches 54 and 55 shown in FIG.
The transmission method is applied to the reset circuit shown in the figure.

Lunch 54 and 55 are at counters 51, 52) and 53
Input the output signal of These launches operate when the valid data signal 90 is low. In operation, counters 51 to 53 count 0 to 34, and repeat 35 to 69.
Count 70 to 104, repeat,
Continue this until 3359. The use of latches 54 and 55 makes this possible. When the count starts, the lunch memorizes 0. When the count reaches 34, the value of vLoaden 30 becomes low, and the launch count number O becomes the output value of the counter, ie, 34, when the primary clock signal turns positive.

When valid data signal 90 goes low, latches 54 and 55
stores the previous output value 34. After counting to 34 twice, counting continues from 35 to 69.

When the counter passes 35, a valid data signal 9
0 becomes low and a value of 35 is stored for lunch. The count continues until 69, at which point VLoad n30
becomes low, which causes 35 to be read as the output value of the counter and becomes the contents of the latch. Once the count reaches 69 twice, counting continues, but when the count passes 70, the latch stores the value of 70. This process continues up to a count value of 3359. At this stage, any output signal of the counter is transferred to the reset circuit and read high.

These output signals are vO, vl*vl *V4 +v
8 +vl O* and vll terol O These signals are passed through an inverter and input to the 7 limp clock 56. Clip-flop 56 receives enable signal CCLK
29, this signal is passed through NAND gate 94 to a low value. The signal that has become low is the signal Vs
It is input to the gate 95 together with ync 4 Q. Vs
ync 40 is a vertical synchronization signal. The output signal of gate 95 is transferred over line 58 and applied to the input terminal of each counter.

When the value of this signal is low, the value of the output signal of the counter is set to a small value, regardless of the value of the enable input signal.

This setting is struck the next time the clock signal changes to a positive value. In this way, the entire count of vehicles is repeated. The purpose of the input counter is to
It is the capture of sequential output signals from a data source into memory such that they are divided into two parts. Referring to Figure 1, the first line in quadrant 11 is entered into memory the first time the counter counts from 0 to 35"1. Then, when the counter repeats the cycle, , the first line of quadrant 12 is entered into memory.This process is followed by all lines of quadrant 1i in the left half of the screen, quadrant 1i in quadrant 13 and quadrant 1 in the right half.
2. Continued alternating with all 14 lines.

The output signal of NAND gate 94 is also transmitted to flip 70 tube 57 through an inverter.

The clip flop 57 is a multiplexer f of FIG. 3a.
-34, and also plays an auxiliary role in determining which part of the memory to input data into.

Output Counter FIG. 4 is a schematic diagram of the output counter. The output counter controls the output of data transmitted from the drive circuit memory to the display screen. The output counter uses memory in a time-sharing manner with the input counter. These two counters operate independently of each other.

4-bit binary data synchronous counters 81, 82) and 83 are connected in cascade form. counter 81
The output signal of counter 82 is an enable input signal of counter 82, and the output signal of counter 82 is an enable input signal of counter 83. The enable input signal of counter 81 is coupled to signal SS;
SSO value is always high. For the counter to count, the value of the enable input signal must be high, so the counter 81 is always enabled to count.

The counter continues counting from 0 to 3359, at which point the counter resets to O and repeats this cycle. Output signal of counter 81 (L0 to L,)
, the output signal of the counter 82 (L4-L,), and the output signal of the counter 83 (L.

~L0□) is input to the multiplexer shown in FIG. 3a. Selected output signal L0. L□g LB HLB
g L4 @LB @L0°, and then L□□ is also transmitted to the reset circuit. When the counter counts to 3359, these selected output signals are read high.

This value signal is converted and transferred on line 88 to the counters 81-830 input terminals.

If this signal is low, the output signal will be low regardless of the value of the enable input signal. In this way, the counting cycle is started anew.

Counting begins when clock pulse signal LC6G turns to a positive value. This LC signal 60 is the main clock signal sent from the computer.

Counters 84 and 85 are connected in cascade format. An LC signal 60 is input to both counters. The enable input signal of counter 84 is coupled with a high value signal SS.

From the three pins of the 4-bit input of each counter, the signal S
S is input, and the remaining one is connected to GRD. The output signal of counter 85 is input to NOR gate 97. Another input signal to the NOR gate 97 is the output signal of the flip-70 tube 87, 6D, and the input signal to the flip-70 tube 87 is transferred on line 88. If either of these inputs has a high value, NOR
The output signal of gate 97 is set to a lower value. The output signal of NOR gate 97 is the load signal of counters 84 and 85.
Alternately transmitted to bin 9. If this signal has a low value, the counter's input signals (GRD and SS) will be converted to the corresponding output signals the next time the clock signal changes to a positive value. This causes the output signals of counters 84 and 85 to alternate arbitrary values, while a new count can be started.

On the other hand, the output signal of the counter 85 is also transmitted to the clip/7o tube 96. One of the output signals of seven limp flops 96 is transferred down line 9B to NOR gate 1.
02 is input. Another output signal of the flip 70 tube 96 is transferred through the line 99 to the clip 70 tube 10.
1 and the output signal of the 7 limb clock 101 is transmitted to the NOR gate 102. If the value of the output signal of counter 85 is high, the value of the output signal of gate 102 will also be high as a result.

The output signal of the game) 102 then passes through five D-type 7 lip-flops, each acting as a register. Each of the seven lip-flops receives the signal CCLK.
29 is used as a clock signal. The output signal of the third 7-lip flop 104 is CPI, which is the clock signal that is transmitted to the display screen to provide horizontal synchronization. The output signal of the second 7-lip/7a block 105 is CPI+1, and the output signal of the fourth flip-flop 105 is CPI-1. The output signal of the fifth clip 70 tube 107 passes through a set-reset circuit and becomes one of the input signals of the NOR gate 109. The output signal of gate 109 provides vertical synchronization of the display screen. Two other signals are input to the gate 109. The first one is a 7-lip prop 8 which is transferred on line 88 and uses signal LC as a clock signal.
This is the signal transmitted through 7. The second is signal C
This is the output signal of the NOR gate 108 which receives PI, CPI+1, and CPI-1 as input signals.

At the end of each count vehicle, the output signal of the reset circuit is passed through an inverter and seven lip-flops 86 to become signal M. At the end of each scan of the liquid crystal display screen, signal M acts as a logic level converter, alternating between high and low values. Signal M ensures that no direct current signal is transmitted to the screen. It is guaranteed that this will not happen.

Data Storage and DisplayThe method of data storage and display on a screen is best explained by the connection between Figures 3 and 3b. In the embodiment described above, two 0MO8 static RAMs 38 and 39 are used as memories. Each song has a capacity of 8 x 8. If the display screen is divided as shown in Figure 1,
RAM 39 holds data related to the left side of the screen which is located in quadrants 11 and 13;
and 14, the related data is stored on the right side of the screen.

Also, if the screen configuration is as shown in Figure 2,
RAM 39 stores data of all odd-numbered columns,
RAM 38 stores data in even-numbered columns.

Multiplexers 31 to 33 are multiplexers that select one line of data from two lines), RAM 38
and controls storage and retrieval of data by the RAM 39. The input signals of these multiplexers are the output signals of the input counter and the output counter. For example, the multiplexer f-31 has an input counter 5 shown in FIG.
V, which is the input signal from 1. -v8 and an input signal Lo-L from the output counter 81 shown in FIG. 4 are input. The input signal V/L from FIG. 10 is input to each multiplexer as a selection signal. The input signal V/L determines whether the value of the input counter or the value of the output counter is output to the output line of the multiplexer.

The fourth multiplexer t-34 inputs V□ and Llm as input signals and input signal selection signals η.

The output signals A12 and A1τ of this multiplexer are R
Of the bits input to AM38 and RAM39, these are the most important bits for each RAM.

Looking at the RAM 38, if the value of the signal A17 is high, the data will be related to quadrant 12, and if it is low, quadrant 14 will be used.

Shift register 37 stores data transmitted from bus 36 one byte at a time. The enable input signal for register 37 is generated by the control circuit shown in FIG. It is related to R/W (read/write) signals. When a read cycle is running, register 37 is off. When a write cycle is active, register 37 transfers data to bus 49.

The memory of this register 37 is communicated to a bus 49 connected to four parallel-serial registers 41-44. These registers receive one byte of data and convert it to serial. After conversion, registers 41-44 transmit this data to flip-flops 45-48, respectively. The output signals of these seven lip-flops are transmitted to a screen, with each output signal contributing to one of the four quadrants of the screen.

During operation, the signal from the input counter is sent to the multiplexer.
31-34, address signals from the address bus are stored in RAM 38 and RAM 39. At this time, data from data bus 36 and registers 37 are written to locations for specific quadrants of the two RAMs.

For example, data for quadrant 11 is written to RAM 39. The R/WO signal generated by the control circuit shown in FIG. 9 operates the RAM 39. On the other hand, the R/Wl signal is RA
Stop the operation of M38. Then, if the value of data AI2 is a high value, the written data is handled by the RAM 39 as data for quadrant 11.

Output counter data is sent to multiplexers 31 to 34
When the input is input, the register 37 turns off and the RAM
The data stored in is read. Output enable signal Q
The capacitor and QEl can be created using the circuit shown in FIG. Parallel-
In each of the serial registers 41 to 44, one four-step process is performed for each column. The data is then communicated to the four quadrants of the screen.

Timing Signals The timing signals discussed herein and their relationship to each other are shown in FIGS. 11a and 11b. The 14 mega look lock signal is for the data signal from the data source. This is the main clock signal; all other timing signals are branched from this signal.

CCLK is a 1.78 MHz character clock signal.
This is the output clock for display. Along with this, C
CLKl, CCLK2, CCLK3 The signal CCLK controls the operation of reading four signals from the circuit memory. Every signal follows the previous one.
Generates main clock pulse.

The load 89 is a parallel-serial register 41 to 4 shown in FIG.
4 is controlled. When this signal is applied, data is passed through these registers from memory to the display screen.

Q controller and Qll control multiplex transmission of the data bus with enable signals that prompt the output of RAM 39 and RAM 38, respectively. Qlφ is a high value when the main clock cycle is an even number and a positive value, and QE is a high value when the main clock cycle is an odd number and a positive value.
l takes a high value.

L12 is 1 at the 12th address bit of RAM390.
7.Llf is set in the 12th address bit of RAM38. These signals disappear after one positive cycle of the main clock signal due to read multiplexing. Both L12 and L12' are 1.78 MHz signals.

V/L is a signal that determines whether input counter data is input to multiplexers t-31 to t-34 and output counter data is taken in as a result, and manages multiplexing of the address bus. ing. V/L is a 1.78 MHz signal.

R/W is a 1.78 MHz signal 1) that tells the timing of reading and writing to memory.

A low value signal is a read command.

As described above, the circuit of the present invention allows serial output signals of a data source designed for CRT display to be
It can be processed so that it can be used as a data source for LCD displays.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of an example of dividing a display screen, FIG. 2 is an explanatory diagram of another method of dividing a display screen,
Figures 3a and 3b are electrical wiring diagrams, which are explanatory diagrams of data input, storage, and output control in the present invention; the fourth factor is an electrical circuit diagram of the output counter; and Figure 5 is an illustration of the input counter 6 is a block diagram of the first embodiment of the present invention, FIG. 7 is an electrical circuit diagram of the input circuit, and FIG. 8 is an electrical circuit diagram of the second input circuit. 9 is an electric circuit diagram of a part of the input counter, FIG. 10 is an electric circuit diagram of a control circuit, and FIGS. 11a and 11b are arbitrary timing signal diagrams of the present invention. 61...Input counter, 62...Output counter, 63...Multiplexer-164...Memo! j-, 65...Shift register, 66...
... Address bus, 67 ... Data bus, 68
...control/timing device. Patent Applicant Abu I Conshi Rep Il-Distribution Agent Masaki Yamakawa (tbi lambda 2 people) J2! ? -2 n parrot 1

Claims (15)

[Claims] (1) A circuit for displaying serial information from a data source on a liquid crystal display screen, the circuit comprising: a first bus for connecting to the data source and supplying addresses to the aforementioned circuit; a second bus connected to the source and for supplying data to the aforementioned circuit; a memory device connected to the first and second buses for storing the information; and a memory device connected to the first bus. , an addressing device that divides the information into subsets; a first counting device connected to the addressing device and controlling the input of the information; a second counting device connected to the addressing device and controlling the output of the information. and an output device connected to said display screen and delivering a subset of said information to a particular location on said screen, whereby said information is effectively displayed on said screen. A display circuit for a liquid crystal display device. (2) The circuit according to claim 1, wherein the storage device includes a plurality of random access memories (
A circuit characterized in that it includes RAMS). (3) The circuit according to claim 1, wherein the addressing device includes a plurality of multiplexers. (4) The circuit according to claim 1, wherein the output device includes a plurality of shift registers. (5) The circuit according to claim 1, wherein the first counting device includes a plurality of binary counters. (6) The circuit according to claim 1, wherein the second counting device includes a plurality of binary counters. (7) a circuit for displaying information from a data source on a liquid crystal display screen, the circuit comprising an input device connected to the data source and receiving a serial data stream from the data source; a memory device connected to an input device and for storing said information in four subsets determined by address locations; said display screen connected to said memory device and electronically divided into four quadrants; a first counting device connected to said input device and for controlling the flow of said information to said memory device; a first counting device connected to said input device and configured to provide information divided into said memory devices; and a second counting device for controlling the flow of the information, whereby the information is effectively displayed on the screen. 8. The circuit of claim 7, wherein said input device includes four multiplexers connected to said memory device by an address bus. (9) The circuit according to claim 7, wherein the memory device includes two random access memories (R
AMS), one of whose memories stores information related to two of the quadrants of the display screen, and another RAMS stores information related to two of the quadrants of the display screen. 2. A circuit for receiving information relating to said RAMS, said RAMS being electrically connected to said output device. (10) The circuit according to claim 7,
The output device includes four shift registers connected together to receive address information associated with each of the four quadrants of the display screen from the memory device. . (11) The circuit according to claim 7,
The first counting device and the second counting device independently of each other,
Further, the circuit is characterized in that it operates at approximately the same speed. (12) The circuit according to claim 7,
The circuit characterized in that the first counting device includes a plurality of binary counters. (13) The circuit according to claim 7,
The circuit characterized in that the second counting device includes a plurality of binary counters. (14) The circuit according to claim 7,
A circuit characterized in that the display screen is substantially rectangular and is divided into four rectangular quadrants of equal size: top left, top right, bottom left, and bottom right. (15) The circuit according to claim 7, wherein the display screen is substantially rectangular and is divided into an upper half and a lower half, and the upper half is in an odd-numbered column. and an even numbered column, and the lower half is divided into an odd numbered column and an even numbered column.