JPH04275592A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To eliminate the need for a frame memory of a high-speed reading out type by allowing the allotment of the entire period of reading out to divided screens. CONSTITUTION:This liquid crystal display device has the frame memory having an address space for at least one screen, divides this address space to the address spaces for the upper screen and the lower screen and applies the respective image data groups stored in the divided address spaces to the two divided regions of a display panel. The above-mentioned liquid crystal display device has an address generating means for generating the address of the above- mentioned frame memory and a writing permitting means for permitting the writing to the address space for the lower screen when the value of this address exceeds the boundary address of the screen division while permitting the writing to the address space for the upper screen until the above-mentioned value exceeds the above-mentioned boundary address. Both of the divided address spaces are simultaneously accessed by this address at the time of reading out.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a liquid crystal display device, particularly a liquid crystal display device.
The present invention relates to a screen type liquid crystal display device. In recent years, as the display quality of liquid crystal displays (hereinafter referred to as LCDs) has improved, they have come to be widely used in display devices for various office automation equipment such as portable computers and word processors, as well as small televisions and LCD projectors. Ta.

However, efforts are still being made to improve the image quality of display devices using cathode ray tubes (CRTs). This accounts for a high proportion.

[0003] Therefore, the number of pixels of a liquid crystal display device (generally 6
40x400 or 640x480) to 1120x78
It is required to increase the voltage to about 0, but the problem with this is the drive duty (hereinafter simply referred to as duty) of the liquid crystal.

[0004] Here, the number of pixels is 640 x 400 (or 4
80) Normal LCD, 1120 x 780
If a large-scale one is called a high-resolution LCD, it is called a normal LCD.
The main duty is about 1/200 to 1/400. The duty is limited by the transmittance-effective voltage characteristics of the liquid crystal material. Even if the optimum material is selected, the maximum value will be only about 1/480.

[0005] Therefore, simply increasing the number of pixels will reduce the number of pixels by 1/
A high duty of 800 to 1/1000 is required, and this value easily exceeds the maximum duty (1/480) mentioned above, so in order to realize a high resolution LCD, it is necessary to do so without exceeding the maximum duty. There is a need for technology that enables an increase in the number of pixels.

[0006]

[Prior art] As such a technique, a liquid crystal panel is
A two-screen system is known in which the screen is divided into two screens and each divided screen is driven separately. Set the number of scanning lines of the split screen to normal L.
It is CD-sized and ensures the number of pixels of a high-resolution LCD across the entire screen. According to this method, the duty can be set for the split screen, and the duty can be set to be less than the maximum value.

By the way, in the two-screen system, image data such as a CRT video signal is developed on a frame memory, and this data is extracted separately for the upper screen and the lower screen. FIG. 8 shows an example of a conventional circuit that performs such processing. The frame memory 10 has an address space for at least one screen, and is switched to either a read mode or a write mode by a switch 11 operated according to a read/write switching signal R/W (W is negative logic). There is only one type of write address signal, and the write address of the frame memory 10 is designated by this write address signal. That is, all pixel data constituting one screen is written within the address specified by the write address signal.

On the other hand, two types of read address signals are input: a signal for the upper screen (R1) and a signal for the lower screen (R2), and one of these signals is switched by a switch 12 operated by a read address switching signal. selected.

That is, when R1 is selected, the upper half screen data is read out from the frame memory 10, while when R2
At the time of selection, the lower half screen data is read from the frame memory 10.

FIG. 9 is a timing chart of such a conventional circuit. The frame memory 10 alternately repeats a write mode and a read mode, for example, during a write period A.
Data D1 from the CRT video signal is written in, and upper screen data and lower screen data are read out in the next read period B.

[0011]

However, in such conventional liquid crystal display devices, the frame memory readout period (see period B in FIG. 9) is divided into two periods, one for the upper screen and one for the lower screen. Because the configuration was such that the readout operation for each split screen had to be completed in half the readout period, it was necessary to finish the readout operation for each split screen in 1/2 the readout period.
had the problem of requiring a high-speed read frame memory.

[0012] Accordingly, an object of the present invention is to make it possible to allocate the entire readout period to a split screen, thereby eliminating the need for a high-speed readout type frame memory.

[0013]

[Means for Solving the Problems] In order to achieve the above object, the present invention is provided with a frame memory having an address space for at least one screen, as shown in the principle diagram in FIG. In a liquid crystal display device that is divided into an upper screen and a lower screen and provides respective image data groups stored in divided address spaces to two divided areas of a display panel, an address generating means for generating an address of the frame memory. and write permission that allows writing to the address space for the upper screen until the value of the address exceeds the boundary address of the screen division, and when it exceeds the boundary address, allows writing to the address space for the lower screen. The method is characterized in that, when reading, both divided address spaces are simultaneously accessed by the address.

[0014]

[Operation] In the present invention, when writing, the address space on the upper screen is first selected and data is written into this space, and then, when the address value exceeds the division boundary address, the address space on the lower screen is selected and data is written into this space. Data is written to the space. Therefore, one screen is developed on the frame memory according to the data transfer order.

On the other hand, during reading, both divided addresses are accessed simultaneously, and the upper screen data and lower screen data are read out in parallel. Therefore, the split screen can be read out using the full readout period of the frame memory, and a high-definition two-screen system can be realized without using a high-speed readout type frame memory.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on the drawings. 2 to 7 are diagrams showing embodiments of a liquid crystal display device according to the present invention. First Embodiment FIGS. 2 and 3 are diagrams showing a first embodiment of the present invention.

In FIG. 2, 20 is an address generation unit (address generation means) that generates a write address signal WA and a read address signal RA, and 21 is a logic 1/lower half screen that detects the upper and lower boundaries of one screen. A split screen detection unit 22 generates a split screen designation signal CS of logic 0 in half the screen, and 22 is a frame memory having a total capacity x (x is equivalent to the number of pixels of 1120×780, for example) for at least one screen. .

[0018] The above address generating section 20 may set the initial value of WA to be the same as the initial value of the address of the upper screen based on the change in CS when switching to the lower screen during writing, or It has a function to set the desired value to a value with a certain offset value added.

The frame memory 22 has two memories 22a.
, 22b, and these memories 22a, 22b are
The entire capacity of the frame memory 22 is divided into halves (x/2). That is, the memories 22a and 22b are x
It has an address space corresponding to /2, and any address within the space is designated by a memory address signal MA that changes from A0 to Ak.

The memories 22a and 22b also have chip selection signals CSa and CSb input thereto in an enabled state (
When the logic is 1), a write operation (write) of the data DT or a read operation (read) of the written DT is executed according to the write address signal WA or the read address signal RA.

Here, the above chip selection signals CSa, C
Sb is a logic circuit (write permission means) 2 consisting of two OR gates 23, 24 and one inverter gate 25.
6, and this logic circuit 26 is generated when the read/write switching signal R/W (where W is logic 0) is logic 0.
That is, when "writing mode designation" is selected, ■If the split screen designation signal CS is logic 1, CSa is set to logic 1 (CSb
(1) is set to logic 0), while if the split screen designation signal CS is set to logic 0, CSb is set to logic 1 (CSa is set to logic 0). Alternatively, when the read/write switching signal R/W is at logic 1, that is, at the time of "read mode designation", both CSa and CSb are set to logic 1, regardless of the logic of (2) the split screen designation signal CS.

The operations of the two memories 22a and 22b can be summarized as follows. [Write mode] R/W CS CSa C
Sb Memory that is allowed to operate
Logic 0 Logic 1 Logic 1 Logic 0
Memory 22a Logic 0 Logic 0
Logic 0 Logic 1 Memory 22b [read mode] R/W CS CSa C
Sb Memory that is allowed to operate
logic 1 logic 1 logic 1 logic 1
Memories 22a and 22b logic 1
Logic 0 Logic 1 Logic 1 Memory 22
In other words, in the write mode, either the upper screen memory 22a or the lower screen memory 22b is specified according to the CS logic, and DT is written to the specified memory, while in the read mode, the memory 22a or the lower screen memory 22b is specified. Both memories 22a and 22b are designated and data is read from both memories simultaneously.

Therefore, as shown in the operational flowchart of FIG.
22b. As a result, the readout period is doubled compared to the conventional method in which 1/2 of the readout period is allocated to each memory, so a high-speed readout type frame memory can be eliminated.

This is especially advantageous for handling high-definition display data in which the data transfer clock (dot clock) is extremely high at 100 MHz (50 MHz even when interlaced). Second Embodiment FIGS. 4 and 5 are diagrams showing a second embodiment of the present invention. Note that parts common to those in FIG. 2 are denoted by the same reference numerals and their explanations will be omitted.

In FIG. 4, 30 is a conversion control circuit, and the conversion control circuit 30 converts a CRT video signal into a high-resolution dual-screen LCD video signal (DT). FIG. 5 is a block diagram of the conversion control circuit 30.

In this figure, 31 is an S/P converter;
2 is a write address generation section, 33 is a 1/2 screen detection section,
34 is a control timing generation section, 35 is a read address generation section, and 36 is a liquid crystal drive signal generation section.

[0027] The S/P converter 31 converts the serial
Parallel string L with video signal synchronized to dot clock
Converts to CD video signal DT, write address generator 3
2 is the lowest value (
A0) and a write address signal WA indicating the highest value (Ak) immediately before the input of Vsync and CSP is generated.

The 1/2 screen detection section 33 counts WA and generates a split screen designation signal CS when it reaches a predetermined value corresponding to 1/2 screen, and the control timing generation section 34
generates various timing signals including a read/write signal R/W based on a dot clock, Vsync, Hsync (horizontal synchronization signal), and the like.

The read address generating section 35 generates signals from the lowest value (A0) to the highest value (Ak) while the signal indicating the read period is outputted from the control timing generating section 34.
The liquid crystal drive signal generating section 36 generates various signals CONT for driving the liquid crystal panel.

Referring again to FIG. 4, 40 is a liquid crystal display section, and the liquid crystal display section 40 has, for example, 1120×780 pixels.
a liquid crystal panel (display panel) 41 that divides the display area into an upper screen area and a lower screen area, an upper screen data driver 42 that sequentially drives the data bus of the upper screen area, and a data bus of the lower screen area. It includes a lower screen data driver 43 that sequentially drives the scan canvas of the upper screen area and the lower screen area, and a scan driver 44 that sequentially drives the scan canvas of the upper screen area and the lower screen area,
Upper screen data DT read from frame memory 22
U and lower screen data DTL are written to liquid crystal cells in each screen area at a predetermined drive duty (for example, 1/400 units).

In such a configuration, memory selection in write mode is determined by the logic of signal CS. In other words, if CS is logic 1, the memory 22 for the upper screen
a is selected, and data DT is written to this memory 22a. Alternatively, if CS is a logic 0, the memory 22b for the upper screen is selected, and the data DT is written to this memory 22b.

On the other hand, memory selection in read mode is as follows:
Since the signal R/W becomes logic 1, both memories 22a and 22b are selected regardless of the logic of the signal CS.
Data is read from both memories simultaneously and in parallel.

Therefore, the entire reading period can be allocated to memory reading, and high-definition LCD display can be realized without using a high-speed read frame memory. Third Embodiment FIGS. 6 and 7 are diagrams showing a third embodiment of the present invention.
This is an example of application to an interlaced video signal in which two fields constitute one frame screen. Note that the same reference numerals are given to the same components as in each of the above embodiments, and the explanation thereof will be omitted.

To simplify the explanation, it is assumed that lines L1, L3, L5, and L7 are sent in the odd field, and lines L2, L4, L6, and L8 are sent in the even field. . L1 and L2 in the upper half of one frame
, L3, L4 are displayed, and the lower half shows L5, L6, L7,
L8 is displayed (see Figure 7).

In this embodiment, logic 0/
Field designation signal F (which becomes logic 1 in even fields)
(for write mode) and a line designation signal L (for read mode) that alternately repeats logic 0/logic 1 for each line.
use.

These signals correspond to the most significant bit (Ak) of the memory address. That is, Ak=0 (logical 0
), then the lower half of the memory space is specified and A
If k=1 (logical 1), the upper half of the memory space is specified. Note that the write address signal W of this embodiment
A and read address signal RA are from A0 to Ak-1
It has address values up to (address values excluding the most significant bit Ak).

In such a configuration, at the time of writing, the most significant bit (Ak) of the memory address changes for each field, so first, the line L of the odd field is
After 1 and L3 are written to the upper screen memory 50a,
The remaining lines L5 and L7 of the odd field are written to the memory 50b for the lower screen, then the lines L2 and L4 of the even field are written to the memory 50a for the upper screen, and then the remaining lines L6 and L7 of the even field are written to the memory 50a for the upper screen. L8 is written to the memory 50b for the lower screen.

[0038] That is, L1→L3→L5→L7→L2
→ The data input in the order of L4 → L6 → L8 is stored in the upper screen memory (L1, L3) → lower screen memory (L5, L8).
7) → Upper screen memory (L2, L4) → Lower screen memory (L6, L8) are stored in this order, and the data arrays in the two memories are [L1, L3, L2, L4], [L5, L7] ,
L6, L8].

Such an array can be rearranged into a desired display data array by skipping line by line.

Therefore, the logic of the most significant bit (Ak) of the address at the time of reading is changed for each line. By repeating Ak=0/Ak=1 alternately for each line, L1, L
Data can be read out in the order of 2, L3, and L4, and at the same time, data can be read out from the memory 50b for the lower screen as well.
, L6, L7, and L8.

Therefore, even in the case of an interlaced video signal, the data can be read out from the two memories 50a and 50b simultaneously in parallel, making it possible to eliminate the need for a high-speed readout type frame memory.

[0042]

According to the present invention, it is possible to allocate the entire readout period to a divided screen, and to realize a liquid crystal display device that eliminates the need for a high-speed readout type frame memory.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a configuration diagram of the first embodiment.

FIG. 3 is an operation timing chart of the first embodiment.

FIG. 4 is a configuration diagram of a second embodiment.

FIG. 5 is a configuration diagram of a conversion control circuit according to a second embodiment.

FIG. 6 is a configuration diagram of a third embodiment.

FIG. 7 is a screen display diagram of the third embodiment.

FIG. 8 is a configuration diagram of a conventional example.

FIG. 9 is an operation timing chart of a conventional example.

[Explanation of symbols]

22: Frame memory 41: Liquid crystal panel (display panel) 20: Address generation unit (address generation means) Address generation means 26: Logic circuit (write permission means)

Claims (1)

[Claims] 1. A frame memory having an address space for at least one screen, the address space being divided into an upper screen and a lower screen, and each image data group stored in the divided address space. In a liquid crystal display device, the address generating means generates the address of the frame memory, and the address generating means generates the address of the frame memory, and the address space for the upper screen until the value of the address exceeds the boundary address of the screen division. It is characterized in that it is provided with a write permission means that allows writing, and also allows writing to the address space for the lower screen when the boundary address is exceeded, and when reading, both divided address spaces are simultaneously accessed by the address. LCD display device.