JPS63131176A - Image display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an image display device, and particularly to a so-called video RAM type image display device that writes image data in an image memory, reads out the image data from the image memory, and displays the image data on a display means. Related to display devices.

(Prior art) For example, "Transistor Technology" February 1984 issue 3
The so-called Video R
An example of an AM image display device is described in detail.

In a conventional image display device of this type, a microprocessor and a CRT controller are connected to an image memory (video RAM).
The address bus, data bus, or control bus of the image memory is switched to the microprocessor side or the CRT controller side by a multiplexer.

(Problems to be Solved by the Invention) In conventional image display devices, the microprocessor and the display circuit often access the image memory at the same time, and when such simultaneous access occurs, the display on the CRT To prevent the image from flickering, priority is given to access from the display circuit side. Therefore, in this prior art, if there is a simultaneous access, the microprocessor is put on a wait, whereas the microprocessor can only access the image memory during the retrace period of the CRT, thus The disadvantage of this technology was that it reduced the processing power of the microprocessor.

Therefore, a main object of the present invention is to provide an image display device in which the displayed image on the display means does not flicker, and the processing capacity of the microprocessor does not deteriorate.

(Means for Solving the Problems) To put it simply, the present invention generates an image memory, a data writing means for writing image data to the image memory, and an address for reading image data from the image memory. address generation means for the address generation means; display circuit means for receiving and displaying image data from the image memory according to the address generated by the address generation means; connected between the output of the image memory and the display circuit means; a memory in which reading and reading can be performed independently and data is read out in the order in which they are written, and a control means that operates in synchronization with the data writing means to provide image data from the image memory to the memory, thereby displaying the data. An image display device in which circuit means receives image data from a memory.

(Function) The data writing means writes image data to the image memory in response to a predetermined clock, and on the other hand, the address generating means is controlled by the control means synchronized with the data writing means. Image data is transferred to that memory. The display control means obtains image data read from the image memory through this memory.

(Effects of the Invention) According to the present invention, since the data writing means such as a microprocessor uses the image memory in a time-sharing manner together with the control means, no weight is placed on the data writing means. can freely access image memory. therefore,
There is no reduction in processing power as in the past. In addition, the control means can operate asynchronously without being affected by accesses to the image memory by the data writing means, and therefore has the advantage of eliminating the need for complex bus management circuits that were conventionally required. be.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

(Example) FIG. 1 is a block diagram showing one embodiment of the present invention.

Microprocessor 12 and display circuit 14 share image memory 18. The microprocessor 12 is a predetermined CPU.
The CPU clock is supplied to the control circuit 20 and the address bus to the image memory 18.

Provided to multiplexers 22, 24 and 26 for switching control and data buses.

Multiplexer 22 has as its two inputs the address bus of microprocessor 12 and the address bus from CRT controller 16, and its output is connected to the address port of image memory 18. The multiplexer 24 also receives the control bus from the microprocessor 12 and the control bus from the control circuit 20 at its inputs, and its output is connected to the control port of the image memory 18. And multiplexer 26
The data bus of the microprocessor 12 and the display circuit 1 are connected to each other.
4, that is, the data bus of the FIFO memory 28, and this multiplexer 26 is connected to the data port of the image memory 18.

The multiplexer 22 connects the address bus of the microprocessor 12 to the address port of the image memory 18 while the applied CPU clock is at a high level, and connects the address bus of the CRT controller 16 when the CPU clock is at a low level.
The address bus from the image memory 18 is connected to the address port of the image memory 18.

Similarly, multiplexer 24 connects the control bus of microprocessor 12 to the control port of image memory 18 while the CPU clock is high;
When the U clock is at low level, the control bus from the control circuit 20 is connected to the image memory 18. Furthermore, when the CPU clock is at a high level, the multiplexer 26 connects the data bus of the microprocessor 12 to the image memory 18.
When the CPU clock is at low level, the data port of the image memory I8 is connected to the FIFO memory 28. In this way, microprocessor 1
2 can access the image memory 18 while the CPU clock is at a high level.

The display circuit 14 has its own clock generation circuit, and this clock generation circuit outputs two clocks, namely a character clock and a dot clock. The character clock is a CRT included in this display circuit 14.
It is synchronized with the display timing of , has a lower frequency than the CPU clock, and is given as a read signal to the FIFO memory 28 . Also, the dot clock is the dot (
It has a repetition frequency corresponding to the pixels) and is given as the output clock of a parallel-to-serial converter that receives bit parallel data output from the FIFO memory 28. That is, F.I.
The bit-parallel image data inputted from the FO memory 28 is provided bit (dot) sequentially as a video signal to the CRT by a parallel-to-serial converter in response to a dot clock.

The CRT controller 16 receives a CRTC clock from a control circuit 20, which will be explained in detail later, and generates an address of an image memory 18 for the display circuit 14.
A synchronization signal is given to the FIFO memory 28.

In addition to the above-mentioned CPU clock, the control circuit 20 also has a FIF clock.
FIFO write permission signal from O memory 28 (this is F
is output when the IFO memory 28 is not "full", that is, when there is an empty area), the above-mentioned CRTC clock is given to the CRT controller 16, and the F
A FIFO write signal is given to the IFO memory 28.

To explain in more detail, this control circuit 20 includes a D flip-flop 30 as shown in FIG.
An O write permission signal is given. A CPU clock inverted by an inverter 32 is applied to the clock input of the D flip-flop 30. The output Q of the D flip-flop 30 is provided as one input of the three-way NAND gate 34, and the output of the inverter 32, ie, the inverted CPU clock, is provided as the other input. Furthermore, the output of the inverter 32 is provided as one input of a two-man power NAND gate 40 via a delay element 36 having a predetermined delay time and an inverter 38, and the other input of the two-man power NAND gate 40 is connected to the inverter 3.
The output of 2 is given as is. The output of the NAND gate 40 is then given as the remaining input to the three-man powered NAND gate 34 described above.

The output of the Nant gate 34 passes through the inverter 42,
The above-mentioned CRTC clock is output, and this is the CRT clock.
is provided to the controller 16.

Further, the output of the Nant gate 34 is directly applied to the FIF○ memory 28 as a FIFO write signal, and is also applied to the multiplexer 24 as an image memory read signal.
output to the control bus.

Note that in the control circuit 20 shown in FIG. 2, the delay elements 36. Inverter 38 and two-person NAND gate 40
The timing diagram of the control circuit 20 shown in FIG. 2 is shown in FIG. There is. To explain in detail, the CPU clock as shown in FIG.
2 and applied to the clock input of the D flip-flop 30, while the FI as shown in FIG.
A FO write permission signal is given from FIFO memory 28. Then, the output of this D flip-flop 30 becomes as shown in FIG. 3(C).

On the other hand, since the delay element 36 delays the CPU clock inverted by the inverter 32 for a predetermined period of time, its output becomes as shown in FIG. 3(D). This delay element 36
Inverting the output of the inverter 38 and inverting the output of the inverter 32
The output shown in FIG. 3(E) is obtained from the NAND game (Nando game) 40 which receives the CPU clock inverted by the two-man power. Therefore, a FIFO write signal and an image memory read signal as shown in FIG. 3(F) are obtained, and as shown in FIG. 3(G), a
An RTC clock is obtained.

In operation, the microprocessor 12 operates as shown in FIG.
In response to the CPU clock shown in FIG. 4, the address and control signals (read/write signals) are output from the falling edge of the CPU clock, as shown in FIG. 4(B). In addition, when reading data from the image memory 18, the microprocessor 12 is configured as shown in FIG. 4(C).
As shown in FIG. 4(E), the CRT controller 16 takes in the image data on the data bus at the next falling edge of the CPU clock. Image memory 1 starts from the falling edge of the CRTC clock as shown in Figure 4 (D).
8 address and a synchronization signal for the FIFO memory 28.

Further, as shown in FIGS. 4(F) and 4(H), the multiplexers 22 to 26 switch between the CRTC cycle and the CPU cycle in response to the CPU clock shown in FIG. 4(A).

Furthermore, data is written into the FIFO memory 28 in response to the rising edge of the FIFO write signal as shown in FIG. 4(G). Then, the character clock shown in FIG. 4(I) from the display circuit 14, ie, flF
When the o-read signal becomes low level, Fig. 4 (J)
It is assumed that data is read from the first register of the FIFO memory 28, as shown in FIG.

The parallel-to-serial converter included in the display circuit 14 is composed of a shift register, for example, and takes in data at the rising edge of the character clock shown in FIG.
In response to the dot clock shown in K), bit series display data is sequentially output.

In the example shown in FIG. 4, the CRTC lock,
Image memory address, FIFO write signal, etc.
This shows the state when the FO memory 28 is not "full", and when this FIFO memory 28 is "full", this fourth
I would like to point out that it does not turn out as shown in the figure.

How the image memory 18 is read will be explained with reference to FIG. When using the n-word FIFO memory 28, at timing
The FO memory 28 contains data i-n, i-n+l,
..., i-2, n-1 pieces of data are stored. Therefore, since the FIFO memory 28 is not "full," the FIFO write permission signal is output at a high level as shown in FIG. 5(B).

Data i-1 is written to the FIFO memory 28 at the falling edge of the FIFO write signal, that is, at timing 2, so that the FIFO memory 28 becomes "full," and the FIFO write permission signal is as shown in FIG. B)
As shown in timing ■, the signal becomes low level once.

However, at the rising edge of the FIFO read signal shown in FIG. 5 (11), that is, at timing 2 in FIG. is completed, the FIFO memory is no longer "full" again,
As shown at timing 3 in FIG. 5(B), the FIFO write permission signal changes to high level again.

As mentioned above, at the falling edge of the CPU clock shown in FIG.
Since the IFO write permission signal is at high level, the CRT clock and FIFO write signal are output as shown in FIG. 5(C) and FIG. 5(G), and the image memory address is output as shown in FIG. 5(D). In the following period ■, the next data i is stored in the FIFO memory 28 as shown in FIG. 5(F) in response to the FIFO write signal shown in FIG. 5(G). written.

Since the FIFO write permission signal is at a low level at another falling edge of the CP[J clock, that is, at timing 2, the FIFO write permission signal is at a low level during the following period 2 when the CPU clock is at a low level, as shown in FIG. 5(B).
No FO write signal is generated.

The multiplexers 22 to 26 are then switched between the CPU cycle and the CRTC cycle as shown in FIG. 5(E), while data is read from the image memory 18 as shown in FIG. 5(F). , is stored in the FIFO memory 28, so the fifth
As shown in the figure (+), data is read out sequentially.

In addition, in the period [phase] in FIG. 5(A), CP
The reason why the high level period of the U clock is long is because it is assumed that the microprocessor 12 is weighted due to accessing other low-speed devices, and is unrelated to the read operation of the image memory 18. I would like to add this.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a circuit diagram showing details of the control circuit. FIG. 3 is a timing diagram illustrating the operation of the control circuit shown in FIG. 2. FIG. 4 is a timing diagram for explaining the operation when the microprocessor accesses the image memory in the embodiment of FIG. 1. FIG. 5 is a timing diagram illustrating the state in which the image memory is read. In the figure, 12 is a microprocessor, 14 is a display circuit, I6 is a CRT controller, 18 is an image memory, and 20
indicates a control circuit, and 2B indicates a FIFO memory. Patent Applicant Sanyo Electric Co., Ltd. Agent Patent Attorney Yama 1) Yoshihito (and 1 other person) 2 Figure 3

Claims (1)

[Scope of Claims] 1. An image memory, a data writing means for writing image data into the image memory, an address generating means for generating an address for reading image data from the image memory, and the address generating means. display circuit means for receiving and displaying image data from the image memory according to an address generated by the image memory, the display circuit means being connected between the output of the image memory and the display circuit means, and writing and reading are independent of each other; a memory from which data can be read out in the order in which they are written; and control means operable in synchronization with said data writing means to provide image data from said image memory to said memory, thereby said display circuit means receives image data from said memory. 2. The image display device according to claim 1, wherein the data writing means includes first clock generation means for generating a clock of a predetermined frequency. 3. The memory outputs a write permission signal indicating that data can be written when there is space in the data storage area, and the control means receives the clock and the write permission signal and sends a message to the address generation means. 3. The image display device according to claim 2, further comprising means for providing a clock for address generation. 4. The image display device according to claim 3, wherein the control means includes means for providing a write signal for writing data to the memory. 5. The image display device according to claim 4, wherein the display circuit means includes second clock generation means for generating another clock, and the memory is read out in response to the another clock. 6. The display circuit means includes a raster scanning display means, and the second clock generating means generates the other clock in synchronization with the raster scanning display means. image display device.