JPS61213897A - Image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION A) The present invention relates to an image display device suitable for a liquid crystal television.

(1) Conventional technology A conventional liquid crystal display device was divided into upper and lower halves, and pixel information was input and displayed for each of the divided halves.
-83892, JP 58-193588, JP 59-28192, JP 59-176
No. 985, etc., all of which can be used for television images and the like. However, as the number of pixels on a liquid crystal display increases, not only the responsiveness of the liquid crystal display but also the responsiveness of the driving elements becomes more apparent. If it is a TV video signal, etc., if it is sent directly to the drive element, the image will tend to be rough (and flicker on the screen).Therefore, the screen memory is used to temporarily store the received video signal and adjust the writing timing. You can change the writing speed and reading speed of the memory by aiming for the gap between the two screens, or you can have screen memory for two screens and use it alternately for writing and reading. However, these methods are undesirable because they require complicated timing control means, large-capacity memory, and deteriorate image quality (particularly display roughness).Furthermore, In these image display devices, the number of rows is roughly determined by the number of scanning lines, but the number of columns depends on the liquid crystal display or its driver, and can range from a coarse display of about 200 pixels to a CRT-like display with over 900 pixels. It was designed only for liquid crystal displays, and for example, increasing the number of pixels required not only increasing the memory capacity but also changing the handling of the video signal itself, which lacked applicability.

C) Problems to be Solved by the Invention The present invention has been made to improve the above-mentioned points, and has a relatively simple configuration, has good image quality, and has an image display that is easy to adapt to changes in the liquid crystal display. It provides equipment.

2) Means for solving the problem The present invention has a screen memory for one screen and a clock generation means for alternately writing and reading from the screen memory,
Timing means for controlling the writing of the screen memory - upper screen reading - writing - lower screen reading into one cycle using a timing delayed by an integer clock number of the clock generation means from the display timing indicating the effective display area. It is also equipped with control means.

E) Effect: Even if the number of columns is rarely changed, it can be handled simply by changing the capacity of the screen memory and the oscillation frequency of the clock generation means.The transfer speed to the liquid crystal display side can be slowed down, and the image quality is excellent. There is.

f) Embodiment FIG. 1 is a block diagram of an image display device according to an embodiment of the present invention.
FIG. 2 is a timing chart of the main parts.

I! In Figure 1, (1) is a twisted nematic type liquid crystal display, the electrodes of which are arranged in a matrix, and the screen (
(or electrode group) is divided into upper and lower halves that can be driven independently, each with 256x256 dots (512x dots on the entire screen).
256 dots). (2) is the driver for the liquid crystal display (1), which is a HD44100H manufactured by Hitachi.
It receives image signals serially transferred independently for the upper screen and lower screen, takes timing, applies bias, and drives the liquid crystal display (1).

(31 (31 is a screen memory that can store one screen worth of pixel information corresponding to the dots (pixels) of the liquid crystal display (1),
It consists of two 192-byte (65,536-bit) status graph-driven random access memories (equivalent to 131,072 bits). In order to simplify the explanation, the data per dot is assumed to be 1 bit (binarized information of white or black), but the present invention is not limited to this. (
4) (51 is the first and second address counter, both of which specify the address of the screen memory (31 (31) via selectors (6a) (6b) (for example, multiplexer integrated circuit, product number 74HC244, etc.) Then, the first address counter (4) increments the output by one address through the selector (6a) when writing, and ignores the lower 1 bit and outputs the output from the selector (6a) when reading the upper screen.
6b) (6λ), outputs a step at a speed of 2 times the step at the time of writing, and the address designation of these first and second address counters (41(5) will be described later. f71
(7) Ha! $1, second address counter (41 (51
This is presetting means for giving a start address to Current screen memo IJ (The address of 31(3) is displayed in hexadecimal (the display corresponding to decimal is 0,1~9)
9.10-15 are A-F), address 0000-1FFF
For addresses (for the upper side) and addresses 2000 to 3FFF (for the lower side), 0000 and 2000 are set or stored in the preset means (71), respectively.

(8) is an image processing circuit that includes a tuner, an intermediate frequency amplifier, etc., and serially outputs a video signal;

It may be configured only with a buffer or the like that receives video signals from a file device or the like. (9) is a timing means for receiving an image control signal from the image processing circuit (8) and generating a basic timing signal and a control signal for making the entire device work smoothly, and is provided with a clock generation means side. ing. The clock (CL) which is the output of this clock generating means a■ is generated within one clock as will be described later.
This is for alternately writing and reading 31. The image control signal that the timing means (9) receives from the image processing circuit (8) includes a vertical retrace signal, a horizontal retrace signal, and a display that provides a display timing indicating the effective display area of the sequentially sent pixel information. This is signal (2). The timing means (9) outputs an initial signal (Is) according to the display signal I after the vertical retrace signal (ψ), and the clock generation means (synchronizes the clock edge of 1G with the display signal I, and outputs an initial signal (Is) by one clock from the display signal 0. A delayed first timing signal (Dl) and a second timing signal (Dl) delayed by three clocks from display signal 0 are output.

(111) (11b) are the first and second timing signals (
DI) (Dl) and outputs a control signal according to the clock (CL).The gate means (11 is screen memo January 3 bar 3) is used to select the write mode and read mode of the gate means. (121) (12b) outputs the specified mode signal (IIL/W) and the sidewalk signals (CA1) (CA2) at the count-up timing of the first and second address counters (4) (51). % frequency.The gate means (11b) is a gate consisting of a toggle flip 70 tab etc. provided as appropriate to obtain the % frequency.On the other hand, the gate means (11b) transmits the video signal read from the screen memo IJ (31) to the driver (2) of the liquid crystal display (1). ) is used to output the transfer timing (CT), etc. for transfer to the image processing circuit (8). Note that (to) is a converter that converts the video signal serially transferred from the image processing circuit (8) into serial and parallel data in 8-bit increments. ,
It has a synchronous Schmitt buffer at the input stage, has the ability to binarize analog signals, and is given a timing signal for serial-to-parallel conversion by a gate α.

(2) (2) is an inverse converter that serially converts the parallel-converted video signal, and αωαη is a latch circuit for timing the video signal. Here, selector (6a
) (6b), gate means (11ri (Ilb), gate (
12m) (12b), inverse converter (15) (15], and latch circuit 00αη constitute the control means (2) for controlling the writing/reading operation of screen memo!J (3) (31), and among them, the gate means (11b) and inverse converter a5 ■Screen memo!
J (31) constitutes a liquid crystal control means αω that transfers the video signal read from 31 to the liquid crystal display side.

The operation will be explained based on the above-mentioned configuration and with reference to FIG. First, the image processing circuit (8) outputs a vertical retrace signal ■, a horizontal retrace signal ■, and a display signal I indicating a range containing effective pixel information from the received radio wave or the sent video signal to the timing means (9). ), and while the display signal I is present, an analog video signal is output to the converter 03). This video signal is sent to the converter αJ, where it is binarized and then converted into a parallel signal of 8 bits each in synchronization with the gate timing. The timing means (9) outputs an initial signal (Is) according to the display signal 0 after the vertical retrace signal M, thereby indicating the first and second addresses. The counter (41 (51) takes in the contents of the preset means (71 (7)).

Now, the memory modes of the screen memory (3) (31) are designated by the level of the mode signal (R/W) as the write mode and the read mode (2), and as mentioned above, the memory mode is alternately set by the clock (CL) of the clock generating means U. The memory mode is switched by timing means (9) and gate means (111).
It is started by the first timing signal (Dl) which is one clock later than the display signal -. This delay of one clock is because the converter can complete the conversion process during that time, but it is necessary to smooth the cycle of writing, reading from the upper screen, reading from the upper screen, and reading from the lower screen. , and the number of pixels in the column direction.

That is, in the present application, when writing for one screen is completed, reading for one screen is also completed (described later), but how many dots of pixel information are extracted within one horizontal scan is determined by the clock (CL) described above.
corresponds one-to-one to how many pulses are sent. Therefore, if the pulse width of the horizontal retrace signal ■ is 64 μS·ec and the pulse width of the display signal 0) is 40 μgee, then n
If there is a dot (n=256 in this example), then (40/n)μ
A clock (CL) of sec may be used.

From this lock (CL), the screen memo IJ to be written or read (the address of 3H31 is selectively given by the first and second address counters (41 (51). (4) is incremented by the gate means (11a) every time the read mode is set, and when the write mode is selected, the output is guided through the selector (6a), so the designated address starts at address [0000J and the write mode is set to four. The address is incremented by 1 each time.Then, it is output through the selector (6b) (6λ) every other time in the read mode W, but the least significant bit is ignored, so the speed is half that of the write/read mode. The read address is incremented.

On the other hand, the second address counter (5) has gate means (11
k), the gate (12b) increments into the write mode chain at half the cycle of the write mode W, and the output is sent to the screen memory (3) through the selectors (6b) and (6a) every other time in the read mode ■. guided by.

Taking the first frame as an example, the first address counter (
4) “0000” and the second address counter (5) l
'After -2000J is stored, the mode signal (R/W) starts to be output by the +s1 timing signal (Dl),
At the first timing (tl), the write mode (mode signal "H") is designated. This allows the latch circuit α
The video signal from e is sent to screen memo January 3) (3), but the address specified at this time is address roool)J by the first address counter (4).

At the next timing (t2), the clock (CL) enters the read mode (mode signal "L"), and "000
0'' address is read out and stored in the latch circuit (171).Furthermore, at the next timing ([3), the write mode W is set again, but the first address counter (4
) is stepped, so the video signal is stored in the screen memory (31
(31 r0001J0001J is done.

At the fourth timing (t4), the screen memory (3) (31 is the second address color (5)
) is guided through the selectors (6b) and (61), so the address [2000J is specified. (Immediately after turning on the power, this address video signal is not memorized, but normally the video from the previous screen is stored.)
・The contents of the address "0" are sent to the inverse converter 6, but from this time on, the second timing signal (Dl) causes the gate means (1
1b) begins to operate, so the inverse converter α9 is connected to the parallel
It is sufficient to carry out serial conversion and then complete the transfer by the time the signal is applied to the inverse converter 09. Therefore, the mode signal (
Transfer timing signal (CT) with twice the frequency of R/W)
is given. At the same time, if the latch circuit αη also allows output, the contents of address l'-0000J and the contents of address "2000" are simultaneously converted to a serial signal and the driver (2
) will be forwarded to.

Thereafter, writing and reading are performed alternately in the same way, but writing is performed sequentially one address at a time starting from address l'-0000J, and reading is performed sequentially, starting from address ``0000'' and pixel information for the upper side, and ``2000''. The pixel information for the sub-screen starting from the address `` is read out alternately, and when the pixel information for the sub-screen is read out, the data is transferred to the driver (2) simultaneously for the upper and lower screens.
But it is done independently.

Therefore, the video signal of the upper screen (address is 1ppp) is read out at the timing just before the writing of the first screen ends (the last address is address 3FFF), and the video signal of the lower screen (address is 3FFF) is read out at the timing immediately after. will be read out. In other words, the writing time and reading time for one screen are equal, and in reading, for the upper side, the video signal of the screen currently being written is read out, and for the lower side, the video signal of the previous screen is read out. Become.

As a result, the image signal input to the driver (2) is performed at a speed of 2 of the writing speed to the screen memo IJ (31 < 31 (i.e. serial clock frequency of the converter (13) = inverse converter (1
514 serial clock frequency x 2), and the continuity of the video signal is maintained on each of the upper and lower screens (the video signal is serial data, so the second half of the n-7th screen and the nth
(The first half of the screen is continuous), so the screen is stable even if it is a video.

In the above explanation, if the converter α button AD converter is included, 2 bits (4 gradations), 4 bits (8 gradations), 8 bits (16 gradations), etc. per pixel. All image information can be displayed in gradation using the same procedure.Furthermore, color signals can be used instead of gradation, or screen memory for three screens can be provided corresponding to the color signals, and the same procedure can be used for each color. You can also display it in color by stepping on it.

Further, the display signal I as the display timing indicating the effective display area of pixel information may be formed after counting the horizontal retrace signal l to be invalidated based on the vertical retrace signal M.
It is easy to use a blanking signal, and devices that directly output digitally processed pixel information, such as personal computers, also output a display timing signal, so this can be used directly.

However, the blanking signal and the display timing signal often have a timing shift, and the center of the original image often does not coincide with the center of the screen of the liquid crystal display (1). In this case, since the present invention uses the display signal I as the reference for memory and transfer timing, it is sufficient to shift the display signal (6). Figure 3 is a block diagram of the main parts at that time, including the image processing circuit (8) and the timing means (9).
) A counter for generating a delay signal may be connected in series to the display signal line between the blanking signal (2) (or the display timing signal), and the output delayed by j clocks from the blanking signal (2) (or display timing signal) may be used as the display signal (2). This j is actually useful between 0 and 8.

g) Effects of the invention As described above, the present invention provides two
When driving a divided dot matrix display using a screen memory with a storage capacity equal to the number of pixels, one cycle of memory usage consists of writing, main screen reading, writing,
In addition, the timing of using the memory is based on a timing signal that is delayed by the write/read clock from the display timing indicating the effective display area. It requires relatively few circuits, can transfer display information at half the writing speed of the memory, so the image does not flicker, and is highly versatile because it can immediately respond to the density of the screen in the horizontal direction.

[Brief Description of the Drawings] Fig. 1 is a block diagram of an image display device according to an embodiment of the present invention, Fig. 2 is a timing chart of its main parts, and Fig. 3 is a block diagram of main parts of another embodiment of the invention. It is. (1)...Liquid crystal display, (2)...Driver, (3
1(3)...Screen memory, (4)(5)...Address counter, (6a)(6b)...Serus) (9)...Timing means, α■...Clock Generating means, (11a) (11b)... Kate means, (12
k) (12b) ・'F'-to, α...converter,
Circle...Gate, (15)(15)...Inverse converter, scream αη...Latch circuit, (181...Control means, α9
...Liquid crystal control means.

Claims (1)

[Claims] 1) A liquid crystal display consisting of a dot matrix divided into two vertically divided pixels, and pixel information corresponding to the dots of the liquid crystal display.
A screen memory that can store data for a screen, a clock generation means for alternately writing and reading from the screen memory, and an integer number of clocks of the clock generation means based on the display timing indicating the effective display area of sequentially sent pixel information. 1. An image display device comprising: timing means for generating a timing delayed by a minute; and control means for controlling a write/read operation of a screen memory using a timing delayed from the display timing. 2) The timing means generates a first timing signal that is delayed by an integer number of clocks from the display timing, and a second timing signal that is further delayed by an integer number of clocks from the first timing signal, and the control means generates a first timing signal that is delayed by an integer number of clocks from the display timing; The present invention is characterized by comprising a liquid crystal control means that controls the write/read operations of the screen memory using a timing signal, and further transfers pixel information read from the screen memory to the liquid crystal display side using a second timing signal. An image display device according to claim 1.