JPH0573001A - Driving method for liquid crystal display device - Google Patents

Abstract

PURPOSE:To obtain a driving method for a liquid crystal display device by which high contrast is obtained without increasing the number of dividing a liquid crystal display panel whose scanning lines are many and which has a comparatively large screen. CONSTITUTION:In the driving method for the liquid crystal display device provided with the liquid crystal display panel 17 divided into two groups, respective scanning electrodes perform scanning in one field twice, and a means which divides a period when one scanning electrode performs scanning once into first to fourth periods and selects the liquid crystal display panel 17 of one group in the first and the third periods and selects the liquid crystal display panel 17 of the other group in the second and the fourth periods, and a means which simultaneously selects two consecutive scanning electrodes are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method of a liquid crystal display device having a relatively large screen used as a display of a liquid crystal television, a liquid crystal projector, a personal computer or the like.

[0002]

2. Description of the Related Art In recent years, liquid crystal display panels have become larger,
It is used as a display for LCD TVs and LCD projectors. The operation mode of the liquid crystal used in these liquid crystal display panels has been mainly the TN mode in the past, but recently, the STN mode with good contrast is widely used.

It is well known that the contrast of liquid crystals decreases as the number of scanning lines increases with the increase in size of liquid crystal display panels. As a countermeasure, for example, as shown in Japanese Examined Patent Publication No. 52-19960, the signal electrodes of the liquid crystal display panel are separated at the central portion to be divided into upper and lower two groups, and each scanning electrode is selected by driving them in parallel. There is a way to double the time. It is also known that, particularly in the STN mode, an improvement in contrast is recognized when the frame frequency for driving the liquid crystal is increased.

[0004]

[Problems to be Solved by the Invention] Japanese Patent Publication No. 52-1996
According to the method of No. 0, the voltage margin for driving the liquid crystal can be increased and the contrast can be improved. Theoretically, the larger the number of divisions, the higher the contrast, but the number of divisions is limited to 2 in manufacturing, and further improvement in contrast could not be expected. Further, the method of increasing the frame frequency does not increase the margin itself, so that there is a limit to the improvement of contrast.

The present invention has been made in view of the above circumstances, and a driving method of a liquid crystal display device which can obtain a high contrast without increasing the number of divisions of a liquid crystal display panel of a relatively large screen having a large number of scanning lines. The purpose is to provide.

[0006]

To solve the above problems, the present invention provides a method of driving a liquid crystal display device having a liquid crystal display panel divided into two groups, in which each scanning electrode is scanned twice in one field. And one scan electrode is
The period scanned once is divided into first to fourth periods, and one group of liquid crystal display panels is selected in the first and third periods,
It is characterized in that it comprises means for selecting the other group of liquid crystal display panels in the second and fourth periods and means for simultaneously selecting two continuous scanning electrodes.

[0007]

According to the present invention, in a driving method of a liquid crystal display device having a liquid crystal display panel divided into two groups, each scanning electrode is scanned twice in one field and one scanning electrode is scanned once. The period is divided into first to fourth periods, one group of liquid crystal display panels is selected in the first and third periods, and the other group of liquid crystal display panels is selected in the second and fourth periods. And a means for selecting two consecutive scan electrodes at the same time, by using a memory having a smaller capacity than before and without increasing the data transfer rate of the signal side drive circuit. The drive frequency can be doubled. In particular, by setting the pulse width of the start signal to 2H and driving a plurality of scan electrodes corresponding to video data to double the selection period of each scan line, the duty becomes low,
The display margin is increased and the contrast is improved.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings.

This embodiment is an example in which the liquid crystal display device of the present invention is applied to a liquid crystal television. FIG. 1 is a block diagram of the liquid crystal television, and FIG. 2 is a time chart showing the operation state of FIG.

In FIG. 1, 1 is a television circuit section and 10 is a liquid crystal display section. In the television circuit unit 11, 11 is a tuner, an intermediate frequency circuit, a detection circuit, a color signal reproduction circuit,
It is a receiving circuit including a voice circuit. This receiving circuit 1
1 is R (red), G (gr) from the received television signal.
video signal S including video signals of een) and B (blue)
While taking out _v and supplying it to the A / D converter 13,
The horizontal synchronizing signal φH and the vertical synchronizing signal φV are taken out and supplied to the control circuit 12. The receiving circuit 11 also extracts an audio signal, but the audio system is omitted.

The control circuit 12 generates various timing signals for controlling the operation timing of the entire apparatus, and is synchronized with the horizontal synchronizing signal φH and the vertical synchronizing signal φV,
Start signal ST _{0 with} a pulse width of 2H, clock signal φ
s, latch signal φn, inverted signal φF, output inhibit signal IN
H1, INH2, switching signal SEL ₀ , address signal A
It outputs various timing signals such as D and read / write signals R / W. The control circuit 12 also outputs a multi-valued liquid crystal drive voltage V _LC . The A / D converter 13 uses the R,
The video signal S _v including the G and B video signals is A / D converted to convert each of the R, G, and B video signals into k-bit, for example, 4-bit digital video data.
A / D of three video signals of G and B at different timings
Conversion, R, G, video data B is output as video data D ₁ to D ₄ of 4 bits time-sharing. The video data E is supplied to the memory M and
It is supplied to the liquid crystal display unit 10. The memory M is an image memory, has a capacity of 1/2 field, and the address and read / write are controlled by the control circuit 12. The video data E _c output from the memory M is supplied to the liquid crystal display unit 10.

In the liquid crystal display unit 17, 17 is 240 ×
A STN type liquid crystal display panel of 528 dots, 15 is a shift register for serially inputting data E _c and data E, storing one scanning line and outputting in parallel, 14 is a switching circuit, and is output from the shift register 15. Data E
_c and data E are selected according to the switching signal SEL ₀ given from the control circuit 12, and are supplied to the signal side drive circuit 16 as data. The signal side drive circuit 16 is a signal electrode drive circuit that selects a predetermined liquid crystal drive voltage according to the data from the switching circuit 14 and applies it to the signal electrodes Y1 to Y528 of the liquid crystal display panel 17.

FIG. 3 shows one pixel portion of the switching circuit 14, which is composed of AND circuits 31 to 36, OR circuits 37 to 39, and an inverter 40. Of the video data E and the memory data E _C stored in the shift register 15 of 4 bits D _{1 to} D ₄ , D _{1 to} D ₃ are AND circuits 31 to 31.
3 is supplied to one of the input terminals of the AND circuits 3, and D ₄ is supplied to one of the input terminals of the AND circuits 34 to 36. To the other input terminal of the AND circuit 34 to 36 is supplied with the switching signal SEL _0, the AND circuit other in the input switching signal SEL ₀ of 31-33 inverter - is supplied via the data 40.
The outputs of the AND circuits 31 and 34 are input to the OR circuit 37, and the outputs of the AND circuits 32 and 35 are OR circuit 38.
The outputs of the AND circuits 33 and 36 are supplied to the input terminal of the OR circuit 39, respectively. As a result, the OR circuits 37 to 39 supply the signal E, that is, the data D _{1 to} D ₃ to the signal side drive circuit 16. The switching circuit 14 and the shift register 15 are composed of 528 stages as the unit shown in FIG.

In order to scan the liquid crystal display panel 17, reference numerals 18 and 19 sequentially shift the start signal ST ₀ having a pulse width of 2H from the control circuit 12 and output the output signals via the output control circuits 22 and 23. Scan side drive circuit 20, 2
1 is a shift register for supplying 1 Output control circuit 2
2 and 23 are output prohibition signals INH1 from the control circuit 12
This is for inhibiting the output of some signals by INH2. The scanning side drive circuits 20 and 21 are the output control circuit 2
A predetermined liquid crystal drive voltage is selected from V _LC in accordance with the signal sent via 2 and 23 and applied to the scanning electrodes of the liquid crystal display panel 17. The scanning side drive circuit 20 is a scanning electrode X.
1 to X120 are driven, and the scanning side drive circuit 21 drives the scanning electrodes X121 to X240.

The start signal ST ₀ having a pulse width of 2H generated by the control circuit 12 is a signal for determining the start timing for scanning the liquid crystal display panel 17, and is supplied to the shift registers 18 and 19. The clock signal φs serves as a sampling clock for the A / D converter 13 and also serves as a basic clock for operating the logic circuits constituting each circuit. The latch signal φn is transferred to the shift register 18,
19 is supplied to the start signal S having a pulse width of 2H.
It becomes a shift signal for shifting T _0, that is, a scanning timing signal of the liquid crystal display panel 17, and a latch signal for latching data for one line in the signal side drive circuit 16. The inversion signal φF is a signal for inverting the voltage (V _LC ) applied to the scan electrodes and the signal electrodes for AC driving the liquid crystal in a predetermined cycle, for example, one frame cycle. Output inhibit signals INH1, INH2
Is a signal which is supplied to the output control circuits 22 and 23 to inhibit a part of the outputs. The switching signal SEL ₀ is a signal for selecting one of the two inputs of the switching circuit 14. The address signal AD is a signal for designating the address of the memory M, and the read / write signal R / W is a signal for designating the read / write of the memory M. The control circuit 12 generates these timing signals at the timing shown in FIG.

In the liquid crystal display panel 17, the scanning electrode is X.
The STN type has 240 electrodes 1 to X240 and 528 signal electrodes Y1 to Y528. R, G, and B color filters are provided corresponding to the signal electrodes. Next, the operation of the above embodiment will be described.

The receiving circuit 11 is video signals from the received television signal S _v, the horizontal synchronizing signal .phi.H, the vertical synchronization signal φV is taken out, the video signal S _v to the A / D converter 13, a horizontal synchronizing signal .phi.H and vertical sync The signal φV is sent to the control circuit 12, respectively. The control circuit 12 uses the horizontal synchronizing signal φH and the vertical synchronizing signal φV to generate a start signal ST ₀ having a pulse width of 2H, a clock signal φs, a latch signal φn, an inverted signal φF, output inhibit signals INH1 and INH2, a switching signal SEL ₀ , and an address signal. Generating various timing signals such as AD and read / write signals R / W, the shift registers 15, 18,
19, the drive circuits 16, 20, and 21, the switching circuit 14, the memory M, the output control circuits 22 and 23, and the like. Further, the control circuit 12 generates a plurality of types of liquid crystal drive voltage V _LC and outputs it to the drive circuits 16, 20, and 21.

On the other hand, the A / D converter 13 converts the input video signal S _v into k-bit, for example, 4-bit (D _{1 to} D ₄ ) video data and outputs it to the memory M. The memory M reads the most significant bit (D ₄ ) of the video data according to the address signal AD and the read / write signal R / W from the control circuit 12.

The data of 1/2 field read into the memory M is 1/2 field later, and then the address signal AD and the read / write signal R / from the control circuit 12 are read.
According to W, it is read and output to the shift register 15 as 1-bit data Ec. Shift register 1
3 bits from the A / D converter 13 (D ₁
The timing relationship between the video data E of D _{3 to} D ₃ ) and the 1-bit data Ec from the memory M is as shown in FIG. The data E and the data Ec are stored in the shift register 15 in parallel every 4 bits in synchronization with the clock signal φs of the control circuit 12. The data E and the data Ec stored in the shift register 15 are output to the switching circuit 14 during the next horizontal scanning period H. The switching circuit 14 is the control circuit 1
According to the switching signal SEL ₀ from 2, the data E is selected in the first half ½H of the 1H period and the data Ec is selected and output in the second half ½H and is input to the signal side drive circuit 16. The signal side driving circuit 16 responds to the latch signal φn from the control circuit 12 and latches the data every 1 / 2H period. Further, the signal side drive circuit 16 selects the liquid crystal drive voltage V _LC corresponding to the gradation according to the latched data, and
_The polarity of the _LC is inverted in order to drive the AC by the inversion signal φF. Then, the signal side drive circuit 16 supplies the obtained signal to the signal electrode of the liquid crystal display panel 17. In addition,
When the data E is converted into the liquid crystal drive voltage V _LC , E × 2 ³ _Is converted into a voltage V _LC corresponding to

The start signal ST ₀ from the control circuit 12 which is at H level for 2H period for each 1/2 field is input to the shift registers 18 and 19, and in response to the clock signal φn, the shift registers 18 and 19 are sequentially shifted every 1H. Is shifted in. Therefore, each output signal in which only one bit of the shift registers 18 and 19 is at "H" level is always output to the output control circuits 22 and 23. The output control circuits 22 and 23 are
In accordance with the output inhibit signals INH1 and INH2, which are inverted every 1H in synchronization with the horizontal synchronizing signal φH, the shift registers 18 and 19 are alternately switched every 1H to switch the scanning side drive circuit 20.
21. That is, the output control circuits 22 and 23 apply the signals X'1 to X'120 and X'121 to X'240 to the scanning side drive circuits 20 and 21, respectively. This scanning side drive circuit 2
0 and 21 are output signals X'1 to X'120, X'121 to
X'240 is converted into the liquid crystal drive voltage V _LC , and the polarity of the voltage V _LC is inverted in response to the inversion signal φF in order to drive the liquid crystal display panel 17. Scanning side drive circuits 20, 21
The obtained AC liquid crystal drive voltage V _LC is applied to the liquid crystal display panel 1
7 to the scan electrodes X1 to X240 to apply the scan electrodes X1 to X240.
Drive the 240.

As described above, in the first half of each field, 1H, 121H (MS
B), 2H, 122H (MSB) …………… video data
(E, E _c ) is supplied with a drive voltage, and the scan electrodes are X ₁ , X ₁₂₁ , X ₁ and X ₂ , X ₁₂₁ and X ₁₂₂ ....
... are selected in this order. On the other hand, in the latter half of each field, 121H, 1H (MSB), 122H
The image data of H, 2H (MSB), ... Is supplied, and the scanning electrodes are selected as X ₁₂₁ , X ₁ , X ₁₂₁ and X ₁₂₂ , X ₁ and X ₂ ,. It Since liquid crystal has a storage effect, averaging one field means that correct driving is performed.

As described above, by setting the pulse width of the start signal ST ₀ to 2H, the output signals X'1 to X'240 of the control circuits 22 and 23 become as shown in FIG. 2 and the selection period of each scanning line. Is doubled. Therefore, the duty is reduced, the display margin is increased, and the contrast is improved.

[0023]

As described above, according to the present invention, in a driving method of a liquid crystal display device having a liquid crystal display panel divided into two groups, each scanning electrode is scanned twice in one field, and A period in which one scan electrode is scanned once is divided into first to fourth periods, one group of liquid crystal display panels is selected in the first and third periods, and in the second and fourth periods. By providing a means for selecting the liquid crystal display panel of the other group and a means for simultaneously selecting two continuous scanning electrodes, a memory having a smaller capacity than the conventional one is used and a signal side drive circuit is used. The drive frequency can be doubled without increasing the data transfer rate of. In particular, when the pulse width of the start signal is set to 2H and a plurality of scan electrodes corresponding to the video data are driven, the selection period of each scan line is doubled. Therefore, the duty is reduced, the display margin is increased, and the contrast is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing waveforms and data contents of each part of FIG.

FIG. 3 is a circuit explanatory diagram showing an example of a switching circuit of FIG. M ... Memory, 11 ... Reception circuit, 12 ... Control circuit, 13 ...
A / D converter, 14 ... Switching circuit, 15, 18, 19 ... Shift register, 16 ... Signal side drive circuit, 17 ... Liquid crystal display panel, 20, 21 ... Scan side drive circuit, 22, 23 ... Output control circuit.

Claims (3)

[Claims] 1. A method of driving a liquid crystal display device having a liquid crystal display panel divided into two groups, wherein each scanning electrode is scanned twice in one field, and
A period in which one scan electrode is scanned once is divided into first to fourth periods, one group of liquid crystal display panels is selected in the first and third periods, and in the second and fourth periods. A method of driving a liquid crystal display device, comprising: a means for selecting the other group of liquid crystal display panels and a means for simultaneously selecting two continuous scanning electrodes. 2. A memory for storing video data, wherein one of two scans in one field displays video data through the memory, and the other displays video data not through the memory. The method for driving a liquid crystal display device according to claim 1, wherein: 3. The method of driving a liquid crystal display device according to claim 2, wherein the memory stores only a part of video data.