JP2642578B2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for displaying an image of a television signal on an image display having, for example, a liquid crystal display element or the like as a pixel. The present invention relates to an apparatus capable of supporting display of a television signal transmitted by a television system.

[0002]

2. Description of the Related Art As is well known, recently, an image display (liquid crystal panel) having a liquid crystal display element as a pixel has been widely used because of its small size and low power consumption. Particularly in a television receiver, a twisted nematic (NT) mode liquid crystal capable of gradation display is often used. Further, at present, a liquid crystal color television receiver capable of performing color display by combining with color filters of three primary colors of red (R), green (G), and blue (B) has also appeared.

FIG. 6 shows a color television receiver using such a conventional liquid crystal panel. That is, reference numerals 11, 12, and 13 in the figure denote color signals R, G, and B, respectively.
Are input terminals respectively supplied. The respective color signals R, G, B supplied to these input terminals 11, 12, 13 are:
Positive polarity amplifier circuits 14a, 1 constituting the polarity inversion circuit 14
4b, 14c and negative polarity amplifier circuits 14d, 14e, 14
f.

Here, the polarity inverting circuit 14 amplifies each of the color signals R, G, and B with a positive polarity and a negative polarity, respectively, so as to enable an AC drive necessary for preventing deterioration of the liquid crystal. Is generated. The output signal of the polarity inversion circuit 14 is supplied to switches 15a, 15b,
15c. This polarity switching circuit 15 synchronizes with the frame pulse FP output from the timing generation circuit 16 and
4a, 14b, 14c and negative polarity amplifier circuits 14d, 14
An AC signal is generated by selecting each output of e and 14f.

The color signals R, G, and B selected by the polarity switching circuit 15 are supplied to switches 17a, 17b, 17
c is supplied to the color switching circuit 17 comprising C. The color switching circuit 17 synchronizes with the horizontal timing signal HP output from the timing generation circuit 16 to output the signal lines a, b, and c.
Are switched among the color signals R, G, and B to be output.

Here, the color signals R, G, B output to the signal lines a, b, c are supplied to an X driver 18. The X driver 18 includes a timing generation circuit 16
, S2,.
.., S480, and a buffer 20 for outputting the color signals R, G, B supplied to the signal lines a, b, c according to the output clock of the shift register 19. A line memory 21 for holding the output of the buffer 20, and a buffer 22 for outputting the color signals R, G, B held in the line memory 21 based on the clock OE output from the timing generation circuit 16. .

The clock SCK is obtained by equally dividing the image display period during the horizontal scanning period by the number of pixels in the horizontal direction (480), and the clock OE is generated during the blanking period in synchronization with the horizontal scanning synchronization signal. Is what is done.

The output D1 of the X driver 18 is
, D2, ..., D480 are supplied to the respective column electrodes 23a, 23a, ... of the liquid crystal panel 23. This liquid crystal panel 23 has the column electrodes 23a, 23a,... And row electrodes 23b, 2 orthogonal to the column electrodes 23a, 23a,.
3b, and a plurality of pixels 24, 24,... Arranged in a matrix in the horizontal and vertical directions. Then, the row electrodes 23b, 23 to which the signal is supplied
b,... connected to the pixels 24, 24,.
A display corresponding to the outputs D1, D2,..., D480 of the driver 18 is performed.

Here, the row electrodes 23b, 23b,...
, L0, L1,..., L of the shift register 26 of the Y driver 25 having the same number of shift stages.
By 219, a drive signal is selectively supplied. That is, the shift register 26, the timing generating circuit 1
, L219 based on a clock HCK generated in synchronism with the horizontal scanning synchronizing signal from S6, and the row electrodes 23b, 23b,.
.. Are sequentially scanned in the vertical direction.

Therefore, each pixel 24, 24,...
The color signals R, G, and B sampled by the number of pixels in the horizontal direction by the X driver 18 are supplied so as to be scanned in the vertical direction for each horizontal scanning period, and an image is displayed.

In this case, when the gate pulse GE is generated from the timing generation circuit 16 in response to the clock HCK, the shift register 26 controls each row electrode 23b,
Output signals L0, L1,..., L219 are generated at 23b,..., And their outputs are cleared based on a clear pulse FCL generated in synchronization with the vertical blanking period.

As shown in FIG. 7, a control electrode is connected to row electrodes 23b, 23b,... And one of the controlled electrodes is connected to column electrodes 23a, 23, as shown in FIG.
, and a liquid crystal 24b and a capacitor 24c connected in parallel between the other controlled electrode of the TFT 24a and the common electrode. When a signal is supplied from the Y driver 25 to the row electrodes 23b, 23b,..., The TFT 24a is turned on, and the output of the X driver 18 is supplied to the liquid crystal 24b and the capacitor 24c. In this case, the signal level supplied to the liquid crystal 24b is kept constant for at least one vertical scanning period by the capacitor 24c.

FIG. 8 is a timing chart showing the operation of the above-described liquid crystal color television receiver. That is, when the clock SCK is supplied to the shift register 19, the outputs S1, S2,...
480 is generated. Now, when the horizontal timing signal HP is L
Assuming that the color signals R, G, and B are supplied to the signal lines a, b, and c, respectively, at the (low) level, the color signals R, G, and B are output from the shift registers 19 to S, S2,. .. Are sequentially sampled in the order of G, B, R, G, B,...

When the sampling for one horizontal pixel is completed, the clock OE generated during the horizontal blanking period becomes H (high) level, and the line memory 2
, D480 of the X driver 18 are simultaneously supplied to the respective column electrodes 23a, 23a,... Of the liquid crystal panel 23 via the buffer 22. At this time, the horizontal timing signal H is synchronized with the clock OE.
P becomes H level, and the switch 17 of the color switching circuit 17 becomes
a, 17b, and 17c are switched so that the signal lines a, b, and
The color signals B, R, and G are supplied to c.

On the other hand, when the gate pulse GE is supplied, the shift register 26 of the Y driver 25 outputs its output L.
One of 0, L1,..., L219 (L0 in FIG. 8) is set to the H level. Then, the TFTs 24 constituting the 480 pixels 24, 24,.
a are all turned on, and the liquid crystal display of the first row in the horizontal direction is performed.

Thereafter, when the clock HCK is generated,
The clock OE goes low, and the shift register 26 attempts to set the output L0 to low and the output L1 to high. However, at this time, since the gate pulse GE has not been generated, the output L1 remains at the L level.

Then, the X driver 18 controls the clock SC
The color signals for one horizontal pixel are sampled based on K, and the liquid crystal display in the second horizontal row is performed in synchronization with the clock OE and the gate pulse GE. Thereafter, the same operation is repeated for 220 lines. Thus, image display for one field is performed.

By the way, as described above, the number of horizontal lines is 2
As shown in FIG. 9, about 20 small liquid crystal panels 23 of 4 inches or less have signals of odd fields Om, Om + 1, Om + 2,... Of the television signal and even fields Em, Em +. 1, Em + 2,... Are supplied to the same horizontal line to display one frame.

However, for example, in an NTSC television signal, since the number of effective horizontal scanning lines in one field is about 240, the liquid crystal panel 23 having 220 horizontal lines has an overscan rate of 8.3%. Will occur. In the PAL television signal, the number of effective horizontal scanning lines in one field is generally about two.
Since the number is 85, the liquid crystal panel 23 has 22.8
% Overscan rate will occur.

That is, unlike the cathode ray tube, the liquid crystal panel 23 has a fixed number of horizontal lines.
In a liquid crystal panel in which the number of horizontal lines is set in correspondence with the number of horizontal scanning lines in the TSC system, the PAL system (the number of horizontal scanning lines is larger by 100 per frame than in the NTSC system)
Cannot be displayed satisfactorily.

Therefore, conventionally, the difference in the number of scanning lines due to the difference in the television system has been absorbed, and for example, N
In order to enable display of a PAL television signal on a TSC liquid crystal panel, a color television receiver including a conversion unit as shown in FIG. 10 has been considered. That is, in the figure, reference numeral 51 denotes an input terminal to selectively supply an NTSC television signal and a PAL television signal.

First, when an NTSC television signal is supplied to the input terminal 51, the television signal is demodulated by the NTSC signal processing circuit 52 into a luminance signal YN, a chrominance signal CN, and a synchronization signal SN. Thereafter, the luminance signal YN and the chrominance signal CN are changed by the NTSC matrix circuit 53 to 3
Demodulated to primary color signals RN, GN, BN. The three primary color signals RN, GN, and BN are derived by an NTSC / PAL switch 54 switched to a state opposite to that shown in the figure, and passed through a polarity switching circuit 55 having the same configuration as that described with reference to FIG. The liquid crystal is supplied to the NTSC liquid crystal panel 56 for image display.

When a PAL television signal is supplied to the input terminal 51, the television signal is
The PAL signal processing circuit 57 outputs the luminance signal YP and the color signal CP.
After that, the PAL matrix circuit 58 demodulates the luminance signal YP and the chrominance signal CP into three primary color signals RP, GP and BP. These three primary color signals RP, GP, BP are converted into NTSC-synchronized three primary color signals RN ', GN', BN 'by PAL / NTSC conversion circuits 59, 60, 61, respectively, and then switched to the switching state shown in the figure. It is derived by the switched NTSC / PAL switch 54 and supplied to the NTSC liquid crystal panel 56 via the polarity switching circuit 55 to be used for image display.

Here, the PAL / NTSC conversion circuit 5
9 will be described. However, since the other PAL / NTSC conversion circuits 60 and 61 have the same configuration as the PAL / NTSC conversion circuit 59, description thereof will be omitted. That is, the analog primary color signal RP output from the PAL matrix circuit 58 is supplied to an A / D (analog / digital) conversion circuit 59a and quantized to about 8 bits at a sampling frequency of about 17.7 MHz. Is converted to digital data. Then, of the digital data output from the A / D conversion circuit 59a, odd field components are stored in the frame memory 59b, and even field components are stored in the frame memory 59c.

Here, the digital data stored in the frame memories 59b and 59c are read out such that one horizontal line is thinned out every predetermined number of horizontal lines.
After being read out by the line memory 59d at the synchronization timing of the NTSC system, it is converted into an NTSC-synchronized analog primary color signal RN 'by a D / A (digital / analog) conversion circuit 59e and output to the NTSC / PAL switch 54. You. That is, when a PAL television signal is supplied, the PAL / NTSC conversion circuits 59, 60,
By thinning out the horizontal lines by 61, it is possible to display an image of a PAL television signal on the NTSC liquid crystal panel 56.

However, in the above-described conversion means, three PAL / NTSC signals are used to digitize the three primary color signals RP, GP and BP and thin out the horizontal lines.
Since the conversion circuits 59, 60 and 61 are required, the number of parts is large and the configuration is complicated, which is economically disadvantageous. For example, it is not suitable for a so-called small-sized television receiver such as a pocket type or a vehicle-mounted type. Occurs.

[0027]

As described above, in the conventional image display device using the liquid crystal panel, it is not possible to display all television signals transmitted by a method having different numbers of horizontal scanning lines. Have a problem. In particular, the means for converting a PAL television signal to the NTSC system has a disadvantage that the configuration is complicated, unsuitable for miniaturization, and economically disadvantageous.

The present invention has been made in view of the above circumstances, and can cope with the display of a television signal transmitted by a plurality of television systems having different horizontal scanning lines in one field. It is an object of the present invention to provide a very good image display device which has a simple configuration, is suitable for miniaturization, and is economically advantageous.

[0029]

According to the present invention, there is provided an image display device comprising a plurality of pixels arranged at intersections of a plurality of horizontal signal lines and a plurality of vertical signal lines arranged in a matrix. Horizontal driving means for supplying video signals sampled for the number of pixels in the horizontal direction to each vertical signal line of the image display in synchronization with a horizontal scanning period of the video signals; A driving signal for causing each pixel to display the video signal supplied to each vertical signal line of the image display by the means is supplied to each horizontal signal line of the image display. and vertical drive means having a built-in shift register having a number and the same number of shift stages for the vertical direction driving means, a driving signal supplied to each horizontal signal line of the image display device is a video signal water Instructing means for instructing the movement of the scanning position so as to sequentially scan in the vertical direction in synchronization with the scanning period, and determining whether the input video signal is the first field or the second field. It is intended for the one provided with field discriminating means.

In the state where the number of horizontal scanning lines of the input video signal is larger than the number of horizontal signal lines of the image display, and the input signal is determined to be the first field by the field determining means, M × n + a (n = 1, 2, 3,..., M and a are positive numbers) of the horizontal scanning line of the video signal
A first detecting means for detecting the actual video signal, and the number of horizontal scanning lines of the input video signal is larger than the number of horizontal signal lines of the image display, and the field determining means determines that the input signal is a second field. in a state of being, m × horizontal scanning lines of the input video signal n + b (n = 1,2,3, ......, m
Is a positive number , b is a positive number that specifies a horizontal scanning line that is not continuous with a.
Number ) second detection means for detecting the first one, first or second detection means
Based on the detection output of the detection means
Stops instructing the direction driving means to move the scanning position.
In the state where the number of horizontal scanning lines of the input video signal substantially corresponds to the number of horizontal signal lines of the image display, the instruction of the scanning position movement to the vertical driving means by the instruction means is stopped. And control means for preventing the operation from being performed.

[0031]

According to the above arrangement, the input video signal
The number of horizontal scanning lines of the signal is
Input video signal in the first field
When the horizontal scanning line is m × n + a (n = 1,
2, 3, ..., m and a are positive numbers)
When the signal is in the second field, its horizontal scan line is
m × n + b (n = 1, 2, 3,..., m is a positive number, b is a
A positive number that specifies a horizontal scanning line that is not continuous)
With this configuration, it is possible to display video signals transmitted by a plurality of television systems having different horizontal scanning lines in one field. can do. In this case,
In addition, the horizontal scanning lines to be thinned are divided into the first field and the second field.
The values of a and b are set so that they do not
As a result, vertical discontinuities in image quality are less noticeable.
Can be.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. 1, the same parts as those in FIG. 6 are denoted by the same reference numerals, and only different parts will be described here. That is, each pixel 2 of the liquid crystal panel 23
The point that the function of the Y driver 27 that sequentially scans 4, 24,... In the vertical direction is changed to control the vertical scanning is different from the conventional one.

Here, the liquid crystal panel 23 has the number of pixels in the vertical direction corresponding to the image display of the television signal transmitted by the NTSC system, and the television signal transmitted by the PAL system and the television signal transmitted by the NTSC system. An example in which an image of a television signal is displayed will be described.

That is, the Y driver 27 sets the switch 28 to the power supply V when supplying a PAL television signal.
By switching to the cc side, and by switching the switch 28 to the ground side when supplying an NTSC television signal,
Each of the pixels 24, 24,... Is controlled in a different manner in the vertical direction, so that image display of both types of television signals can be performed well.

FIG. 2 shows details of the Y driver 27. In the figure, reference numeral 29 denotes an input terminal to which the clock HCK is supplied, which is connected to the clock input terminal CK of the 5-bit shift register 30, the input terminal of the knot circuit 31, and the input terminal of the AND circuit 32, respectively. In the figure, reference numeral 33 denotes an input terminal to which the gate pulse GE is supplied, which is connected to a gate pulse input terminal GI of the shift register 34 having a 220-stage output.

Further, in the figure, 35 is the frame pulse F
The input terminal supplied with P is connected to the input terminal of the NAND circuit 36 and connected to the input terminal of the NAND circuit 38 via the knot circuit 37. In the drawing, reference numeral 39 denotes an input terminal to which the clear pulse FCL is supplied, which is connected to each of the clear input terminals CL of the shift registers 30 and 34 and a D-type flip-flop circuit (hereinafter referred to as a D-FF circuit) 40. I have.

Here, reference numeral 41 denotes an input terminal to which a pulse ST generated at the start of display for each vertical synchronization signal is supplied. The input terminal 41 is connected to the shift register 34
And to the input terminal of the OR circuit 42. In the figure, 43 is the switch 2
Input terminals to which the power supply level Vcc or the ground level selected by 8 is supplied, and are connected to the input terminals of the NAND circuits 36 and 38, respectively.

The third and fifth output terminals QC and QE of the shift register 30 are connected to the input terminals of the NAND circuits 36 and 38, respectively. , Is connected to the input terminal of the AND circuit 32. The output terminal of the AND circuit 32 is connected to the clock input terminal CK of the shift register 34.

The fifth output terminal QE of the shift register 30 is connected to the input terminal D of the D-FF circuit 40, and the output terminal Q of the D-FF circuit 40 is connected to the OR circuit 42. Connected to input terminal. Further, the output terminal of the OR circuit 42 is connected to the input terminal D of the shift register 30.

Here, the shift register 30
Since the pulse ST goes high at the start of display, the input terminal D goes high. Then, the shift register 30
Sets the output terminal QA to the H level in synchronization with the rising of the clock HCK. When the next clock HCK rises, the pulse ST is at the L level, so that the output terminal QA is at the L level and the output terminal QB is at the H level. Thereafter, the shift register 30 has its output terminal QE at H level.
The shift operation is repeated in synchronization with the clock HCK until the level becomes the level.

The output terminal QE of the shift register 30
Becomes H level, the H level output of the clock HC
It is latched by the D-FF circuit 40 at the fall of K. Therefore, the input terminal D of the shift register 30 goes high again, and the output terminal QA goes high, and the same operation is repeated thereafter. Here, the above operation of the shift register 30 is continued until the clear pulse FCL is generated at the end of the vertical scanning.

For this reason, the H level is supplied to the NAND circuit 36 at the third H from the start of the display, and thereafter the H level is supplied to the NAND circuit 36 for 5H.
The H level is supplied every time. Therefore, now, the frame pulse FP that is inverted every vertical scanning is at the H level,
Assuming that the switch 28 is connected to the power supply Vcc side (H level), the output of the NAND circuit 36 becomes
H level, 8H, 13H, 18H,...
In other periods, it is at the H level.

Further, the NAND circuit 38 operates similarly. However, in this case, when the frame pulse FP is at the L level and the switch 28 is connected to the power supply Vcc side (H level), the output of the NAND circuit 38 becomes 5H, 10H, 15H, 20H, ... Go to L level every time, and go to H level in other periods.

Therefore, while the outputs of the NAND circuits 36 and 38 are at the L level, the clock HCK is not supplied to the shift register 34 due to the operation of the AND circuit 32.
The shift operation is not performed.

Each of the NAND circuits 36 and 38 receives the frame pulse FP inverted from each other. Therefore, one of the outputs of the NAND circuits 36 and 38 is fixed at the H level during one vertical scanning period, and only the other output can be at the L level as described above.

Here, the frame pulse FP is set to be at the H level during the odd field period and at the L level during the even field period. Therefore, the output of the NAND circuit 38 is fixed at the H level during the odd field period, and the output of the NAND circuit 36 is fixed at the H level during the even field period. Therefore, the output of the AND circuit 32 becomes L level at 3H, 8H, 13H, 18H,... After the start of display during the odd field period, and at 5H, 10H,.
... 15H, 20H,...

In other words, during the odd field period, the shift register 34 sets 3H, 8H, 13H, 1 after the start of display.
8H,..., The shift operation is not performed on the eyes, and 5H, 10H, 15H, 20
H,... No shift operation is performed on the eyes.

The shift register 34 is activated when the pulse ST is supplied to the input terminal D. Then, each time the gate pulse GE is supplied, one of the outputs L0, L1,..., L219 is set to the H level. Further, assuming that the output L0 is at the H level in synchronization with the output of the AND circuit 32, for example,
The output at H level is sequentially shifted in the order of L0, L1, L2,....

FIG. 3 is a timing chart showing the operation of the Y driver 27. The polarity of the color signals supplied to the signal lines a, b, and c is inverted every vertical scanning period.
Except for the overscan at the top of the screen, the pulse ST goes high at the start of display, and the output terminal QA of the shift register 30 goes high in synchronization with the clock HCK. Thereafter, every time the clock HCK is supplied, the operation of going high in the order of the output terminals QB, QC,... Of the shift register 30 is repeated.

Here, during the odd field period,
Since the frame pulse FP is at H level, the output of the NAND circuit 36 goes to L level in synchronization with the output terminal QC of the shift register 30 going to H level. Also, during the even field period, the frame pulse FP is at the L level, so that the output of the NAND circuit 38 goes to the L level in synchronization with the output terminal QE of the shift register 30 going to the H level.

As a result, the output of the AND circuit 32 is such that every fifth clock HCK is missing, and in the odd field, the outputs L1, L5,... In the field, the outputs L3, L7,... Of the shift register 34 are generated twice consecutively.

Therefore, in the odd field, the output of the X driver 18 continues for 2H with respect to the pixels 24, 24,... Of the liquid crystal panel 23 shown in FIG. The signal supplied in the first 1H of these 2Hs is overwritten and erased, that is, thinned out. In the even field, 4, 8, 1 from the top of the liquid crystal panel 23 shown in FIG.
The output of the X driver 18 is continuously supplied for 2H to the pixels 24, 24,... In the rows 2,..., And the signal supplied in the first 1H of the 2H is overwritten. Will be erased, that is, thinned out.

FIG. 4 shows a vertical scanning mode of the liquid crystal panel 23 by the Y driver 27 as described above. Horizontal scanning lines to be thinned out are shown by dotted lines. Thus, the odd fields Om, Om of the television signal
m + 1, Om + 2,..., and even-numbered fields Em, E
By alternately thinning out the signals of m + 1, Em + 2,... every 5H, the number of pixels in the vertical direction is set to 220 in correspondence with the number of horizontal scanning lines of the NTSC television signal.
Can be used to display 275 horizontal scanning lines at an overscan rate of 3.5% in one field of a PAL television signal.

When the switch 28 is switched to the ground side, the outputs of the NAND circuits 36 and 38 are both fixed at the H level.
K is all supplied, and the above-described thinning operation is not performed. For this reason, it is possible to display an NTSC television signal by the same operation as in the related art.

When the horizontal scanning lines are thinned out as described above, it is conceivable to thin out the fifth, 10, 15, 20,... Lines for both odd and even fields as shown in FIG. Then, since two consecutive signals per field disappear, the discontinuity becomes more conspicuous as the image quality.

On the other hand, as shown in the above-described embodiment, the horizontal scanning lines to be thinned out are not continuous in the odd and even fields, that is, m.times.
.., m and a are positive numbers, and n × a + n (n = 1, 2,
3, ..., m is a positive number , b is a horizontal scanning line not continuous with a
By thinning out and dispersing every ( specified positive number ) lines, discontinuities in image quality become less noticeable. In particular, in a small liquid crystal television receiver, since the odd field and the even field are overlapped and supplied to the same horizontal pixel line, the resolution in the vertical direction is deteriorated. The thinned PAL television signal hardly deteriorates. It should be noted that the present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the scope of the invention.

[0057]

As described in detail above, according to the present invention,
A very good image which can correspond to the display of television signals transmitted by a plurality of television systems having different horizontal scanning lines in one field, has a simple configuration, is suitable for miniaturization, and is economically advantageous. A display device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an image display device according to the present invention.

FIG. 2 is a block diagram showing a main part of the embodiment in detail.

FIG. 3 is a timing chart for explaining the operation of the embodiment.

FIG. 4 is an exemplary view for explaining a thinning operation of the embodiment.

FIG. 5 is a view for explaining an undesired example of the thinning operation.

FIG. 6 is a block diagram showing a conventional image display device.

FIG. 7 is a circuit diagram showing details of a pixel.

FIG. 8 is a timing chart for explaining the operation of the conventional device.

FIG. 9 is a diagram showing processing means for horizontal scanning lines by the conventional device.

FIG. 10 is a block diagram showing a conventional PAL / NTSC converter.

[Explanation of symbols]

11 to 13: input terminal, 14: polarity reversing circuit, 15: polarity switching circuit, 16: timing generation circuit, 17: color switching circuit, 18: X driver, 19: shift register, 2
0: buffer, 21: line memory, 22: buffer,
23: liquid crystal panel, 24: pixel, 25: Y driver,
26: shift register, 27: Y driver, 28: switch, 29: input terminal, 30: shift register, 31
... Knot circuit, 32 ... And circuit, 33 ... Input terminal, 3
4 shift register, 35 input terminal, 36 NAND circuit, 37 knot circuit, 38 NAND circuit, 39 input terminal, 40 D-FF circuit, 41 input terminal, 42 OR circuit, 43 input Terminals, 51 ... input terminals, 52 ... NT
SC signal processing circuit, 53 NTSC matrix circuit, 54 NTSC / PAL switch, 55 polarity switch circuit, 56 NTSC liquid crystal panel, 57 PAL
Signal processing circuit, 58... PAL matrix circuit, 59
61 to PAL / NTSC conversion circuit.

Claims (1)

(57) [Claims] 1. A plurality of horizontal directions arranged in a matrix
A pixel is located at each intersection of the directional signal line and the vertical signal line.
The image display that is installed, and the number of pixels in the horizontal direction is assigned to each vertical signal line of this image display
The video signal sampled every minute is
Horizontal driving means for supplying in synchronization with a scanning period; and
The video signal supplied to the direction signal line is displayed on each of the pixels.
The drive signal for indicating each horizontal direction of the image display
The horizontal direction signals to be supplied to the respective signal lines.
Same as the number of linesHave the same number of shift stagesBuilt-in shift register
Vertical driving means, and each water of the image display is provided to the vertical driving means.
The drive signal given to the horizontal signal line is
Scan in the vertical direction sequentially in synchronization with the horizontal scanning period
Instruction means for instructing movement of the scanning position; and whether the input video signal is a first field or not.
Field discriminating means for discriminating whether the field is No. 2
In the image display device having the following, the number of horizontal scanning lines of the input video signal is
More than the horizontal signal lines of the image display,
The field is determined to be the first field by the field discriminating means.
In the separated state, m × n horizontal scanning lines of the input video signal
+ A (n = 1, 2, 3, ..., m and a are positive numbers)Look into the eyes
First detecting means for outputting;  The number of horizontal scanning lines of the input video signal is
More than the horizontal signal lines of the image display,
The field is judged to be the second field by the field discriminating means.
In the separated state, m × n horizontal scanning lines of the input video signal
+ B (n = 1, 2, 3,...,m ispositive number, B is continuous with a
Positive number specifying no horizontal scan line)BookEye detection second
Detection means, On the basis of a detection output of the first or second detection means,
Running by the indicating means with respect to the vertical driving means;
Stop the inspection position move instruction, The input video signal
The number of horizontal scanning lines of the image display
In a state substantially corresponding to the number of direction signal lines,
Instruct the vertical drive means to move the scanning position.
Control means not to stopWhenCharacterized by comprising
Image display device.