JPH01218183A - Image display device - Google Patents

Abstract

PURPOSE:To cope with the display of television signals transmitted by plural television systems different in the number of horizontal scanning lines in one frame differ from each other by displaying an image by selecting a particular first television signal or second television signal. CONSTITUTION:The horizontal scanning lines in one field of the first television signal transmitted by a television system in which the number of horizontal scanning lines in one frame exceeds the number of picture elements in the vertical direction are scanned by interlaced scanning and line sequentially scanning alternately at every prescribed number of lines. An image is displayed by selecting this signal or a second television signal transmitted in a television system in which the number of horizontal scanning lines in one frame is approximately equal to the number of picture elements in the vertical direction. In such a way, television signals transmitted by plural television systems whose numbers of horizontal scanning lines in one frame differ from each other can be displayed as an excellent image.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an image display device that displays an image of a television signal using an image display device whose pixels are, for example, a liquid crystal display element. In particular, the present invention relates to a device capable of displaying television signals transmitted by a plurality of television systems having different numbers of horizontal scanning lines in one field.

(Prior Art) Recently, image displays (liquid crystal panels) using liquid crystal display elements as pixels have been adopted in many fields because of their small size and low power consumption. Particularly in television receivers, twisted nematic (NT) mode liquid crystals capable of displaying gradations are often used. Furthermore, liquid crystal color television receivers that can display color by combining color filters of the three primary colors of red (R), green (G), and blue (B) are now appearing.

FIG. 6 shows a color television receiver using such a conventional liquid crystal panel.

That is, 11 to 13 in the figure are input terminals to which color signals R, G, and B are respectively supplied. This input terminal 11-1
The color signals R, G, and B supplied to the circuit 3 are respectively supplied to a polarity inverting circuit 4 consisting of positive polarity amplifier circuits 14a to 14c and negative polarity amplifier circuits 14d to 14f'.

Here, the polarity inversion circuit 14 outputs each color signal R1G, B
is amplified with positive polarity and negative polarity, respectively, to generate bipolar signals to enable alternating current driving necessary to prevent deterioration of the liquid crystal. And this polarity inversion circuit 14
The output signal is supplied to a polarity switching circuit 15 made up of switches 15a to 15c.

This polarity switching circuit 15 connects the positive polarity amplifier circuits 14a-14e and the negative polarity amplifier circuits 14d to 14' in synchronization with the frame pulse FP output from the timing generation circuit 1B.
By selecting each output, an AC signal is generated.

Then, the color signal R selected by the polarity switching circuit 15,
G and B are supplied to a color switching circuit 17 consisting of switches 17a to 17c. This color switching circuit 17 receives a vertical timing signal V output from the timing generation circuit 16.
Color signals R and G are output to signal lines a-c in synchronization with P.
, B.

Here, the color signals R and G output to the signal lines a-c are
, B are supplied to the X driver 18. This X driver 18 operates based on the clock SCK outputted from the timing generation circuit 16.
A shift register ■9 generates clocks in the order of
- the color signals R, G supplied to C;

A buffer 20 that outputs B, a line memory 21 that holds the output of this buffer 20, and this line memory 21
The color signals R, G, and B held in the timing generation circuit 1
The buffer 22 outputs data based on the clock OE outputted from the clock OE outputted from the clock OE outputted from the clock OE outputted from the clock OE outputted from the buffer 22 outputted from the clock OE outputted from the clock OE outputted from the clock OE outputted from the buffer 22 outputted from the clock OE outputted from the clock OE outputted from the clock OE outputted from the clock OE outputted from the clock OE outputted from the buffer 22 that outputs the output based on the clock OE outputted from the clock OE outputted from the clock OE outputted from the clock OE outputted from the clock OE outputted from the clock OE outputted from the clock OE outputted from the clock OE outputted from the clock OE outputted from the clock OE.

Note that the clock SCK is obtained by equally dividing the image display period during the horizontal scanning period by the number of pixels in the horizontal direction (480), and the clock OE is generated during the blanking period in synchronization with the horizontal scanning synchronization signal. It is something that is generated.

Outputs D1 to D480 of the X driver 18 are supplied to each column electrode 23a of the liquid crystal panel 23, respectively. This liquid crystal panel 23 includes a plurality of pixels 24 connected to the column electrode 23a and a row electrode 21b orthogonal to the column electrode 23a, and arranged in a matrix in the horizontal and vertical directions.
It is equipped with Then, the row electrode 23b to which the signal is supplied
The pixel 24 connected to the pixel 24 performs display corresponding to the output Di-D 480 of the X driver 18.

Here, a signal is selectively supplied to the row electrode 23b by the output Lo-L 439 of the shift register 26 constituting the Y driver 25. That is, the shift register 2B is set to Lo in odd fields based on the clock HCK generated twice from the timing generation circuit 1B in synchronization with the horizontal scanning synchronization signal.

L2. In the order of L4..., Ll, L3 . The signals are generated in the order of L5, . . . , and each row electrode 23b is interlacedly scanned in the vertical direction.

Therefore, each pixel 24 has color signals R, G, sampled by the X driver 18 for the number of pixels in the horizontal direction,
B is supplied so as to be scanned in the vertical direction every horizontal scanning period, and an image is displayed.

In this case, the shift register 2B receives a gate pulse G from the timing generation circuit 1B in response to the clock HCK.
In the state where E is generated, an output signal Lo is applied to each row electrode 23b.
, L2. L4...or LL.

L3. Clear pulse FCL generated in synchronization with the vertical blanking period as well as generating L5...
Cleared based on.

Here, as shown in FIG. 7, the pixel 24 includes a thin film transistor (hereinafter referred to as TPT) 24a in which a control electrode is connected to a row electrode 23b and one controlled electrode is connected to a column electrode 23a, and this T F It is composed of a liquid crystal 24b and a capacitor 24c connected in parallel between the other controlled electrode of T 24a and a common electrode. When a signal is supplied from the Y driver 25 to the row electrode 23b, the TPT 24a is turned on, and the output of the X driver 18 is supplied to the liquid crystal 24b and the capacitor 24c. In this case, the signal level supplied to the liquid crystal 24b is held constant during at least one vertical scanning period by the capacitor 24e.

FIG. 8 is a timing chart showing the operation of the above-mentioned liquid crystal color television receiver. That is, when the clock SCK is supplied to the shift register 19, outputs Sl, S2, S3, . . . are sequentially generated in synchronization with the rising edge of the clock SCK. Now, assuming that the vertical timing signal vP is at L (low) level and color signals R, G, and B are supplied to signal lines a-C, respectively, the output SL of the shift register 19,
S2. St...... allows color signals to be R, G, B,
R, G, B, . . . are sequentially sampled in the order and stored in the line memory 21.

When sampling for one horizontal pixel is completed, the clock OE generated during the horizontal blanking period becomes H (high) level, and the contents of the line memory 21 are transferred via the buffer 22 to the outputs D1 to D1 of the X driver 18. D4
The signal 80 is supplied to each column electrode 23a of the liquid crystal panel 3 at the same time.

On the other hand, when the shift register 26 of the Y driver 25 is supplied with the gate pulse GE, its output is changed.

- H any one of L439 (Lo in Figure 8)
level. Then, all the T P T 24a constituting the 480 pixels 24 in the first row in the horizontal direction are turned on, and liquid crystal display in the first row in the horizontal direction is performed.

After that, when clock HCK is generated twice, clock OE becomes L level, and shift register 2B outputs Lo.
is set to L level and outputted, and 2 is set to H level. However, at this point, since the gate pulse GE has not been generated, the output signal 2 remains at the L level.

Then, the X driver 18 samples the color signal for one horizontal pixel based on the clock SCK, and the liquid crystal display on the third horizontal row is performed in synchronization with the clock OE and gate pulse GE. By repeating the operation for 220 lines, the image for one field is displayed.Next, the vertical timing signal vP goes to H level in synchronization with the vertical scanning synchronization signal, and the color switching circuit 17
The switches 17a to 17c are switched, and the signal lines a to
Color signals B, R, and G are supplied to C, respectively.

By the way, in the liquid crystal panel 23 having about 440 horizontal lines as described above, as shown in FIG. 9, the odd field OIl of the television signal.

0m+1, Oi+2... signals and even fields Em, Ea++1, En++2
By alternately supplying the signals .

However, for example, in an NTSC television signal, the number of horizontal scanning lines in one frame is 525, so in the liquid crystal panel 23 having 440 horizontal lines, 1 frame has 525 horizontal scanning lines.
This results in a 6.2% hidden portion. Also, P.A.
In L format television signals, the number of horizontal scanning lines in one frame is generally 625, so the liquid crystal panel 2
3, a non-display portion of about 30% will occur.

That is, unlike a cathode ray tube, the number of horizontal lines in the liquid crystal panel 23 is fixed, so for example, in a liquid crystal panel whose number of horizontal lines is set to correspond to the number of horizontal scanning lines in the NTSC system, the number of horizontal scanning lines is fixed. 1 compared to the NTSC system
If 100 more PAL television signals are displayed per frame, a problem arises in that the number of non-displayed portions increases and good display cannot be achieved.

(Problems to be Solved by the Invention) As described above, in conventional image display devices using liquid crystal panels, it is difficult to display all television signals transmitted using different horizontal scanning line numbers. The problem is that it cannot be done.

Therefore, the present invention has been made in consideration of the above circumstances, and provides an extremely good image display that can correspond to the display of television signals transmitted by a plurality of television systems having different numbers of horizontal scanning lines in one frame. The purpose is to provide equipment.

[Structure of the Invention] (Means for Solving the Problems) That is, an image display device according to the present invention has an image display device in which a plurality of pixels are arranged in a matrix in the horizontal and vertical directions. The present invention is intended for displaying an image by supplying a television signal sampled every minute in a vertical scanning manner every horizontal scanning period of the television signal.

Then, interlaced scanning and line scanning are performed every predetermined number of horizontal scanning lines of one field of the first television signal transmitted by a television system in which the number of horizontal scanning lines of one frame is greater than the number of pixels in the vertical direction. A television system in which the number of horizontal scanning lines of one frame approximately corresponds to the number of pixels in the vertical direction, and a first television signal outputted from the scanning switching means; and a selection means for selecting a second television signal to be transmitted and displaying an image.

(Function) According to the above configuration, for the horizontal scanning lines of one field of the first television signal transmitted by the television system in which the number of horizontal scanning lines of one frame is greater than the number of pixels in the vertical direction, A second television transmits a signal in which interlaced scanning and line sequential scanning are performed alternately every predetermined number of lines, and a television system in which the number of horizontal scanning lines of one frame approximately corresponds to the number of pixels in the vertical direction. Since the image display is performed by selecting the television signal and the television signal, it becomes possible to display an image of television signals transmitted by multiple television systems with different numbers of horizontal scanning lines in one frame. .

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, the same parts as in FIG. 6 are indicated by the same symbols, and only the different parts will be described here. That is, by changing the function of the Y driver 27 that sequentially scans each pixel 24 of the liquid crystal panel 23 in the vertical direction,
The difference from the conventional method is that control is given to scanning in the vertical direction.

In this case, the liquid crystal panel 23 has a vertical pixel number corresponding to the image display of the television signal transmitted by the NTSC system, and the number of horizontal scanning lines is 625, which corresponds to the television signal transmitted by the PAL system. , the number of horizontal scanning lines is 525
Television signals transmitted using the original NTSC system,
The case where an image is displayed will be explained as an example.

That is, the Y driver 27 switches the switch 28 to the power supply Vce side when a PAL television signal is supplied, and switches the switch 28 to the ground side when an NTSC television signal is supplied, thereby controlling the vertical direction of each pixel 24. The scanning in the directions is controlled in different ways so that images of both types of television signals can be displayed satisfactorily.

FIG. 2 shows details of the Y driver 27. 29 in the figure is a clock H synchronized with the horizontal scanning synchronization signal.
This is an input terminal to which CK is supplied, and is a clock input terminal CK of a shift register 30 with a 5-bit output.

A clock input terminal CK of a D-type flip-flop circuit (hereinafter referred to as D-FF circuit) 32 via a NOT circuit 31
and one input terminal of the NAND circuit 83, respectively. In addition, 34 in the figure is an input terminal to which the gate pulse GE is supplied, and a shift register 35 with 220 stage outputs.
is connected to the gate pulse input terminal GI of.

Further, reference numeral 36 in the figure denotes an input terminal to which the frame pulse FP is supplied, which is connected to one input terminal of each of the NAND circuit 37 and the OR circuit 38, respectively.

Each output terminal of the NAND circuit 37 and the OR circuit 38 is connected to a re-input terminal of an AND circuit 39, respectively. Further, 40 in the figure is an input terminal to which the clear pulse FCL is supplied, and the input terminal 40 is connected to the shift register 30, 35 and D-FF.
Each is connected to each clear input terminal CL of circuit q2.

Here, 41 in the figure is an input terminal to which a pulse ST generated at the start of display for each vertical synchronization signal is supplied. This input terminal 41 is connected to the input end of the shift register 35 and also to one input end of the OR circuit 42 . Further, numeral 43 in the figure is an input terminal to which the power supply level Vcc or ground level selected by the switch 28 is supplied, and is connected to one input terminal of the NAND circuit 44.

Here, the third output terminal QC of the shift register 30 is connected to the NAND circuit 37, 44 and the OR circuit 3.
8, respectively. Also,
The output terminal of the NAND circuit 44 is connected to the other input terminal of the NAND circuit 33. And this NAND circuit 3
The output terminal of No. 3 is connected to the clock input terminal CK of the shift register 35.

Also, the fifth output terminal QE of the shift register 30
is connected to the input end of the D-FF circuit 32, and the output end Q of this D-FF circuit 32 is connected to the other input end of the OR circuit 42. And this OR circuit 4
The output terminal of 2 is connected to the input terminal of the shift register 30.

Here, in the shift register 30, since the pulse ST becomes H level at the start of display, the input end becomes H level. Then, the shift register 30 sets the output terminal Q^ to H level in synchronization with the rising edge of the clock HCK. Then, at the next rise of the clock HCK, the pulse ST goes low.
Therefore, the output terminal QA becomes the L level, and the output terminal QB becomes the H level instead. Thereafter, the shift register 30 repeats the shift operation in synchronization with the clock HCK until its output terminal QB becomes H level.

Then, when the output terminal QE of the shift register 30 becomes H level, the H level output is latched into the D-FF circuit 32 at the falling edge of the clock HCK.

Therefore, the input end of the shift register 30 becomes H level again, the output end QA becomes H level, and the same operation is repeated thereafter. Here, the above operation of the shift register 30 is continued until a clear pulse FCL is generated at the end of vertical scanning.

Therefore, the H level is supplied to the NAND circuit 44 at the 3rd H from the start of the display, and thereafter the H level is supplied at the 5th H. Therefore, the switch 28 is now connected to the power supply Vce side, that is, the input terminal 431
: If H level is supplied, the NAND circuit 44
After the display starts, the output is 3H, 8H, 13H, 18H.
. . . becomes L level for each period, and becomes H level for other periods.

While the output of the NAND circuit 44 is at L level, the clock obtained by inverting the clock HCK is not supplied to the clock input terminal CK of the shift register 35 due to the action of the NAND circuit 33, so that the shift register 35 performs a shift operation. I won't do it. In other words, the shift register 35
is 3H after the start of display.

8H, 13H, 18H, . . . no shift operation is performed.

Further, the shift register 35 is brought into operation by the pulse ST being supplied to the input end, and
Every time the gate pulse GE is supplied to the gate pulse input terminal Gl, any one of the output terminals Qo-Q219 is set to H level. Furthermore, if the output terminal Qo of this shift register 35 is at H level, for example,
In synchronization with the output of the NAND circuit 33, the output terminals Qo, Ql,
The H level output is sequentially shifted in the order of Q2...

Here, the output terminals Qo to Q 219 of the shift register 35
is an output switching circuit 45 consisting of 220 switches.
is supplied to This output switching circuit 45 is switched and controlled by the output of the AND circuit 39, and when the output of the AND circuit 39 is at H level, Q □ -h L
O Ql → L2 Q2 → L4 Q 219 → L438, and when the output of the AND circuit 39 is at L level, it is switched as follows: Qo −+LI Ql → L3 Q2 → L5 Q219 → L439.

Therefore, the output of the AND circuit 39 is determined by the frame pulse FP and the output of the output terminal QC of the shift register 30. First, the frame pulse FP is at H level,
That is, in the case of an odd field, the output of the OR circuit 38 is at H level, so one input terminal of the AND circuit 39 is at H level. At this time, if the output terminal QC of the shift register 30 is at the L level, the output of the NAND circuit 37 is at the H level.
Since the signal is at the high level, the AND circuit 39 outputs the H level.

Next, as mentioned above, the output terminal Q of the shift register 30
When C goes to H level once every 5H, the output of NAND circuit 37 goes to L level, so the output of AND circuit 39 goes to L level. In other words, if the frame pulse FP is at H level, the output of the AND circuit 39 is
It is the inverted output of the output terminal QC of 0. Furthermore, when the frame pulse FP is at the L level, that is, in an even field, the output of the NAND circuit 37 is at the H level.
The output of the AND circuit 39 is equal to the output of the output end QC of the shift register 30.

Therefore, in the odd field, the output of the AND circuit 39 is at the L level at the 3H, 8H, 13H, 18H, . . . , and at the H level during the other periods. Therefore, in odd fields, the output switching circuit 45
Normally, as mentioned above, QO→L.

Ql → L2 Ql → L4 Q　219→L438 Although it is switched so that it becomes 3H, 8H.

13H, 18H...In the eyes, QO-+LI Ql 4L3 Ql → L5 Q　219→L439 It can be switched so that

On the other hand, in the even field, the output switching circuit 45 is normally switched so that Qo → LI Ql → L3 Ql → L5 Q 219 → L489, contrary to the above, but 3H, 8H.

13H, 18H...In the eyes, QO→L.

Ql → L2 Ql → L4 Q　219→L438 It can be switched so that

Therefore, in an odd field, a gate pulse is normally output to the odd row electrodes 23b, 3H28H, 13
H, 18H... For eyes, even numbered row electrodes 23
A gate pulse is now output to b.

In addition, in an even field, normally the even numbered row electrode 2
Gate pulse is output to 3b, 3H, 8H.

At 13H, 18H, . . . , gate pulses are output to odd-numbered row electrodes 23b.

In short, the PAL system, which has a larger number of horizontal scanning lines per frame than the NTSC system, uses a liquid crystal panel 23 that has the number of pixels in the vertical direction corresponding to the number of horizontal scanning lines per frame of the NTSC television signal. In order to display a television signal, switching to line sequential scanning is performed without performing interlaced scanning once every 5H, in other words, interlaced scanning and line sequential scanning are alternately performed every predetermined number of horizontal scanning lines. I have to.

Therefore, using a 440-line liquid crystal panel 23,
It is possible to display one field of 264 lines of television signals at the same non-display rate (16.2%) as the non-display rate of the NTSC television signal, making it possible to display a good image.

Here, FIGS. 3 and 4 are timing diagrams showing the operation of each part of the Y driver 27 shown in FIG. 2 in odd and even fields, respectively. That is, after the display start pulse ST is generated, the horizontal drive pulse HD begins to be generated. Then, for each horizontal drive pulse HD, the shift register/star 30 generates an H level in the order of its output terminals QA to QB, and when the output terminal QC becomes an H level, the output of the NAND circuit 44 becomes an L level. .

Therefore, the outputs of the NAND circuit 33 are 3H and 5H.

13H, 18H...The eyes are missing. Furthermore, the output of the shift register 35 is not shifted to the shift door knob for each IH, but is output from the output terminals Ql, Q5. Q9...
..., the H level continues for the 2H period. In the odd field, since the frame pulse FPIJ<H level, the output switching circuit 45 switches as follows: QO4LO Ql → L2 Q2 → L4 Q219 → L438, but the output end QC is set to H level in the shift register 30. As explained above, the IH off period output switching circuit 45 is switched to Qo - "LI Ql → L3 Q2 → L5 Q219 → L439, and a pulse is output from L3. It becomes like this.

As a result, Lo, L2. Instead of interlaced scanning in which a gate pulse is generated every other line as in L4..., Lo, L2, L3
.

L4... Don't skip over the 3rd line, write the 4th line, then the 5th line, the 7th line, etc.
I started writing...

Also, even in the even field, the operation is the same as in the odd field, except that the switching operation of the output switching circuit 45 is reversed.
LL, L3. L4. L5. The 5th line is scanned after the 4th line like L7°L9..., and then the 6th line, the 8th line, etc. are scanned.

FIG. 5 shows the writing positional relationship between the television signal and each line of the actual liquid crystal panel 23, as described above. It can be seen that in each field, interlaced scanning is stopped every five lines and line sequential scanning is performed.

Here, in the above embodiment, the interlaced scanning is stopped once every 5 lines, but this may be done, for example, once every 4 lines or once every 6 lines. All that is required is to stop the scanning so that interlaced scanning and line sequential scanning can be performed alternately.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As detailed above, according to the present invention, an extremely good image can be produced that can support the display of television signals transmitted by a plurality of television systems in which the number of horizontal scanning lines in one frame is different. A display device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the image display device according to the present invention, FIG. 2 is a block diagram showing the main parts of the embodiment in detail, and FIGS. 3 and 4 are the same embodiment. FIG. 5 is a timing diagram for explaining the operation of the example. FIG. 5 is a diagram for explaining the write operation of the example. FIG. 6 is a block configuration diagram showing a conventional image display device. FIG. 7 is a detailed diagram of the pixels. FIG. 8 is a timing diagram for explaining the operation of the conventional image display device, and FIG. 9 is a diagram showing the horizontal scanning line processing means of the conventional image display device. 11-13...Input terminal, 14...Polarity inversion circuit,
15... Polarity switching circuit, IB... Timing generation circuit, 17... Color switching circuit, 18... X driver,
19...Shift register, 20...Buffer, 21
...Line memory, 22...Buffer, 23...
Liquid crystal panel, 24...pixel, 25...Y driver, 2B...shift register, 27...Y driver, 28...switch, 29...input terminal, 30...
・Shift register, 31... Nozuto circuit, 32...
D-FF circuit, 33... NAND circuit, 34... Input terminal, 35... Shift register, 3B... Input terminal, 37... NAND circuit, 3B... OR circuit, 39
...AND circuit, 40.41...Input terminal, 42.
...OR circuit, 43...input terminal, 44...NAND circuit, 45...output switching circuit. Applicant's agent Patent attorney Takehiko Suzue ()m □ LO (Om
)Em −=======L 1 (1:m
) Om++ -11, Yaeya ==
=L2 (Om+ +) Figure 5 Figure 7 SC to vP L□ I wealth t of signal 41a
RFigure 8

Claims (1)

[Claims] An image display device having a plurality of pixels arranged in a matrix in the horizontal and vertical directions is scanned vertically with a television signal sampled by the number of pixels in the horizontal direction every horizontal scanning period of the television signal. One field of a first television signal transmitted by a television system in which the number of horizontal scanning lines in one frame is greater than the number of pixels in the vertical direction of the image display device. scanning switching means for alternately performing interlaced scanning and line sequential scanning for every predetermined number of horizontal scanning lines; a first television signal output from the scanning switching means; and the number of horizontal scanning lines in one frame. a second television signal transmitted by a television system that substantially corresponds to the number of pixels in the vertical direction of the image display, and a selection means for selectively supplying the image display to display an image; An image display device comprising: