JPH0836370A - Color display device - Google Patents

Abstract

PURPOSE:To synthesize color images which are perfectly matched by optically superposing respective single color images of three sheets of display panels. CONSTITUTION:The respective display panels 1R, 1G, 1B have plural pixels which are arranged like deltas and are offset arranged by rows, perpendicular driving circuits for successively and selectively select one line-component of the pixels and horizontal driving circuit s for writing one-line component of video signals in the one-line component of the pixels. A timing generator 3 offset controls the input timing of start pulses in correspondence with the offset arrangement of the pixels very time the respective rows of the pixels are successively selected. Three sheets of the display panels 1R, 1G, 1B are divided to forward or backward display panels displaying forward or backward single color images with respect to the row direction and the timing generator 3 reverses the offset control of the start pulses according thereto.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color display device. More specifically, red displayed on the three display panels,
The present invention relates to a color display device such as a projector that reproduces a color image by optically superposing green and blue single color images.

[0002]

2. Description of the Related Art Conventionally, a single-panel type projector that projects a color image by using one full-color liquid crystal display panel and a three-panel projector that projects a color image by optically overlapping three monochromatic liquid crystal display panels. Was known. As shown in FIG. 8, a single-panel type projector uses a color display panel in which innumerable pixels are arranged in delta in order to improve image quality such as resolution. As shown in the figure, the pixel array is composed of a set of three primary color pixels R, G, B arranged in a delta arrangement. A delta array of pixel arrays includes linearly aligned pixel rows and zigzag interdigitated pixel columns. In the illustrated example, seven pixel rows and eight pixel columns are shown. In the delta arrangement, the pixels R, G,
Bs are arranged in order at a predetermined pitch. However, in the odd-numbered rows and the even-numbered rows, the sets of pixels R, G, and B are offset from each other by 1.5 pitches. Therefore, any three pixels (shown by hatching) located at the vertices of an equilateral triangle are always a combination of R, G, and B, which is called a delta arrangement. This delta arrangement can improve resolution and provide smooth color display. However, if the delta arrangement is adopted, each pixel row has a zigzag complicated shape.
For example, focusing on the third column, the seven pixels R are commonly connected by one signal line from the first row to the seventh row. Since the pixels R are arranged in shifts by 1.5 pitches between the odd-numbered rows and the even-numbered rows, the pixel rows are intricately zigzag.

[0003]

On the other hand, in the three-panel type projector, since there is no difference in resolution due to the pixel arrangement, a display panel having a pixel array of stripe arrangement has been conventionally used. In this stripe arrangement, individual pixels are arranged in a simple grid pattern. As described above, the display panels having the pixel arrays of different configurations have been used in the conventional single-plate type projector and three-plate type projector, respectively. However, when considering mass production, it is preferable to use a display panel having a common pixel array configuration for both the single-plate type projector and the three-plate type projector from the viewpoint of cost reduction of parts. Therefore, it has been attempted to employ a display panel having a pixel array like a delta array also in a three-plate type projector. However, unlike the single plate type, in the three plate type, all the pixels of each display panel are assigned the same color. However, when three delta array monochromatic display panels are combined, it is a problem to be solved that drive timings of the respective display panels are matched with each other due to the asymmetry of the pixel array as described above.

[0004]

In order to solve the above-mentioned problems of the conventional technique, the following two means are taken. That is, the color display device according to the first aspect of the present invention is, as a basic configuration, three display panels to which each of the three primary colors is assigned, and a signal source that supplies a video signal of each primary color corresponding to each display panel. And a timing means for controlling the drive of each display panel in synchronization with each other, and the color images are reproduced by optically superimposing the monochromatic images displayed on the three display panels. Each display panel has a plurality of pixels arranged in a delta pattern and arranged in an offset manner for each row, a vertical drive circuit for sequentially selecting one row of pixels, and a pixel selected in response to a start pulse input from the timing means. And a horizontal drive circuit for writing one line of the video signal in one row. Characteristically, the timing means offset-controls the input timing of the start pulse in accordance with the offset array of pixels each time each row of pixels is sequentially selected.

Preferably, the display panel has pixels which are arranged in an offset manner between odd rows and even rows. On the other hand, the timing means relatively controls the input timing of the start pulse between the odd-numbered rows and the even-numbered rows. Further, preferably, the three display panels are divided into a normal display panel for displaying a normal single color image and a reverse display panel for displaying a reverse single color image in the row direction. In this case, the timing means reverses the offset control of the start pulse input to the reverse display panel with respect to the offset control of the start pulse input to the normal display panel. More preferably, the timing means presets a relative offset to a start pulse input to both display panels according to a relative delay in the start of the writing operation between the normal display panel and the reverse display panel. To do.
In addition, preferably, each display panel includes a pixel electrode, a counter electrode facing the pixel electrode with a predetermined gap, a liquid crystal held in the gap, a vertical driving circuit and a horizontal driving circuit connected to the pixel electrode. And an active matrix liquid crystal display panel having a plurality of pixels each composed of a switching element connected to.

According to the second aspect of the present invention, the color display device has, as a basic configuration, three display panels to which each of the three primary colors is assigned and a video signal of each primary color corresponding to each display panel. And a timing means for controlling the drive of each display panel in synchronization with each other, and reproduces a color image by optically superimposing the single color images displayed on the three display panels. Each display panel has a plurality of pixels arranged in rows, a vertical drive circuit for sequentially selecting one row of pixels, and a row of the video signal for one row of pixels selected in response to a start pulse input from the timing means. And a horizontal drive circuit for sequentially writing one line.
The three display panels are divided into a normal display panel and a reverse display panel. In the normal display panel, the horizontal drive circuit sequentially writes in the forward direction of the row in response to the start pulse to display a normal monochrome image. In the reverse display panel, in response to the start pulse, the horizontal drive circuit sequentially executes writing along the reverse direction of the row to display a reverse monochrome image. Characteristically, the timing means applies a relative offset in advance to the start pulse input to both display panels according to the relative delay of the sequential writing start occurring between the normal display panel and the reverse display panel. I have to.

[0007]

According to the present invention, a color display device such as a three-plate type projector is constructed by using three monochromatic display panels each having a delta array-like pixel array. In the delta arrangement, the pixels connected to the same signal line are displaced by 1.5 pitches between the odd row and the even row. Therefore, an offset time corresponding to an offset arrangement of 1.5 pitches is added to the start pulse for instructing writing of one line of the video signal in the odd-numbered row and the even-numbered row. Further, in the three-plate type projector, a system in which a normal display panel and a reverse display panel in which scanning directions of sequential writing by a horizontal drive circuit are different from each other is generally combined is generally used because of an internal optical arrangement. At this time, the shift directions of the video signals are opposite in the display panels having different scanning directions. Therefore, the timing means reverses the offset control of the start pulse input to the reverse display panel with respect to the offset control of the start pulse input to the normal display panel. When a three-panel type projector or the like is configured by combining display panels having different writing scanning directions, a delay occurs due to data transfer in the horizontal drive circuit from the generation timing of the start pulse to the actual writing of the video signal. Since this delay amount differs between the forward scanning and the backward scanning, the generation timing of the start pulse is offset in advance according to the scanning direction. With the above configuration, the three display panels can write the video signals in perfect synchronization with each other, so that it is possible to reproduce a color image without color misregistration.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing the basic configuration of a color display device according to the present invention. As shown in the figure, the color display device includes three display panels 1R, 1G and 1B to which the three primary colors are assigned. A red image is assigned to the display panel 1R,
A green image is assigned to G, and a blue image is assigned to the display panel 1B. In addition, each display panel 1R,
An R driver 2R, a G driver 2G, and a B driver 2B are provided as signal sources for supplying video signals of respective primary colors corresponding to 1G and 1B. Furthermore, each display panel 1R,
A single timing generator (TG) 3 is provided as timing means for controlling the driving of 1G and 1B in synchronization with each other. With this configuration, the three display panels 1
The color images are reproduced by optically superposing the monochromatic images displayed on the R, 1G, and 1B. Such a configuration can be applied to, for example, a three-plate type projector.

Each display panel 1R, 1G, 1B has the same pixel array. For example, paying attention to the display panel 1R, the individual pixels R are arranged in a delta pattern and are arranged in an offset arrangement for each row. Although not shown, each display panel incorporates a vertical drive circuit and a horizontal drive circuit. The vertical drive circuit sequentially selects one row of pixels. On the other hand, the horizontal drive circuit writes one line of the video signal in one row of the selected pixel in response to the start pulse input from the timing generator 3. As a feature of the present invention,
The timing generator 3 offset-controls the input timing of the start pulse in accordance with the pixel offset array each time each row of pixels is sequentially selected. Specifically, each display panel has pixels that are arranged relatively offset between the odd-numbered rows and the even-numbered rows, and the timing generator 3 changes the input timing of the start pulse between the odd-numbered rows and the even-numbered rows. Offset control is performed relatively.

The display panel employed in the present invention has a structure capable of switching between normal display and reverse display on the left and right sides of the screen. This left-right reversal function is necessary when, for example, three display panels are applied to a light valve of a projector. The projector is composed of three display panels to which each of the three primary colors is assigned and a common magnifying projection lens system. Each display panel functions as a light valve for each color system of R, G, and B. Each display panel displays a single color image decomposed into R, G and B. At the same time, R,
Illumination light of G and B enters. After the monochromatic transmitted light of each display panel is combined by a dichroic prism or a dichroic mirror, this combined color image is enlarged and projected on a screen by a projection lens system. In the optical system of this projector, monochromatic images are combined after repeating reflection inversion several times. The number of reflection inversions for each color system varies depending on the arrangement structure of the optical system. Therefore, in order to obtain a matched color image, it is necessary to reversely display a specific monochrome image in advance. In the example of FIG. 1, the red image and the blue image are displayed in the normal rotation, while the green image is displayed in the reverse rotation.

That is, in this embodiment, the three display panels are divided into the normal display panels 1R and 1B and the reverse display panel 1G. In the normal display panels 1R and 1B, in response to the start pulse, the horizontal drive circuit executes sequential writing scanning along the forward direction of the row to display a normal monochrome image. On the other hand, in the reverse display panel 1G, in response to the start pulse, the horizontal drive circuit sequentially performs the writing scan along the reverse direction of the row to display the reverse monochrome image. In this case, the timing generator 3 includes the normal display panels 1R and 1B and the reverse display panel 1G.
Depending on the relative delay in the start of sequential writing between the two, a relative offset is applied in advance to the start pulse input to both. As a result, the leading pixel R1 of the normal display panel 1R and the leading pixel G of the reverse display panel 1G.
1 is written at a timing completely synchronized with each other.

In the normal rotation display panel and the reverse rotation display panel, the relationship of the pixels relatively offset in the odd rows and the even rows is reversed. Corresponding to this, the timing generator 3 reverses the offset control of the start pulse input to the reverse display panel with respect to the offset control of the start pulse input to the normal display panel.

FIG. 2 is a block diagram showing a specific configuration of each display panel shown in FIG. The three display panels have the same structure and are all shown as the display panel 1. The display panel 1 includes a pixel array section 11 and a peripheral circuit section. The pixel array unit 11 includes a set of single color pixels arranged in a delta pattern. Similar to the full-color display panel, they are arranged in a delta arrangement, but include only pixels of a single color instead of the three primary colors. Pixel array section 11
Has a delta-like arrangement, and therefore linearly aligned pixel rows and zig-zag intricate pixel columns are defined. The peripheral circuit section includes a vertical drive circuit 12 and a horizontal drive circuit 13. The vertical drive circuit 12 sequentially selects each pixel row according to the vertical start pulse VST input from the external timing generator 3. The horizontal drive circuit 13 similarly supplies the video signal SIG to the pixels of one row in response to the horizontal start pulse HST input from the timing generator 3 every horizontal period.
Write one line. The video signal SIG is supplied from the external driver 2. At this time, the horizontal drive circuit 13
Has a left-right inversion function and can switch the writing scanning of the video signal between the forward direction and the reverse direction.

As shown in the drawing, each pixel column arranged in zigzag is connected to the horizontal drive circuit 13 via a corresponding signal line Y. The horizontal drive circuit 13 outputs a horizontal start pulse HST
Sequentially sampling each signal line Y according to
G will be distributed. Now, pay attention to the Jth column, the Kth row, and the K + 1th row. With respect to the signal line Y, the pixel J / K located in J column and K row is located on the right side, and the pixel J / K + 1 located in J column and K + 1 row is located on the left side. That is, the pixels connected to the same signal line Y have an offset of 1.5 pixels in the odd and even rows. When the write scan of the horizontal drive circuit 13 is performed in the forward direction (from left to right), the video signal SIG written in the pixel in the Kth row is delayed by 1.5 pixels compared with the video signal written in the pixel in the K + 1th row. The input signal is input from the signal line Y. On the other hand, in the case of reverse scanning (from right to left), the pixel in the Kth row is 1.5 pixels faster than the pixel in the K + 1th row. Accordingly, the sampling timing of the signal line Y is relatively shifted row by row in order to offset the writing timing of the video signal. By the way, the sampling timing of the signal line Y is the horizontal start pulse HST input from the timing generator 3 every horizontal period.
Is specified by the multistage data transfer of the shift register. Therefore, in order to add a desired offset to the sampling timing of the signal line Y for each row, an offset may be provided at the input timing of the HST.

FIG. 3 shows the horizontal start pulse HS described above.
7 is a timing chart showing T offset control. (A) shows the case of normal rotation display, and (B) shows the case of reverse rotation display. In the case of normal display, the horizontal start pulse HST (K + 1) corresponding to the K + 1th row is 1.5 compared to the horizontal start pulse HST (K) corresponding to the Kth row.
It is delayed corresponding to the offset for pixels. On the other hand, in reverse display, the horizontal scanning direction is reversed, so HST (K +
Compared to 1), HST (K) is delayed by a time corresponding to the offset of 1.5 pixels. Thus, when a three-panel projector or the like is configured using a display panel having a delta-arrangement-like pixel array, the horizontal scanning direction is different in each display panel, so that the start pulse input to the normal display panel is different. The offset control of the start pulse input to the reverse display panel is reversed with respect to the offset control. In the delta arrangement shown in this embodiment, the pixel-by-row offset is 2H cycles for each line (1H represents one horizontal period). However, the present invention is not limited to this, and even if the pixel array has an offset cycle of 3H or more, it can be easily dealt with by adding an offset according to the pixel array to the input timing of the HST.

Obviously, in the normal display and the reverse display, the position of the leading pixel is different when the video signal is written in the pixels for one row. That is, the head pixel is located on the left side of the display panel in the normal display, whereas the head pixel is located on the right side of the display panel in the reverse display. Due to the structure of the horizontal drive circuit incorporated in each display panel, a relative delay occurs depending on the scanning direction from the input of the start pulse HST to the actual writing of the first pixel. In view of this point, an offset is added to the input timing of the HST in advance according to the scanning direction. By doing so, it becomes possible to synchronize writing to the leading pixel between the respective display panels.
FIG. 4 shows the position of the leading pixel in the normal display by hatching. As shown in (A), when the odd-numbered row precedes the even-numbered row, the leading pixel is located in the odd-numbered row. On the other hand, as shown in (B), when the even-numbered row precedes the odd-numbered row in time, the leading pixel is located in the even-numbered row. A predetermined offset is added to the input timing of the HST between the normal display panel and the reverse display panel based on the leading pixel defined in this way. As will be understood from the figure, the leading pixel is a pixel in which the writing operation is performed relatively fastest with respect to the HST, and is not necessarily the first row.

FIG. 5 is a circuit diagram showing a more specific structure of the display panel shown in FIG. As shown in the figure, M signal lines Y and N gate lines X are arranged in a cross manner in the screen. A pixel is arranged at each intersection of the signal line Y and the gate line X. As shown in the figure, each pixel is a fine liquid crystal cell L.
It consists of a combination of C and a switching element. In this example, the switching element is composed of a thin film transistor Tr, the gate electrode of which is connected to the corresponding gate line X, the source electrode is connected to the corresponding signal line Y, and the drain electrode is located at one end of the corresponding liquid crystal cell LC. It is connected to the electrode.
The other end of the liquid crystal cell LC is composed of a counter electrode. Liquid crystal is held between the counter electrode and each pixel electrode to form an individual liquid crystal cell LC.

A vertical drive circuit 12 is provided at one end of each gate line X.
Are connected, and the gate pulse φ _V is sequentially output every horizontal period (1H) according to the vertical start pulse VST and the clock signal VCK supplied from the timing generator. In response to the gate pulse φ _V , the thin film transistor Tr becomes conductive and sequentially selects each pixel row.

A horizontal switch HS is provided at the upper end of each signal line Y.
The video line 14 is connected via W. The video line 14 receives the video signal SIG from an external driver. The horizontal switch HSW is the horizontal address circuit 1
Opening and closing are controlled by the sampling pulse φ _H sequentially output from 3a, the video signal SIG is sampled, and SIG is written in the pixel column in synchronization with the above-described sequential selection.
As can be understood from the above description, the horizontal address circuit 13
The combination of a and the horizontal switch HSW constitutes the horizontal drive circuit 13 shown in FIG. Horizontal address circuit 13a
Outputs a sampling pulse φ _H sequentially according to a horizontal start pulse HST and a clock signal HCK supplied from an external timing generator. The horizontal address circuit 13a is composed of a shift register and the like, and bidirectional scanning of the signal line Y is possible.

FIG. 6 shows a specific example of a horizontal address circuit having a bidirectional scanning function. As shown in the figure, the horizontal address circuit has a single shift register 40 and transfers a predetermined start pulse HST for each stage to perform dot sequential writing of pixels (not shown). The shift register 40 has a structure in which flip-flops FF having a pair of input terminals I and output terminals O are connected in multiple stages in a number corresponding to the total number of columns of pixels. The input / output terminals of each FF are sequentially connected via two data transfer paths 41.
In this example, M flip-flops are connected in multiple stages from FF _{1 in the first} stage to FF _{M in the} last stage. The shift register 40 of this example is bidirectional and can perform forward transfer and reverse transfer of data (HST) in a selectable manner. For this purpose, transfer gate elements A and B are respectively interposed between the input and output terminals of a pair of flip-flops located adjacent to each other. By selectively opening and closing the transfer gate elements A and B, the data transfer is controlled in the forward direction or the reverse direction to enable bidirectional point sequential writing of pixels. For example, one transfer gate element B is interposed between the input terminal of FF _{1 and} the output terminal of FF ₂ . Also, the output terminal O of FF ₁ and FF
_The other transfer gate element A is interposed between the _second input terminal I and the _second input terminal I. Similarly, transfer gate elements A and B are respectively interposed between the input and output terminals of the FFs adjacent to each other. When the transfer gate element A is opened and the transfer gate element B is closed, the start pulse HST is sent in the forward direction via the data transfer path 41. Conversely, when the transfer gate element A is closed and the transfer gate element B is opened, the start pulse HST changes the data transfer path 41.
Is sequentially sent in the reverse direction via. In this case, due to the structure of the horizontal address circuit, there is a time difference between the forward transfer and the reverse transfer from the input of HST to the output of the first sampling pulse. In the present invention, an offset is provided in advance in the input timing of the HST between the normal rotation display panel and the reverse rotation display panel according to this temporal difference.

FIG. 7 is a circuit diagram partially showing a specific configuration example of the horizontal address circuit shown in FIG. To explain the bidirectional transfer of data, only two flip-flops (first stage FF and second stage FF) and their associated transfer gate elements A and B are shown. All circuit elements are composed of thin film transistors (TFTs). Both the front FF and the next FF are composed of D-type flip-flops. Each D-type flip-flop is composed of first and second clocked inverters and a third inverter, and operates according to clock signals HCK and HCKX having mutually opposite phases, and converts the data input from the input terminal IN into clock signals. It is delayed by a half cycle and output to the output terminal OUT. The transfer gate elements A and B are each composed of a CMOS type transmission gate element. The transfer gate elements A and B are controlled by antiphase control signals T and TX input from the outside. When one control signal T is at high level and the other control signal T
When X is at low level, one transfer gate element A is opened and the other transfer gate element B is closed. Therefore, at this time, the data is supplied to the input terminal IN of the preceding stage FF after passing through the first transfer gate element A. Here, after the delay processing is performed by half a cycle of the clock signal, the output terminal O
Transfer from the UT to the input terminal IN of the next stage FF via the next transfer gate element A. In this way, the data is sequentially transferred in the forward direction. On the other hand, when the control signal T switches to the low level and the control signal TX switches to the high level,
One transfer gate element A is closed and the other transfer gate element B is
Opens. In this case, the data transferred from the reverse direction is supplied to the input terminal IN of the next-stage FF and subjected to a predetermined delay process, and then the output terminal OUT passes through the transfer gate element B and the input terminal of the previous-stage FF. Transferred to IN. The data output from the output terminal OUT after being subjected to the predetermined delay processing again reaches the next transfer gate element B.

[0022]

As described above, according to the present invention, a color display device such as a three-plate type projector is constructed by using three display panels each having a delta array-like pixel array. An offset for each row is added to the start pulse for horizontal writing input to each display panel. Also, an offset is provided for each horizontal scanning direction. Accordingly, there is an effect that a full-color image in which the normal image and the reverse image are perfectly aligned with each other can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a color display device according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a display panel incorporated in the color display device shown in FIG.

FIG. 3 is a timing chart for explaining the operation of the color display device according to the present invention.

FIG. 4 is a schematic diagram for explaining the operation of the color display device according to the present invention.

5 is a circuit diagram showing a more specific configuration example of the display panel shown in FIG.

6 is a block diagram showing a specific configuration example of the horizontal address circuit shown in FIG.

7 is a circuit diagram showing a more specific configuration example of the horizontal address circuit shown in FIG.

FIG. 8 is a schematic diagram showing a delta arrangement of a general pixel array.

[Explanation of symbols]

 1R display panel 1G display panel 1B display panel 2R R driver 2G G driver 2B B driver 3 timing generator 11 pixel array unit 12 vertical drive circuit 13 horizontal drive circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 9/31 B

Claims (6)

[Claims] 1. A three display panel to which each of the three primary colors is assigned, a signal source for supplying a video signal of each primary color corresponding to each display panel, and a timing means for synchronously controlling the drive of each display panel. It is a color display device that is equipped with, and reproduces a color image by optically superimposing the monochromatic images displayed on the three display panels. A plurality of pixels, a vertical drive circuit that sequentially selects one row of pixels, and a horizontal drive that writes one line of a video signal to one row of the selected pixels in response to a start pulse input from the timing means. And a timing circuit that controls the input timing of the start pulse in accordance with the offset array of the pixels each time each row of pixels is sequentially selected. Color display device according to claim. 2. The display panel has pixels which are arranged in offset relative to each other between an odd row and an even row, and the timing means sets an input timing of a start pulse between the odd row and the even row. The color display device according to claim 1, wherein offset control is relatively performed. 3. The three display panels are divided into a normal display panel for displaying a normal single color image and a reverse display panel for displaying a reverse single color image in the row direction, and the timing means is a normal display panel. The color display device according to claim 1, wherein the offset control of the start pulse input to the reverse display panel is reversed with respect to the offset control of the start pulse input. 4. The timing means preliminarily sets an offset relative to a start pulse input to both display panels according to a relative delay in the start of a writing operation occurring between the normal display panel and the reverse display panel. The color display device according to claim 3, wherein the color display device is set. 5. Each display panel comprises a pixel electrode, a counter electrode facing the pixel electrode with a predetermined gap therebetween, a liquid crystal held in the gap, a pixel electrode, and a vertical drive circuit and a horizontal drive circuit. The color display device according to claim 1, wherein the color display device is an active matrix liquid crystal display panel including a plurality of pixels each having a switching element connected to a circuit. 6. Three display panels to which each of the three primary colors is assigned, a signal source for supplying a video signal of each primary color corresponding to each display panel, and a timing means for synchronously controlling the drive of each display panel. A color display device that reproduces a color image by optically superimposing the single-color images displayed on the three display panels, each display panel including a plurality of pixels arranged in rows, A vertical drive circuit for sequentially selecting one row, and a horizontal drive circuit for sequentially writing one line of the video signal to one row of the selected pixels in response to the start pulse input from the timing means. The three display panels are divided into a forward rotation display panel and a reverse rotation display panel. In the forward rotation display panel, the horizontal drive circuit sequentially writes in the forward direction of the row in response to the start pulse. On the other hand, in the reverse display panel, in response to the start pulse, the horizontal drive circuit sequentially executes writing in the reverse direction of the row to display the reverse single color image while displaying the reverse single color image. A color display device characterized in that a relative offset is applied in advance to a start pulse input to both display panels according to a relative delay in starting sequential writing between the display panel and the reverse display panel.