JP3312484B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device. More specifically, the present invention relates to a display device having pixels in a delta arrangement and having a screen capable of switching between normal display (for example, aspect ratio 4: 3) and wide display (for example, aspect ratio 16: 9). For more information,
The present invention relates to a technique for shaping border lines appearing at both left and right ends in normal display.

[0002]

2. Description of the Related Art The structure of a conventional display device will be briefly described with reference to FIG. As shown in the figure, there is provided a pixel array constituting a horizontally long screen which can be switched between wide display and normal display. The pixel array is composed of a set of three primary color pixels R, G, and B arranged in a delta arrangement. A pixel array in a delta arrangement includes linearly aligned pixel rows and zigzag interlaced pixel columns. In the schematic example of FIG. 8, seven pixel rows and fifteen pixel columns are shown. Note that an actual active matrix display device includes, for example, several hundreds to several hundreds of pixel rows and pixel columns. As shown in the figure, in the delta arrangement, pixels R, G, and B are sequentially arranged at a predetermined pitch along the row direction. However, in the odd-numbered rows and the even-numbered rows, pairs of pixels R, G, and B are offset from each other by 1.5 pitch. Therefore, any three pixels (indicated by hatching) located at the vertices of an equilateral triangle are always a combination of R, G, and B, which is the reason why the combination is called a delta arrangement. This delta arrangement can apparently improve the color resolution and provide a smooth color display. However, adopting the delta arrangement results in a complicated shape in which each pixel row is staggered. For example, focusing on the fourth column, a configuration in which seven pixels R are commonly connected by one signal line over the first to seventh rows is obtained. Since the pixels R are shifted by 1.5 pitches between the odd-numbered rows and the even-numbered rows, the pixels R form a zigzag pixel column. Similarly, the fifth column contains a pixel G that is staggered in each row. Further, the sixth column has a configuration in which pixels B are zigzag in each row.

When a display device having such a configuration is driven, each pixel row is sequentially selected for each horizontal period, and video signals for each of the three primary colors are written in a pixel column in synchronization with the sequential selection. At the time of wide display, a video signal is sequentially written to the first to fifteenth pixel columns over the entire screen. On the other hand, during normal display, the video signal is written to the fourth to twelfth pixel columns included in the center of the screen, and the first to third pixel columns included in the left part of the screen and the thirteenth pixel column included in the right part. A side black signal is written to the 14th to 14th pixel columns.

[0004]

FIG. 8 shows a normal display in which side black signals are written on the left and right sides of the screen. As described above, each pixel column is zigzag because of the delta arrangement, and is shifted by 1.5 pitch for each row. For this reason, the boundary between the left and right portions of the screen and the center portion has a zigzag shape of 1.5 pitches, so that both ends of the normal display do not appear sharply.

Next, another problem to be solved by the present invention will be described with reference to FIG. In a display device capable of switching between wide display and normal display, a structure capable of switching between normal rotation display and reverse rotation display on the left and right sides of the screen has been recently developed. This left-right inversion function is required, for example, when an active matrix type display device is applied to a light valve of a projector. The projector is composed of three display devices to which each of the three primary colors is assigned, and a common enlarged projection lens system. Each display device functions as a light valve for each of red, green, and blue color systems. Each display device decomposes the primary image into red, green, and blue components and displays it. At the same time, red, green, and blue illumination light is incident on each display device. The monochromatic transmitted light from each display device is synthesized by a dichroic prism or a dichroic mirror, and the synthesized full-color image is enlarged and projected on a screen by a projection lens system. In the optical system of this projector, the primary image is synthesized after repeating reflection inversion several times. The number of reflection inversions for each color system differs depending on the arrangement structure of the optical system. Therefore, in order to obtain a matched full-color image, it is necessary to reversely display a primary image of a specific color in advance. The example of FIG. 9 shows an example in which a red image (R) and a blue image (B) are displayed in a normal direction, while a green image (G) is displayed in a reverse direction.

However, when a normal display is displayed on a screen composed of a set of single-color pixels arranged in a delta pattern, the boundary lines appearing at the left and right ends have a zigzag shape as described above. Furthermore, when the number of pixels included in each row is all constant, the zigzag shape of the left and right boundary lines becomes asymmetric. Therefore, as shown in FIG. 9, the three primary color pixels R and R are located at the left and right ends between the normal display of red and blue and the reverse display of green.
There is a portion where G and B do not overlap. Therefore, there is a problem that an unnatural color tone appears on the left and right side lines of the RGB composite display.

[0007]

SUMMARY OF THE INVENTION In view of the above-mentioned problems in the prior art, it is a first object of the present invention to sharpen side lines at both ends of a screen when switching from wide display to normal display. Also, each of the red, green and blue color display devices is 3
A second object is to adjust the color tone of the side lines at both ends of the screen when switching from the wide display to the normal display in a configuration in which the RGB composite display is displayed by superimposing the images.

The following means have been taken to achieve the first object. That is, the display device according to the present invention includes, as a basic configuration, a pixel array unit that forms a horizontally long screen that can be switched between wide display and normal display, and a peripheral circuit unit that drives the pixel array unit. The pixel array section includes a set of three primary color pixels arranged in a delta, and defines linearly aligned pixel rows and zigzag pixel columns. The peripheral circuit section includes a vertical drive circuit for sequentially selecting each pixel row every one horizontal period, a horizontal drive circuit for writing a video signal to a pixel column in synchronization with the sequential selection, and a mask means for writing a side black signal to the pixel column. And As a feature of the present invention, a control unit connected to the peripheral circuit unit is provided, and controls the horizontal drive circuit at the time of wide display to write a video signal to a pixel column over the entire screen. On the other hand, at the time of normal display, the horizontal drive circuit and the mask means are controlled to write a video signal to a pixel row included in a part of the screen and to write a side black signal to a pixel row included in the rest of the screen. At this time, a video signal and a side black signal are alternately written into a specific pixel column located at the boundary between the two portions every one horizontal period, and a complicated zigzag boundary is shaped.

The following means have been taken to achieve the second object of the present invention. That is, the display device according to the present invention includes, as a basic configuration, a pixel array unit that forms a horizontally long screen that can be switched between wide display and normal display, and a peripheral circuit unit that drives the pixel array unit. . The pixel array section includes a set of single color pixels arranged in a delta fashion, defining a linearly aligned pixel row and a zigzag interlaced pixel column. The peripheral circuit section includes a vertical drive circuit for sequentially selecting each pixel row, a horizontal drive circuit for writing a video signal to a pixel column in synchronization with the sequential selection, and a mask means for writing a side black signal to the pixel column. As a feature of the present invention, a control unit connected to the peripheral circuit unit is provided, and controls the horizontal drive circuit at the time of wide display to write a video signal to a pixel column over the entire screen. On the other hand, at the time of normal display, the horizontal drive circuit and the masking means are controlled to write a video signal to a pixel column included in the center of the screen and to write a side black signal to a pixel column included in the left and right sides of the screen. At this time, the video signal and the side black signal are alternately written every one horizontal period for a predetermined number of pixel columns located at the boundary between the central portion and the left and right portions, and the left and right boundaries that are interleaved with each other are symmetrically shaped. I do. Preferably, the horizontal driving circuit is a normal display in which the video signal is sequentially written to the pixel column from left to right of the screen, and a reverse display in which the video signal is sequentially written to the pixel column from right to left of the screen. The display can be switched.

[0010]

According to the first aspect of the present invention, a video signal is written to a pixel column included in a part (for example, a center portion) of a horizontal screen, and a video signal is written to a pixel column included in a remaining portion (for example, left and right sides) of the horizontal screen. A normal display is enabled by writing a side black signal. At this time, a video signal and a side black signal are alternately written for each row in a specific pixel column located at the boundary between the center and the left and right sides, thereby shaping the zigzag boundary. As a result, in the related art, a boundary that has been zigzag by 1.5 pitches becomes a zigzag shape by 0.5 pitches, and the side line becomes remarkably sharp.

According to the second aspect of the present invention, a video signal is written to a pixel column included in a central portion of a horizontal screen, and a side black signal is written to a pixel column included in left and right portions of a horizontal screen to enable normal display. ing. At this time, the video signal and the side black signal are mixed and written into a predetermined number of pixel rows located at the boundary between the central portion and the left and right side portions, and the left and right boundaries that are intertwined in a zigzag shape are symmetrically shaped with respect to each other. As a result, even when the left-right inverted display is performed, the left and right boundary shapes are correctly matched with the normal display. Therefore, normal display and reverse display are performed for each of the three primary colors.
When the RGB display is projected by superimposing the two display devices, it is possible to correctly project the color tones appearing on the left and right borders.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a first view of a display device according to the present invention.
It is a schematic block diagram which shows an Example. The display device is a full-color active matrix type, and includes a pixel array section 1 and a peripheral circuit section. The pixel array unit 1 forms a horizontally long screen 2 that can be switched between wide display and normal display. The pixel array unit 1 includes a set of three primary color pixels R, G, and B arranged in a delta, and any three pixels located at the vertices of an equilateral triangle are a combination of R, G, and B as indicated by hatching. The color resolution can be apparently improved. In accordance with the delta arrangement, the pixel array unit 1 includes pixel rows that are linearly aligned and pixel columns that are intertwined in a zigzag. In this example, the screen 2 is schematically composed of seven pixel rows and 15 pixel columns. However, it actually includes, for example, hundreds of pixel rows and thousands of pixel columns. As shown in the drawing, the zigzag-shaped pixels are commonly connected by one signal line Y for each column. For example, focusing on the fourth pixel column, seven pixels R are commonly connected in a zigzag manner by the signal line Y.

On the other hand, the peripheral circuit section comprises a vertical drive circuit 3, a horizontal drive circuit 4, and a mask means 5. The vertical drive circuit 3 sequentially selects the first to seventh pixel rows for each horizontal period. The horizontal drive circuit 4 writes the video signal VSIG to each pixel column via the signal line Y in synchronization with the sequential selection. The mask means 5 similarly writes the side black signal VSB to each pixel column in synchronization with the sequential selection. Note that the above-described video signal VSIG and side black signal VSB
Is supplied from an external signal source 6 (such as a video driver).

As a feature of the present invention, a control means 7 including a timing generator and the like is connected to the above-described peripheral circuit section. The control means 7 controls the horizontal drive circuit 4 at the time of wide display to write the video signal VSIG to the first to fifteenth pixel columns over the entire screen 2. on the other hand,
By controlling the horizontal drive circuit 4 and the masking means 5 during the normal display, the video signal VSIG is written into a pixel column included in a part of the screen, and the side black signal VSB is written into the pixel column included in the rest of the screen 2. For example, the video signal VSIG is written to the fourth to eleventh pixel columns included in the central part of the horizontal screen 2, and the first and second pixel columns included in the left part of the horizontal screen 2 and The side black signal VSB is written to the 13th to 15th pixel columns included. Further, the video signal VSIG and the side black signal VSB are alternately written in a specific pixel row located at the boundary between the left and right sides and the center in normal display every one horizontal period, thereby shaping the zigzag boundary. Specifically, VSB is written into the third pixel column during the horizontal period of the odd-numbered row, while VSIG of the blue component is written during the horizontal period of the even-numbered row. As a result, the boundary between the left side portion and the center portion enters and exits in a zigzag manner by 0.5 pitch, and the side line becomes sharp. In addition, for the twelfth pixel column located at the boundary between the center and the right side, VSIG of the blue component is written in the horizontal period of the odd-numbered row, and VSB is written in the horizontal period of the even-numbered row to shape the boundary. ing.

In the embodiment described above, the horizontal drive circuit 4
And the masking means 5 are arranged separately above and below the screen 2, but the present invention is not limited to this. For example,
It is possible to incorporate the mask means 5 in the horizontal drive circuit 4. In the above-described embodiment, the masking means 5 is connected to the first to third pixel columns and the twelfth to
Although the VSB is written only in the first pixel column, the connection may be made so that the side black signal can be written in all of the first to fifteenth pixel columns in some cases.

FIG. 2 is a block diagram showing a specific configuration example of the display device shown in FIG. As shown in the drawing, 15 signal lines Y and 7 gate lines X are arranged crossing each other in the screen. Pixels are arranged at each intersection of the signal line Y and the gate line X. In this example, only the pixels commonly connected to the third signal line Y are shown. As shown in the figure, each pixel is composed of a combination of a fine liquid crystal cell LC and an active element. In this example, the active element is a thin film transistor T
r, the gate electrode of which corresponds to the corresponding gate line X
, The source electrode is connected to the corresponding signal line Y, and the drain electrode is connected to the corresponding liquid crystal cell LC. The above-mentioned peripheral circuit section drives each liquid crystal cell through an active matrix through an active matrix.

A vertical drive circuit 3 is connected to one end of each gate line X, and a gate pulse φ _V is sequentially applied to one end according to a start signal VST or a clock signal VCK supplied from a control means (not shown). Output every horizontal period (1H). The thin film transistor Tr in response to the gate pulse φ _V
Are turned on to sequentially select the first to seventh pixel rows.

A video line 8 is connected to the upper end of each signal line Y via a horizontal switch HSW. The video line 8 is divided into three lines, and receives a video signal VSIG divided into RGB from an external video driver. Video lines 8 are connected so as to correspond to the three primary colors assigned to each pixel column. Horizontal switch HSW is controlled to open and close by a sampling pulse phi _H sequentially output from the horizontal address circuit 4a, samples the video signal VSIG, writes VSIG to pixel columns in synchronization with the sequentially selected above. As can be understood from the above description,
The combination of the horizontal address circuit 4a and the horizontal switch HSW constitutes the horizontal drive circuit 4 shown in FIG. The horizontal address circuit 4a includes a start signal HST and a clock signal HCK supplied from an external timing generator or the like.
Depending on, sequentially outputs a sampling pulse phi _H. In the case of wide display, a sampling pulse φ _H1 corresponding to the first pixel column to a sampling pulse φ _H15 corresponding to the fifteenth pixel column are sequentially output. On the other hand, in the case of the normal display, _φH3 to _φH12 are output. In this case, φ _H3 and φ _H12 are irregular, and are output only every other horizontal period.

The other end of each signal line Y is connected to an auxiliary switch P
It is connected to the auxiliary line 9 via SW. The auxiliary line 9 receives a side black signal VSB from an external video driver or the like. Each auxiliary switch PSW is controlled to be opened and closed by a sampling pulse φ _P sequentially output from the horizontal address circuit 5a, and a side black signal VSB
Is sampled on the signal line Y. As understood from the above description, the horizontal address circuit 5a and the auxiliary switch P
The combination of the switches constitutes the mask unit 5 shown in FIG. The horizontal address circuit 5a receives a start signal PST or a clock signal PCK from an external timing generator or the like.
Supplied with the normal display when the sampling pulses _{φ P1, φ P2, φ P3} , φ P12, φ P13, φ P14, and outputs the phi _P15. However, φ _P3 and φ _P12 are irregular, and are output every other horizontal period. Note that the horizontal address circuit 5a is in the stop state during wide display.

Next, the operation of the circuit shown in FIG. 2 during normal display will be described with reference to the timing chart of FIG. Note that the display device of this example performs 1H inversion driving in the normally white mode. As shown, the polarity of the side black signal VSB is inverted every 1 H with reference to a predetermined central potential. The polarity of the video signal VSIG is also inverted every 1 H with reference to a predetermined center potential. The signal line located at the boundary between the center of the screen and the left or right side alternately samples VSB and VSIG, and the potential changes as shown. For example, focusing on the third signal line Y located at the boundary between the left side and the center, the sampling pulse φ from the lower horizontal address circuit 5a in the first horizontal period.
_P3 is output, and the positive polarity VSB is sampled.
In the second horizontal period, the sampling pulse φ _H3 is output from the upper horizontal address circuit 4a, and the negative polarity VSIG is sampled. Similarly, a positive VSB is sampled in the third horizontal period, a negative VSIG is sampled in the fourth horizontal period, a positive VSB is sampled in the fifth horizontal period, and a negative VSB is sampled in the sixth horizontal period. The positive VSB is sampled in the seventh horizontal period. The VSB and VSIG sampled alternately in each horizontal period in this manner are written to each pixel in a row-sequential manner at each fall of the gate pulse.

FIG. 4 is a schematic block diagram showing another embodiment of the display device according to the present invention. This display device includes a pixel array section 11 and a peripheral circuit section. The pixel array unit 11 forms a horizontally long screen that can be switched between wide display and normal display. The peripheral circuit section is the pixel array section 11
Drive. The pixel array section 11 includes a set of single color pixels arranged in a delta manner. As in the embodiment shown in FIG. 1, the pixels are arranged in a delta arrangement, but contain only pixels of a single color instead of the three primary colors. In this example, it is composed of only the green pixel G. Since the pixel array section 11 has a delta-like arrangement, linearly aligned pixel rows and zigzag pixel columns are defined as in the embodiment of FIG. In this example, a horizontally long screen schematically includes seven pixel rows and 15 pixel columns.

The peripheral circuit section has a vertical drive circuit 13, a horizontal drive circuit 14, and a mask means 15. Vertical drive circuit 1
No. 3 sequentially selects the first to seventh pixel rows. The horizontal drive circuit 14 writes the video signal VSIG to each pixel column in synchronization with the sequential selection. The mask means 15 writes the side black signal VSB to a predetermined pixel column in synchronization with the sequential selection.

As a feature of the present invention, a control means 17 connected to the above-described peripheral circuit section is provided. Control means 1
7 controls the horizontal driving circuit 14 at the time of wide display to apply the video signal VS to the first to fifteenth pixel columns over the entire screen.
Write IG. On the other hand, the normal driving horizontal drive circuit 1
4 and the mask means 15 to control the video signal VSIG to the fourth to eleventh pixel columns included in the center of the screen.
And the side black signal VSB is written to the first and second pixel columns included in the left side of the screen and the 14th and 15th pixel columns included in the right side of the screen. At this time, the video signal VSIG and the side black signal VSB are mixedly written into a predetermined number of pixel columns located at the boundary between the center and the left and right sides, and the zigzag right and left boundaries are symmetrically set to each other. Shape it. More specifically, VSIG and VSB are written alternately for each horizontal period in the third pixel column located at the boundary between the left side and the center.
As a result, the left end side boundary is shaped into a side line shape with 0.5 pitches in and out. Similarly, VSB and VSIG are alternately written to the twelfth pixel column located at the boundary between the center part and the right part. Thereby, the boundary on the right end side has the same shape as the boundary on the left end side, but is not symmetric with respect to the center of the screen. Therefore, in the present invention, VSIG and VSB are alternately written in the thirteenth pixel column every one horizontal period. Thereby, the boundary on the left end side and the boundary on the right end side are symmetrical to each other in the normal display.

The horizontal drive circuit 14 shown in FIG.
The video signals VS are sequentially arranged in pixel rows from the left to the right of the screen.
It is possible to switch between the normal display in which the IG is written and the reverse display in which the video signal is sequentially written in the pixel row from the right to the left of the screen. By using three display devices having such a configuration, it is possible to perform three-panel RGB combined display as shown in FIG. The display device having the red pixel R performs normal rotation normal display. In the display device including the green pixel G, the normal display of the reverse is performed. Blue pixel B
The display device having normal display performs normal rotation. According to the present invention, the display device has a symmetrical boundary shape. Therefore, the normal display and the reverse display are correctly aligned with each other when three sheets are overlapped, and a complete RGB combined display including the boundary is obtained.

Finally, with reference to FIG. 6, a description will be given of a specific example of the horizontal address circuit suitable for the drive for switching between the wide display and the normal display and the left / right inversion drive. As shown in the figure, the horizontal address circuit has a single shift register 40, and transfers a predetermined start signal HST for each stage to perform dot sequential writing of pixels (not shown). The shift register 40 has a structure in which flip-flops FF each having a pair of input terminals I and output terminals O are connected in multiple stages in a number corresponding to the total number of columns of pixels. The input / output terminals of the individual FFs are sequentially connected via two data transfer paths 41. In this example, M flip-flops from FF ₁ of the first stage to FF _M the final stage are connected in multiple stages. This M
All the FFs are driven to perform wide display. The M flip-flops include intermediate stages from FF _J to FF _K and are selectively driven during normal display.
In this case, not in the middle stage FF ₁ ~FF _J-1 and FF
_{K + 1 ~FF M} operation is stopped the pause stage. A pair of FF _J-1 and FF _J and another pair of FF _K and FF _{K + 1} are located at the boundary between the wide display and the normal display.

The shift register 40 of the present embodiment is bidirectional, and can selectively perform forward transfer and reverse transfer of data. For this purpose, transfer gate elements L and R are interposed between the input / output terminals of a pair of flip-flops located in adjacent stages. By selectively opening and closing the transfer gate elements L and R, data transfer is controlled in the forward direction or the reverse direction to enable bidirectional point-sequential writing of pixels. For example one of the transfer gate element L is interposed between the output terminal of the input terminal and FF ₂ of FF _1. Also, the other transfer gate element R is interposed between the input terminal I of the output terminal O and FF ₂ of FF _1. Similarly, transfer gate elements R and L are interposed between input / output terminals of FFs adjacent to each other. When the transfer gate element R is opened while the transfer gate element L is closed, the start signal HST is sequentially sent through the data transfer path 41 in the forward direction. Conversely, when the transfer gate element R is closed while the transfer gate element L is opened, the start signal HST
Are sequentially transmitted in the reverse direction via the data transfer path 41.

The horizontal address circuit has a wide input switch element W and a normal input switch element N. The wide input switch element W injects the start signal HST into the input terminal of the flip-flop located at the first stage during wide display. On the other hand, the normal input switch element N injects the start signal HST to the input terminal of the flip-flop located at a specific intermediate stage during normal display. In the forward transfer, FF1 is the _first stage, so the wide input switch element W is connected to its input terminal I. On the other hand, in the reverse transfer, the FF _M is at the first stage, so the input terminal I is also connected to the wide input switch element W. In the forward transfer at the time of normal display, FF _J corresponds to a specific intermediate stage, and a normal input switch element N is connected to its input terminal I. FF _K is a reverse transfer is the leading stage of the normal display, and is also connected to the normal input switch element N to the input terminal I. In the case of wide display, the start signal HST injected into the first stage is transferred to the last stage in both forward transfer and reverse transfer. In contrast, when the start pulse HST forward transfer is transferred to FF _K is injected into the FF _J in the normal display. In the case of reverse transfer, it is injected into FF _K and transferred to FF _J.

In the horizontal address circuit, a connection gate element G is interposed between input / output terminals of a pair of flip-flops located at the boundary between wide display and normal display. Specifically, connection gate elements G are provided between FF _J-1 and FF _J and between FF _K and FF _{K + 1} , respectively. This allows data transfer at the boundary during wide display, while blocking data transfer at the boundary during normal display. With this configuration, the single shift register 40 can reliably divide each FF between the normal display and the wide display. At the time of wide display, the connection gate element G functions equivalently to the transfer gate elements R and L described above.

FIG. 7 is a circuit diagram partially showing an example of a specific circuit configuration of the horizontal address circuit shown in FIG. In order to explain the bidirectional transfer of data, only two flip-flops (first-stage FF and next-stage FF) and their associated transfer gate elements R and L are shown. All circuit elements are composed of thin film transistors (TFTs). Both the first-stage FF and the second-stage FF are constituted by D-type flip-flops. Each D-type flip-flop includes first and second clocked inverters and a third inverter, operates in response to clock signals HCK and HCKX having phases opposite to each other, and converts data input from an input terminal IN into a clock signal. The signal is output to the output terminal OUT with a delay of a half cycle. Each of the transfer gate elements R and L is a CMOS type transmission gate element. The transfer gate elements R and L are supplied with control signals R of opposite phases supplied from a control means (not shown).
It is controlled by T and RTX. One control signal RT
Is high and the other control signal RTX is low, one transfer gate element R is opened and the other transfer gate element L is closed. Therefore, at this time, the data is supplied to the input terminal IN of the preceding stage FF after passing through the first transfer gate element R. Here, after a delay process is performed for a half cycle of the clock signal, the signal is transferred from the output terminal OUT to the input terminal IN of the next stage FF via the next transfer gate element R. In this way, data is sequentially transferred in the forward direction. On the other hand, when the control signal RT switches to low level and the control signal RTX switches to high level, one transfer gate element R closes and the other transfer gate element L opens. In this case, after the data transferred from the opposite direction is supplied to the input terminal IN of the next stage FF and subjected to a predetermined delay processing, the data is transferred from the output terminal OUT via the transfer gate element L to the input terminal of the previous stage FF. Transferred to IN. After the predetermined delay processing is performed again, the data output from the output terminal OUT reaches the next transfer gate element L.

[0030]

As described above, according to the first aspect of the present invention, in a display device having a delta pixel array and capable of switching between a wide display and a normal display, the display device is included in a central portion of a horizontally long screen. In addition, a video signal is written to a pixel row to be written, and a side black signal is written to a pixel row included on the left and right sides of a horizontally long screen, thereby realizing a normal display.
At this time, a zigzag boundary is shaped by alternately writing a video signal and a sampling signal into a specific pixel row located at the boundary between the center and the left and right sides every one horizontal period. Therefore, there is an effect that both side lines of the normal display can be sharpened. According to the second aspect of the present invention, in a display device having a single-color pixel array for each of the three primary colors and capable of switching between wide display and normal display, a video signal is applied to a pixel column included in a central portion of a horizontally long screen. A normal display is realized by writing a side black signal into a pixel row included in the left and right sides of the screen while writing. At this time, the video signal and the side black signal are mixed and written for a predetermined number of pixel rows located at the boundary between the central portion and the left and right side portions, and the left and right boundaries that are intertwined in a zigzag shape are symmetrically shaped with respect to each other. I have. Thus, when three display devices of three primary colors are superimposed on each other to perform normal display of RGB synthesis, R
This makes it possible to perfectly match the pixels of the three primary colors, so that the color tone along the side line can be made regular.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing one embodiment of a display device according to the present invention.

FIG. 2 is a block diagram showing a specific configuration example of the embodiment shown in FIG. 1;

FIG. 3 is a waveform chart for explaining the operation of the circuit shown in FIG. 2;

FIG. 4 is a schematic block diagram showing another embodiment of the display device according to the present invention.

FIG. 5 is a schematic view showing an example of how to use the embodiment shown in FIG.

FIG. 6 is a block diagram showing an example of a horizontal address circuit suitable for the present invention.

FIG. 7 is a circuit diagram showing a specific configuration example of the horizontal address circuit shown in FIG. 6;

FIG. 8 is a schematic plan view showing an example of a conventional display device.

FIG. 9 is a schematic diagram showing another example of a conventional display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pixel array part 2 Screen 3 Vertical drive circuit 4 Horizontal drive circuit 5 Mask means 6 Signal source 7 Control means 8 Video line 9 Auxiliary line 11 Pixel array part 13 Vertical drive circuit 14 Horizontal drive circuit 15 Mask means 17 Control means

Continuation of the front page (56) References JP-A-2-143781 (JP, A) JP-A-3-131182 (JP, A) JP-A-3-171116 (JP, A) JP-A-4-342395 (JP) JP-A-5-83658 (JP, A) JP-A-6-6734 (JP, A) JP-A-6-324645 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H04N 5/66 G09G 3/20 H04N 9/30

Claims (5)

(57) [Claims] An image display apparatus includes: a pixel array unit that forms a horizontally long screen that can be switched between a wide display and a normal display; and a peripheral circuit unit that drives the pixel array unit. The peripheral circuit section includes a set, includes a pixel row that is linearly arranged, and a pixel column that is intertwined in a zigzag manner. The peripheral circuit section synchronizes with the vertical drive circuit that sequentially selects each pixel row every horizontal period. A horizontal drive circuit for writing a video signal to a pixel column by using a horizontal driving circuit, and a masking unit for writing a side black signal to the pixel column. The horizontal drive circuit is controlled to write a video signal to a pixel row over the entire screen, and during normal display, the horizontal drive circuit and mask means are controlled to control the horizontal row drive circuit and the mask means so that a video row is included in a pixel row included in a part of the screen. Write a signal and write a side black signal to a pixel row included in the rest of the screen, and alternately write a video signal and a side black signal every one horizontal period to a specific pixel row located at the boundary between the two sections, forming a zigzag pattern. A display device characterized by shaping the boundary. 2. The pixel array section includes a set of pixels formed by coupling fine liquid crystal cells and active elements, and the peripheral circuit section drives each liquid crystal cell by an active matrix through individual active elements. The display device according to claim 1, wherein: 3. A pixel array section comprising a horizontally long screen capable of switching between a wide display and a normal display, and a peripheral circuit section for driving the pixel array section. The peripheral circuit section includes a set of pixels of one color and defines pixel rows that are linearly arranged and pixel columns that are intertwined in a zigzag pattern. The peripheral circuit section synchronizes with the vertical drive circuit that sequentially selects each pixel row and the sequential selection. A display device comprising: a horizontal drive circuit for writing a video signal to a pixel column by using a horizontal driving circuit; and a mask unit for writing a side black signal to a pixel column, comprising a control unit connected to the peripheral circuit unit. While controlling the horizontal drive circuit to write the video signal to the pixel columns over the entire screen, during normal display, controlling the horizontal drive circuit and the mask means to transfer the video signal to the pixel columns included in the center portion of the screen. Write and write the side black signal to the pixel columns included in the left and right sides of the screen, and apply the video signal and the side black signal to a predetermined number of pixel columns located at the boundary between the center and the left and right sides for one horizontal period every
A display device characterized in that left and right boundaries that alternately enter a zigzag shape are symmetrically shaped. 4. The non-rotating display in which a video signal is sequentially written in a pixel column from left to right of a screen, and a video signal is sequentially written in a pixel column from right to left of a screen. 4. The display device according to claim 3, wherein the display device can be switched between a reverse display and an inverted display. 5. The pixel array section includes a set of pixels formed by coupling fine liquid crystal cells and active elements, and the peripheral circuit section drives each liquid crystal cell through an active element through an active matrix. 4. The display device according to claim 3, wherein: