JPH08234165A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: To reduce the number of decoders/drivers needed for dot inversion drivings. CONSTITUTION: A liquid crystal panel 3 is provided with pixels arranged at respective crossing parts of scanning lines and signal lines intersecting each other and incorporates driving circuits which sample three kinds of video signals of respective red, green and blue signals simultaneously to distribute them to six lines of signal lines in unison and perform gathering drivings by six lines by six lines. The decoder/drivers 1, 2 are provided at least by two pieces in the panel and perform relatively delay processings of three kinds of video signals corresponding to arrangement pitches of respective pixels to supply them to the liquid crystal panel 3. The first decoder/driver 1 generates three kinds of video signals R<+> , G<+> , B<+> having the polarity of one side to distribute them to the odd numbered signal lines of together driven six lines. The second decoder/driver 2 generates three kinds of video signals R<-> , G<-> , B<-> having an opposite polarity to distribute them to even numbered signal lines of together driven six lines. A timing generator 4 controls the together drivings of driving circuits and the delay processings of decoders/drivers 1, 2 included in the liquid crystal panel 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device using an active matrix type liquid crystal panel or the like as a display device. More specifically, the present invention relates to a liquid crystal display device that employs a multiple pixel (dot) simultaneous sampling method. More specifically, the present invention relates to a liquid crystal display device that employs an AC driving technique for a liquid crystal panel by dot inversion.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a general structure of a conventional liquid crystal display device. Decoder / Driver 10
1 is provided to decode the input video signal to generate three kinds of video signals R, G and B for each of red, green and blue systems, and to separate the synchronization signal SYNC. The decoder / driver 101 further performs polarity inversion processing on the original video signal at a predetermined cycle, and converts the AC-converted video signals R, G, B into the liquid crystal panel 1.
Output to 02. The timing generator 103 operates according to the synchronization signal SYNC, and controls the liquid crystal panel 102 to have HST, HCK1, HCK2, VST, VCK1 and VC.
A timing signal such as K2 is supplied. Through these signals, the vertical drive circuit 104 built in the liquid crystal panel 102.
And the operation of the horizontal drive circuit 105 is controlled. Further, the alternating signal FRP is supplied to the decoder / driver 101 to control the timing of the polarity reversal process of the video signal described above. The liquid crystal panel 102 includes scanning lines X in rows and signal lines Y in columns. A pixel 106 is provided at the intersection of both lines. Vertical drive circuit 104
Selects the pixel 106 by sequentially scanning the scan line X for each vertical period (one field period, 1F). On the other hand, the horizontal drive circuit 105 sequentially samples the video signals R, G, B of three systems on the signal line Y every horizontal period (1H),
The video signal is written to the selected pixel 106. The vertical drive circuit 104 sequentially transfers the vertical start signal VST input from the timing generator 103 in accordance with the two-phase clock signals VCK1 and VCK2, and scans the scan line X described above. The horizontal drive circuit 105 uses the horizontal start signal HST input from the timing generator 103 as the two-phase clock signals HCK1 and HC.
The above-described sampling operation is performed by sequentially transferring according to K2.

Generally, when driving the liquid crystal panel 102, AC driving is performed to prevent deterioration of the liquid crystal. For example,
The timing generator 103 supplies the alternating signal FRP having a period of 2H to the decoder / driver 101 in response to the horizontal synchronizing signal having a period of 1H. As a result, the polarities of the video signals R, G, B are inverted every 1H with respect to the reference potential VCOM, and so-called 1H inversion driving is performed. As shown in FIG. 9, the scanning lines X and the signal lines Y have many intersections on the same plane in the liquid crystal panel 102. Coupling between Y and scan line X is a problem. As the liquid crystal panel becomes larger and finer, in the case of 1H inversion driving, the polarity of a plurality of signal lines Y intersecting the same scanning line X is inverted every 1H. All signal lines Y
Change in the electric potential of all jumps into one scanning line X all at once,
This effect further affects the pixel potential. For this reason, the pixel potential oscillates in a cycle of 1H and the effective voltage applied to the liquid crystal is reduced, causing a defect such as insufficient contrast.

In order to prevent the fluctuation of the pixel potential caused by such coupling, AC drive in which the polarity is inverted for each signal line Y has been proposed, for example, Japanese Patent Publication No. 4-224.
No. 86 publication. As shown in FIG. 10, if the polarity inversion for each signal line and the 1H inversion are combined, so-called dot inversion drive (checkered inversion drive) becomes possible. In this dot inversion drive, the potential levels sampled in each signal line are alternately opposite in polarity, so that the potential change is canceled on one scanning line, and the above-described coupling can be significantly suppressed. Further, flicker and the like due to 1F inversion can be suppressed.

By the way, when driving a full-color type liquid crystal panel, a multi-dot simultaneous sampling method is effective, and is disclosed in, for example, Japanese Unexamined Patent Publication No. 4-116686. This method will be briefly described with reference to FIG. The liquid crystal panel 102 has data lines X along the row direction.
And a signal line Y along the column direction, and pixels R, G, B of the three primary colors arranged at the intersections of the two. The pixels R, G, B are arranged at a predetermined pitch along the row direction. Also, horizontal switches HSW1, HSW2, ..., HSWn-1, H connected to one end of the signal line Y in units of three lines.
It has SWn. These horizontal switches HSW simultaneously select each signal line Y in units of three lines, and select three types of AC video signals R, G, B divided into three primary colors into three pixels R ,.
Write in G and B. The horizontal switch HSW is shown in FIG.
It constitutes a part of the horizontal drive circuit 105 shown in FIG. When performing such three-dot simultaneous sampling drive, the decoder / driver 10 is a delay unit that relatively gives a delay amount corresponding to the pixel pitch to the video signals R, G, B of the three systems in advance.
1 (FIG. 9). A relative amount of delay corresponding to the pixel pitch is given to the video signals R, G, B, and the horizontal switches are simultaneously controlled to open and close in units of R, G, B, so that a shift register for driving the horizontal switches is driven. The number of stages is reduced to simplify the configuration and the power consumption is also reduced so that good color display can be obtained. Since each horizontal switch HSW is controlled to be opened and closed at the same time by the sampling pulse output from the shift register, the number of stages of the shift register of the horizontal drive circuit becomes 1/3. Further, the frequencies of the horizontal clock signals HCK1 and HCK2 supplied from the timing generator 103 also become 1/3. The decoder / driver 101 designed for such a 3-dot simultaneous sampling system is currently being generalized as a system IC.

[0006]

As described above, in the liquid crystal panel drive system, the dot inversion drive as shown in FIG. 10 is preferable, which remarkably improves the image quality by dispersing flicker and canceling the coupling. it can. In order to perform the dot inversion drive, it is necessary to input the video signals RGB whose polarities are inverted line by line to the signal line. However, as described above, the full-color liquid crystal panel employs the 3-dot simultaneous sampling method, and since it is driven in units of three RGB, the system IC that constitutes the decoder / driver for signal processing is RGB one system. There are many output units. Therefore, there is a problem in practical use when the dot inversion drive is adopted.

This problem will be briefly described with reference to FIG. In this example, the signal line Y is set as a unit of three lines, and the multiple dot simultaneous sampling method is performed. The horizontal switch HSW selects three signal lines Y at the same time, and the corresponding pixel 106 is selected via the thin film transistor TR.
Write the video signal to. At this time, if the dot inversion drive is attempted, for example, the positive video signals R ⁺ , G ⁺ , and B ⁺ are sampled on the odd-numbered signal lines Y, and the negative video signals are sampled on the even-numbered signal lines Y. signal R ^-,
It is necessary to supply G ⁻ and B ⁻ . In this case, four system ICs for the decoder / driver are required, resulting in waste of output terminals. That is, to the three signal lines Y belonging to the first group, a system IC that supplies positive polarity video signals R ⁺ and B ⁺ and a system I that supplies G ⁻ similarly.
C is required. Further, a system IC supplying R ⁻ and B ⁻ to the three signal lines Y belonging to the second group, and G
A system IC that supplies ⁺ is required. Like this, 6
A total of four system ICs are required for the signal line Y of the book, the number of unused terminals is 3 × 4-6 = 6, which is extremely uneconomical, which causes an increase in the cost of the entire system. . Further, FIG. 13 shows a case where the multiple dot simultaneous sampling method is performed in units of two lines. If the dot inversion driving method is applied to this, too, four system ICs are still required, which is extremely uneconomical.

[0008]

Means for Solving the Problems In order to solve the above-mentioned problems of the conventional technique, the following means were taken. That is, the liquid crystal display device according to the present invention has a liquid crystal panel, a decoder / driver, and a timing generator as a basic configuration. The liquid crystal panel includes pixels arranged at respective intersections of scanning lines and signal lines intersecting with each other. In addition, it has a built-in drive circuit, which simultaneously samples three types of red, green, and blue video signals and distributes them to 6 × n (n is an integer of 1 or 2 or more) signal lines at a time, collecting 6 × n each. Drive. At least two decoders / drivers are provided, and the three types of video signals are relatively delayed in advance according to the pixel arrangement pitch and supplied to the liquid crystal panel. At this time, one of the decoders / drivers generates a three-polarity video signal of one polarity and distributes it to the odd-numbered 6n signal lines collectively driven through the drive circuit. The other decoder / driver generates three kinds of video signals of opposite polarities and distributes them to even-numbered 6n signal lines collectively driven through the drive circuit. The timing generator controls the collective driving of the driving circuits included in the liquid crystal panel and also controls the delay processing of the decoder / driver.

Preferably, the drive circuit comprises a horizontal drive circuit for collectively driving 6n signal lines and a vertical drive circuit for sequentially selectively driving one or two scanning lines in accordance with the collective drive. There is. That is, this vertical drive circuit can switch between single line selection and simultaneous selection of two lines, thereby achieving both non-interlaced scanning and interlaced scanning. For this reason, the vertical drive circuit includes a switching means, and when a non-interlaced video signal is input, a sequential selection drive for each scanning line (single line single selection drive) is executed, and an interlaced video signal is output. When input, sequential selection drive of two scanning lines (two-line simultaneous selection drive) is executed.

[0010]

According to the present invention, 6n signal lines are collectively driven. In accordance with this, the three types of video signals of one polarity are distributed to the odd-numbered 6n signal lines,
Three types of video signals of opposite polarities are distributed to even-numbered signal lines of the book. Therefore, for example, when 6 signal lines are driven collectively, it can be dealt with by using only two decoder / driver ICs having one RGB output system, and a system without waste can be constructed. Further, by setting the input unit of the signal line to be 12, 18, ..., And 6n units, the generation of unused IC terminals is prevented, the number of decoder / driver ICs is reduced, and the frequency of the horizontal clock signal is reduced. It can be reduced. Thus, by setting the input unit of the video signal to 6n, the number of system IC chips required for dot inversion can be optimized, and the system cost can be reduced. In particular,
In the structure in which the vertical drive circuit side sequentially selects and drives two scanning lines to accommodate interlaced video signals, flicker of 15 Hz period becomes noticeable. In this respect, when the dot inversion drive according to the present invention is applied, the flicker is dispersed and the image quality is improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. As shown in FIG. 1, the present liquid crystal display device includes a pair of decoders / drivers 1 and 2, an active matrix type color liquid crystal panel 3, and a timing generator 4. Each of the decoders / drivers 1 and 2 decodes an externally input video signal to generate three kinds of video signals R, G and B for the three primary colors of red, green and blue, and separates the sync signal SYNC. Further, each of the decoders / drivers 1 and 2 performs polarity inversion processing of the video signals R, G, B at 1H and outputs an alternating video signal. The liquid crystal panel 3 has row-shaped scanning lines, column-shaped signal lines, and pixels provided at the intersections of the two. It also has a vertical drive circuit and a horizontal drive circuit. The vertical drive circuit sequentially scans the scan lines to select pixels. The horizontal driving circuit sequentially samples the alternating video signal on the signal line every 1H and writes the alternating video signal to the selected pixel. The timing generator 4 operates in response to the synchronization signal SYNC and supplies the alternating signal FRP to the pair of decoders / drivers 1 and 2 to control the timing of the polarity inversion process. Further, the sample hold signal SH is supplied to the pair of decoders / drivers 1 and 2 to control their delay processing.
That is, the decoders / drivers 1 and 2 relatively delay the three types of video signals R, G, and B according to the pixel arrangement pitch and supply them to the liquid crystal panel 3. The timing generator 4 further includes HST, HCK1, HCK2 and VS.
T, VCK1, VCK2, etc. are supplied to the liquid crystal panel 3 to control the operation of the vertical drive circuit and the horizontal drive circuit. In addition, the control signals EN and INT are supplied to the liquid crystal panel 3 to control the switching between the sequential selective drive for each scanning line and the sequential selective drive for every two scanning lines.

A feature of the present invention is that the first decoder /
The driver 1 outputs video signals R ⁺ , G ⁺ , B ⁺ of one polarity. The second decoder / driver 2 outputs video signals R ⁻ , G ⁻ , B ⁻ having opposite polarities. In addition, R ⁺ , G ⁺ , B
⁺ A pair ^{of, R -, G -, B} - set, depending on the FRP IH
The sign is reversed every time. That is, in this example, 1H inversion drive is performed.

FIG. 2 is a block diagram showing a concrete configuration example of the liquid crystal panel 3 shown in FIG. As shown in the figure, the liquid crystal panel is provided with scanning lines X in rows and signal lines Y in columns, and pixels 31 are provided at the intersections of both. The pixel 31 includes a liquid crystal cell LC, a storage capacitor CS, and a thin film transistor TR. Further, it is provided with six video lines 32, and a total of six video signals R ⁺ , G ⁺ , B ⁺ , R supplied from the pair of decoders / drivers 1 and 2 are provided.
^{-, G -,} B ^-, respectively accept. Individual signal line Y
Are connected to a predetermined video line 32 via a horizontal switch HSW with six as one unit. In addition to the above configuration, the present liquid crystal panel includes a vertical drive circuit 33 and a horizontal drive circuit 3.
4 built-in. The vertical drive circuit 33 supplies VST, VCK1, VCK2 supplied from the timing generator 4.
The scanning lines X are sequentially scanned one by one or two by two in order to select the pixels 31 for each row. Control signals EN and INT are also supplied from the timing generator 4 in order to control the switching between single line single selection and simultaneous selection of two lines. On the other hand, the horizontal drive circuit 34 uses the HST, HCK1, and HCK supplied from the timing generator 4.
It operates in response to 2 and sequentially opens and closes the HSW to drive the six signal lines Y collectively as one unit. That is, the video signals R ⁺ , B ⁺ , G ⁺ , G ⁻ , R ⁻ , and B ⁻ are simultaneously sampled to the corresponding signal lines Y, respectively.

As shown, a video signal R ^{+ of} one polarity,
B ⁺ and G ⁺ are distributed to the odd-numbered of the six signal lines Y collectively driven through the horizontal drive circuit 34. On the other hand, the video signals R ⁻ , G ⁻ , and B ⁻ having opposite polarities are distributed to even-numbered six signal lines Y which are collectively driven by the horizontal drive circuit 34. That is, the horizontal switch HSW simultaneously selects the signal line Y in units of six lines, and writes the video signals R ⁺ , G ⁺ , B ⁺ and R ⁻ , G ⁻ , B ⁻ alternately in each pixel. By combining this with 1H inversion, complete dot inversion drive is possible. Therefore, unlike the prior art, the coupling that occurs when the polarity of all the signal lines Y is simultaneously reversed along the same scanning line X is canceled out, and the problem of lowering the contrast does not occur. Although the six signal lines Y are simultaneously selected as one unit in the above-described embodiment, the present invention is not limited to this.
Generally, by driving 6n signal lines Y together as one group, the number of decoder / driver IC chips required for dot inversion can be optimized and the system cost can be reduced.

By the way, the vertical drive circuit of the liquid crystal panel according to the present invention is, as described above, one line single selection drive and two lines.
The line simultaneous selection drive can be switched, and both non-interlaced scanning and interlaced scanning are used. This point will be described in detail below. FIG. 3 is a block diagram showing a specific configuration example of the vertical drive circuit.
A shift register 51 in which D-type flip-flops DF / F are connected in multiple stages is provided, and VST is sequentially transferred according to VCK1 and VCK2, and primary selection pulses a, b, c, d.
Are sequentially generated. Further, the AND gate element AND1 provided for each stage is provided, and the primary selection pulse (for example, a, b) output from the adjacent stage is AND-processed and the secondary selection pulse (for example, A1) is output. . Further, an AND gate element AND2 provided for each stage is provided, and the waveforms of A1, B1, C1, D1 are shaped according to EN, and final secondary selection pulses A2, B2, C2, D2 are generated. . These are supplied to the corresponding scan lines. As a characteristic item, a switch VSW is provided for each stage, and constitutes a switching means. This VSW is open / close controlled by INT. When INT is at low level, the primary selection pulse from DF / F is guided to the AND1 side. When INT is at a high level, DF / F and AND1 are disconnected, and the disconnected input terminal of AND1 is connected to the high level side. As a result, the gate of AND1 is opened and DF
Outputs a / b, c, d from / F correspond to the corresponding AN
It is output after passing through D1 and AND2. However, AND
2 performs predetermined waveform shaping processing according to EN.

FIG. 4 is a timing chart for explaining the operation of the vertical drive circuit shown in FIG. This timing chart shows a case where non-interlaced driving is performed on a liquid crystal panel having a full frame structure. The vertical clock signals VCK1 and VCK2 have a duty ratio of 50.
It is set to%. The vertical start signal VST is sequentially transferred every half cycle of the clock signals VCK1 and VCK2,
From the D-F / F of each stage, the primary selection pulses a, b, c,
d is obtained. Here, INT is set to the low level and VSW is in the conductive state. Therefore, the primary selection pulses a, b, c, d are ANDed by the AND1, and the secondary selection pulses A1, B1, C1, D1 are sequentially output. At this time, EN is set to the high level, so A1, B1, C1, D1 remain A2, B.
2, C2 and D2 are supplied to the corresponding scan lines.

In this case, as shown in FIG. 5, a selection pulse is sequentially generated for each horizontal line X of the liquid crystal panel, and a video signal corresponding to one line is written and transferred to perform non-interlaced driving.

On the other hand, FIG. 6 shows a timing chart when the liquid crystal panel of the full frame structure is driven by the interlace drive. In this example, the duty ratio of VCK1 is set to 5% and the duty ratio of VCK2 is set to 9%.
It is set to 5%. In this case, the first stage DF /
With respect to the primary selection pulse a output from F, the primary selection pulse b output from the second stage D-F / F is output after being delayed by a duty ratio of 5%. 3rd stage DF
The primary selection pulse c output from / F is output with a delay corresponding to a duty ratio of 95% with respect to the preceding stage b. When VCK1 and VCK2 are switched between the odd field (ODD) and the even field (EVEN), the phase relationship of a, b, c, d changes as shown in the figure. Here, since INT is set to the high level, VSW is switched and the D-F / F of the next stage is ANDed.
Separated from 1. Therefore, a, b, c and d pass through AND1 as they are to become A1, B1, C1 and D1.
Here, EN becomes low active in synchronization with VCK. Therefore, A1, B1, C1, D1 are masked by AND2, and the final selection pulses A2, B2, C
2, D2 is obtained. As shown in the figure, A2 and B2 are simultaneously output and two lines can be simultaneously selected. C2 and D2 are simultaneously output for the next two lines. The set of lines that are simultaneously selected is controlled such that ODD and EVEN are shifted by one line.

FIG. 7 is a schematic diagram showing an example of interlace driving by simultaneous selection of two lines. In ODD, only one line is selected alone, and then the line is selected at the same time. Subsequently, the lines and are selected at the same time. In addition, lines, are simultaneously selected. EV
In EN, the set of line pairs is shifted by one line, and the lines are first selected simultaneously. Next, lines and lines are selected simultaneously. In this way, interlace driving is performed by repeating ODD and EVEN.

FIG. 8 shows a change in polarity of the video signal when attention is paid to each line, ....
However, this is the case where the dot inversion drive is not performed. For example, focusing on lines, positive, positive,
The polarity changes in the order of negative and negative. Negative, positive,
The polarity changes like positive and negative. On the line negative, negative,
The polarity changes like positive and positive. Positive, negative,
The polarity changes like negative and positive. Thus, when 1H inversion is performed and interlace driving is performed by simultaneous selection of two lines, the polarity change of the video signal becomes a four-field cycle (15 Hz), and flicker becomes noticeable. Therefore, in the present invention, since this 15 Hz flicker is dispersed,
The dot inversion drive described above is adopted.

[0021]

As described above, according to the present invention, by setting the input unit of the video signal to 6n, the number of system IC chips required for dot inversion can be optimized and the cost of the display system can be reduced. It is possible. Further, by driving 6n signal lines together, the frequency of the horizontal clock signal can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a circuit diagram showing an example of a liquid crystal panel incorporated in the liquid crystal display device shown in FIG.

FIG. 3 is a circuit diagram showing an example of a vertical drive circuit incorporated in the liquid crystal panel shown in FIG.

FIG. 4 is a timing chart for explaining the operation of the vertical drive circuit shown in FIG.

5 is a schematic diagram showing non-interlaced driving of the liquid crystal panel shown in FIG.

FIG. 6 is a timing chart used to explain the operation of the vertical drive circuit shown in FIG.

7 is a schematic diagram showing interlaced driving of the liquid crystal panel shown in FIG.

FIG. 8 is a schematic diagram showing a change in polarity of a video signal during interlace driving.

FIG. 9 is a block diagram showing an example of a conventional liquid crystal display device.

FIG. 10 is a diagram schematically showing dot inversion driving.

FIG. 11 is a schematic diagram illustrating an example of simultaneous driving of plural dots.

FIG. 12 is a circuit diagram showing an example of a conventional liquid crystal panel.

FIG. 13 is a circuit diagram showing another example of a conventional liquid crystal panel.

[Explanation of symbols]

 1 Decoder / Driver 2 Decoder / Driver 3 Liquid Crystal Panel 4 Timing Generator 31 Pixels 33 Vertical Drive Circuit 34 Horizontal Drive Circuit

Claims (3)

[Claims] 1. A liquid crystal display device comprising a liquid crystal panel, a decoder / driver, and a timing generator, the liquid crystal panel comprising pixels arranged at respective intersections of scanning lines and signal lines intersecting each other, and red, green, and blue pixels. And a driving circuit for simultaneously sampling the 3 types of video signals and simultaneously distributing them to 6 × n (n is an integer of 1 or 2 or more) signal lines to drive 6 × n at a time. / Driver is provided at least, and each of the three types of video signals is relatively delayed in advance according to the pixel arrangement pitch and supplied to the liquid crystal panel, and one decoder / driver outputs one type of three types of video signals. Generated and distributed to the odd-numbered 6n signal lines that are collectively driven through the drive circuit, and the other decoder / driver generates three-type video signals of opposite polarities. The 6n signal lines collectively driven via the drive circuit are distributed to even-numbered signal lines, and the timing generator controls the collective drive of the drive circuits included in the liquid crystal panel and the delay processing of the decoder / driver. A liquid crystal display device characterized by: 2. The drive circuit is divided into a horizontal drive circuit that collectively drives 6n signal lines and a vertical drive circuit that sequentially selects and drives one or two scan lines in accordance with the collective drive. The liquid crystal display device according to claim 1, wherein: 3. The vertical drive circuit includes a switching means, and performs sequential selective drive for each scanning line when a non-interlaced video signal is input, and when the interlaced video signal is input, a scanning line 2 is selected. 3. The liquid crystal display device according to claim 2, wherein sequential selection drive is performed for each book.