JPH07322177A - Display device - Google Patents

Abstract

PURPOSE:To shape a side line appearing at the time of performing a switch from a wide display to a normal display. CONSTITUTION:An image element array part 1 composes a long sideways screen where wide and normal displays are possible to be switched, contains the set of three original color picture elements R, G and B and stipulates the picture element line of linear alignment and the picture element column of a zigzag. A peripheral circuit part has a vertical driving circuit 3 successively selecting each picture element line, a horizontal driving circuit 4 writing a video signal VSIG in the picture element column and a mask means 5 writing a side black signal VSB. At the time of a normal display, the horizontal driving circuit 4 and the mask means 5 are controlled by a control means 7, the video signal VSIG is written in the picture element column at the center part of a screen 2 and a side black signal VSB is written in the picture element column on the left and right side parts. The video signal and the side black signal are alternately written in the specified picture element column of the boundary of the center part and the left and right side parts for every horizontal period and the boundary is faired.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device. More specifically, the present invention relates to a display device having pixels in a delta arrangement and having a screen capable of switching between normal display (for example, aspect ratio 4: 3) and wide display (for example, aspect ratio 16: 9). For more details,
This is related to the technique for shaping the boundary lines that appear at the left and right ends during normal display.

[0002]

2. Description of the Related Art The structure of a conventional display device will be briefly described with reference to FIG. As shown in the figure, a pixel array that forms a horizontally long screen capable of switching between wide display and normal display is provided. The pixel array is composed of a set of three primary color pixels R, G, B arranged in a delta arrangement. A delta array of pixel arrays includes linearly aligned pixel rows and zigzag interdigitated pixel columns. In the schematic example of FIG. 8, seven pixel rows and fifteen pixel columns are shown. It should be noted that an actual active matrix type display device includes, for example, several hundred to one thousand and several hundred pixel rows and pixel columns. As shown in the figure, in the delta arrangement, the pixels R, G and B are arranged in order at a predetermined pitch along the row direction. However, in the odd-numbered row and the even-numbered row, the sets of pixels R, G, and B are offset from each other by 1.5 pitches. Therefore, any three pixels (shown by hatching) located at the vertices of an equilateral triangle are always a combination of R, G, and B and are called a delta array. This delta arrangement can apparently improve color resolution and provide smooth color display. However, by adopting the delta arrangement, each pixel row becomes a zigzag complicated shape. For example, focusing on the fourth column, the configuration is such that seven pixels R are commonly connected by one signal line across the first row to the seventh row. Since the pixel R is shifted by 1.5 pitches between the odd-numbered row and the even-numbered row, the pixel R becomes a zigzag pixel row. Similarly, the fifth column includes pixels G intricately zigzag row by row. Further, the sixth column has a configuration in which pixels B are zigzag in every row.

When driving the display device having such a configuration, each pixel row is sequentially selected every horizontal period, and video signals for each of the three primary colors are written to the pixel column in synchronization with the sequential selection. During wide display, video signals are sequentially written from the first pixel column to the fifteenth pixel column over the entire screen. On the other hand, during normal display, the video signal is written to the 4th to 12th pixel columns included in the center of the screen, and the 1st to 3rd pixel columns included in the left side of the screen and the 13th pixel included in the right side of the screen. A side black signal is written in the 14th pixel column.

[0004]

FIG. 8 shows a normal display in which side black signals are written on the left and right sides of the screen. As described above, since each pixel column is in a zigzag pattern due to the delta arrangement, it is shifted by 1.5 pitches for each row. Therefore, there is a problem in that the boundaries between the left and right sides and the center of the screen are intricately zigzag by 1.5 pitches, and both ends of the normal display do not appear sharply.

Next, another problem to be solved by the present invention will be described with reference to FIG. In a display device capable of switching between wide display and normal display, a structure capable of switching between normal rotation display and reverse rotation display for the left and right of the screen has also been recently developed. This left-right inversion function becomes necessary, for example, when an active matrix type display device is applied to a light valve of a projector. The projector is composed of three display devices to which each of the three primary colors is assigned and a common magnifying projection lens system. Each display device functions as a light valve for each color system of red, green, and blue. Each display device decomposes and displays the primary image into red, green, and blue components. At the same time, red, green, and blue illumination light is incident on each display device. After the monochromatic transmitted light of each display device is combined by a dichroic prism or a dichroic mirror, the combined full-color image is enlarged and projected on a screen by a projection lens system. In the optical system of this projector, the primary image is synthesized after repeating reflection inversion several times. The number of reflection inversions for each color system varies depending on the arrangement structure of the optical system. Therefore, in order to obtain a matched full-color image, it is necessary to reversely display the primary image of a specific color in advance. The example in FIG. 9 shows an example in which the red image (R) and the blue image (B) are displayed in the normal rotation while the green image (G) is displayed in the reverse rotation.

However, when a normal display is projected on a screen composed of a set of single color pixels arranged in a delta pattern, the boundary lines appearing at the left and right ends are zigzag-shaped as described above. Furthermore, if the number of pixels included in each row is constant, the zigzag shape of the left and right boundary lines becomes asymmetric. Therefore, as shown in FIG. 9, between the red and blue normal display and the green reverse display, the three primary color pixels R,
A part where G and B do not overlap occurs. Therefore, there is a problem that an unnatural color tone appears on the left and right side lines of the RGB composite display.

[0007]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, it is a first object of the present invention to sharpen the side lines at both ends of the screen when switching from wide display to normal display. In addition, the red, green and blue color display devices are 3
A second object is to adjust the color tone of the side lines at both ends of the screen when switching from the wide display to the normal display with a structure in which the RGB composite display is projected by superimposing the sheets.

The following measures have been taken to achieve the first object. That is, the display device according to the present invention has, as a basic configuration, a pixel array section that constitutes a horizontally long screen capable of switching between wide display and normal display, and a peripheral circuit section that drives the pixel array section. The pixel array section includes a set of three primary color pixels arranged in a delta arrangement to define linearly aligned pixel rows and zigzag intricate pixel columns. The peripheral circuit section includes a vertical drive circuit that sequentially selects each pixel row for each horizontal period, a horizontal drive circuit that writes a video signal to a pixel column in synchronization with the sequential selection, and a mask unit that writes a side black signal to the pixel column. Have and. As a feature of the present invention, a control means connected to the peripheral circuit portion is provided, and the horizontal drive circuit is controlled during wide display to write a video signal in pixel columns over the entire screen. On the other hand, during normal display, the horizontal drive circuit and the mask means are controlled to write a video signal in a pixel column included in a part of the screen and a side black signal in a pixel column included in the rest of the screen. At this time, a video signal and a side black signal are alternately written to a specific pixel row located at the boundary between both parts every horizontal period, and the boundary intricately zigzag is shaped.

The following measures have been taken to achieve the second object of the present invention. That is, the display device according to the present invention has, as a basic configuration, a pixel array section that forms a horizontally long screen capable of switching between wide display and normal display, and a peripheral circuit section that drives the pixel array section. . The pixel array portion includes a set of single color pixels arranged in a delta pattern to define linearly aligned pixel rows and zigzag intricate pixel columns. The peripheral circuit section includes a vertical drive circuit that sequentially selects each pixel row, a horizontal drive circuit that writes a video signal to a pixel column in synchronization with the sequential selection, and a mask unit that writes a side black signal to the pixel column. As a feature of the present invention, a control means connected to the peripheral circuit portion is provided, and the horizontal drive circuit is controlled during wide display to write a video signal in pixel columns over the entire screen. On the other hand, during normal display, the horizontal drive circuit and the masking means are controlled to write the video signal to the pixel columns included in the central part of the screen and write the side black signals to the pixel columns included on the left and right sides of the screen. At this time, the video signal and the side black signal are mixed with respect to a predetermined number of pixel columns located at the boundary between the central part and the left and right side parts, and the left and right boundaries that are complicated in writing zigzag are shaped symmetrically with each other. Preferably, the horizontal drive circuit has a normal display in which video signals are sequentially written in pixel columns from left to right of the screen, and a reverse display in which video signals are sequentially written in pixel columns from right to left of the screen. The display can be switched.

[0010]

According to the first aspect of the present invention, a video signal is written in a pixel column included in a part (for example, a central portion) of a horizontally long screen and is written in a pixel column included in the rest of the horizontally long screen (for example, left and right side portions). A side black signal is written to enable normal display. At this time, a video signal and a side black signal are alternately written row by row to a specific pixel column located at the boundary between the central portion and the left and right side portions to shape the boundary intricately zigzag. As a result, conventionally, a boundary that is zigzag-complexed by 1.5 pitches has a zigzag shape for 0.5 pitches, and the side lines are remarkably sharp.

According to the second aspect of the present invention, the video signal is written in the pixel column included in the central portion of the landscape screen and the side black signals are written in the pixel columns included in the left and right sides of the landscape screen to enable normal display. ing. At this time, the video signal and the side black signal are mixed and written into a predetermined number of pixel columns located at the boundary between the central portion and the left and right side portions, and the left and right boundaries intricately zigzag are shaped symmetrically with each other. As a result, the right and left boundary shapes are correctly aligned with the normal display even when the left and right reverse display is performed. Therefore, the normal display and the reverse display are performed for each of the three primary colors.
When the RGB display is displayed by superposing the display devices on one another, the color tones appearing on the left and right boundaries can be correctly displayed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a first display device according to the present invention.
It is a schematic block diagram showing an example. The display device is an active matrix type full-color type and includes a pixel array section 1 and a peripheral circuit section. The pixel array unit 1 constitutes a horizontally long screen 2 capable of switching between wide display and normal display. The pixel array unit 1 includes a set of three primary color pixels R, G, B arranged in a delta array, and any three pixels located at the vertices of an equilateral triangle are a combination of R, G, B as shown by hatching. The color resolution can be apparently improved. According to the delta arrangement, the pixel array unit 1 includes linearly aligned pixel rows and zigzag intricate pixel columns. In this example, the screen 2 is typically composed of 7 pixel rows and 15 pixel columns. However, in reality, for example, the pixel row includes hundreds of pixel rows and the pixel column including thousands of pixels. As shown in the figure, the zigzag intricate pixels are commonly connected by one signal line Y for each column. For example, focusing on the fourth pixel column, seven pixels R are commonly connected in a zigzag manner by a signal line Y.

On the other hand, the peripheral circuit section comprises a vertical drive circuit 3, a horizontal drive circuit 4 and a mask means 5. The vertical drive circuit 3 sequentially selects the first to seventh pixel rows every horizontal period. The horizontal drive circuit 4 writes the video signal VSIG to each pixel column via the signal line Y in synchronization with the sequential selection. Similarly, the mask means 5 writes the side black signal VSB in each pixel column in synchronization with the sequential selection. The above-mentioned video signal VSIG and side black signal VSB
Is supplied from, for example, an external signal source 6 (video driver or the like).

A feature of the present invention is that the control means 7 including a timing generator is connected to the above-mentioned peripheral circuit section. The control means 7 controls the horizontal drive circuit 4 during wide display to write the video signal VSIG in the first to fifteenth pixel columns over the entire screen 2. on the other hand,
By controlling the horizontal drive circuit 4 and the mask means 5 during normal display, the video signal VSIG is written to the pixel columns included in a part of the screen, and the side black signal VSB is written to the pixel columns included in the rest of the screen 2. For example, the video signal VSIG is written to the 4th to 11th pixel columns included in the central portion of the horizontal screen 2, and the first and second pixel columns included in the left side portion of the horizontal screen 2 and the right side portion The side black signal VSB is written to the included 13th to 15th pixel columns. Further, the video signal VSIG and the side black signal VSB are alternately written for each horizontal period to a specific pixel column located on the boundary between the left and right side portions and the central portion during normal display, and the boundary intricately zigzag is shaped. Specifically, VSB is written to the third pixel column in the horizontal period of the odd-numbered rows, while VSIG of the blue component is written in the horizontal period of the even-numbered rows. As a result, the boundary between the left side portion and the central portion moves in and out in zigzag by 0.5 pitch, and the side line becomes sharp. For the twelfth pixel column located at the boundary between the central part and the right part, blue component VSIG is written in the horizontal period of the odd-numbered rows and VSB is written in the horizontal period of the even-numbered rows to shape the boundary. ing.

In the above-mentioned embodiment, the horizontal drive circuit 4
Although the mask means 5 is arranged above and below the screen 2 in a divided manner, the present invention is not limited to this. For example,
It is possible to incorporate the mask means 5 in the horizontal drive circuit 4. Further, in the above-described embodiment, the masking means 5 passes the signal line Y to the first to third pixel columns and the twelfth to fifteenth pixel columns.
Although VSB is written only to the pixel column of the th, in some cases, it may be connected so that the side black signal can be written to all the pixel columns of the first to fifteenth.

FIG. 2 is a block diagram showing a specific configuration example of the display device shown in FIG. As shown in the figure, 15 signal lines Y and 7 gate lines X are arranged in an intersecting manner in the screen. A pixel is arranged at each intersection of the signal line Y and the gate line X. In this example, only the pixels commonly connected to the third signal line Y are shown. As shown in the figure, each pixel comprises a combination of a fine liquid crystal cell LC and an active element. In this example, the active element is the thin film transistor T
r, and its gate electrode is the corresponding gate line X
, The source electrode is connected to the corresponding signal line Y, and the drain electrode is connected to the corresponding liquid crystal cell LC. The peripheral circuit section described above drives each liquid crystal cell in an active matrix via individual active elements.

A vertical drive circuit 3 is connected to one end of each gate line X, and sequentially outputs a gate pulse φ _V according to a start signal VST, a clock signal VCK, etc. supplied from a control means (not shown). Output every horizontal period (1H). In response to the gate pulse φ _V , the thin film transistor Tr
Are sequentially conducted, and the first to seventh pixel rows are sequentially selected.

A video line 8 is connected to the upper end of each signal line Y via a horizontal switch HSW. The video line 8 is divided into three lines, and the video signal VSIG divided into RGB is supplied from an external video driver. Video lines 8 are connected so as to correspond to the three primary colors assigned to each pixel column. The horizontal switch HSW is open / close controlled by the sampling pulse φ _H sequentially output from the horizontal address circuit 4a, samples the video signal VSIG, and writes VSIG to the pixel column in synchronization with the above-described sequential selection. As can be understood from the above explanation,
The combination of the horizontal address circuit 4a and the horizontal switch HSW constitutes the horizontal drive circuit 4 shown in FIG. The horizontal address circuit 4a is provided with a start signal HST and a clock signal HCK supplied from an external timing generator or the like.
The sampling pulse φ _H is sequentially output in accordance with the above. In the case of wide display, the sampling pulse φ _H1 corresponding to the first pixel column to the sampling pulse φ _H15 corresponding to the fifteenth pixel column are sequentially output. On the other hand, in the case of normal display, _φH3 to _φH12 are output. In this case, φ _H3 and φ _H12 are irregular and are output only every other horizontal period.

The other end of each signal line Y is an auxiliary switch P.
It is connected to the auxiliary line 9 via SW. The auxiliary line 9 receives the side black signal VSB from an external video driver or the like. Each auxiliary switch PSW is controlled to open and close by a sampling pulse φ _P sequentially output from the horizontal address circuit 5a, and a side black signal VSB is output.
Are sampled on the signal line Y. As can be understood from the above description, the horizontal address circuit 5a and the auxiliary switch P
The combination of SWs constitutes the mask means 5 shown in FIG. The horizontal address circuit 5a receives a start signal PST and a clock signal PCK from an external timing generator or the like.
Is supplied, the sampling pulse φ _P1 , φ _P2 , φ _P3 , φ _P12 , φ _P13 , φ _P14 , and φ _P15 for normal display are output. However, φ _P3 and φ _P12 are irregular and are output every other horizontal period. The horizontal address circuit 5a is in a stopped state during wide display.

Next, the operation of the circuit shown in FIG. 2 during normal display will be described with reference to the timing chart of FIG. The display device of this example performs 1H inversion driving in the normally white mode. As shown in the drawing, the polarity of the side black signal VSB is inverted every 1H with reference to a predetermined center potential. The polarity of the video signal VSIG is also inverted every 1H with reference to a predetermined center potential. The signal line located at the boundary between the center part of the screen and the left side part or the right side part alternately samples VSB and VSIG, and the potential changes as shown. For example, focusing on the third signal line Y located at the boundary between the left side portion and the central portion, the sampling pulse φ from the lower horizontal address circuit 5a in the first horizontal period.
_P3 is output and the positive VSB is sampled.
In the second horizontal period, the sampling pulse φ _H3 is output from the upper horizontal address circuit 4a, and negative polarity VSIG is sampled. Similarly, the positive VSB is sampled during the third horizontal period, the negative VSIG is sampled during the fourth horizontal period, the positive VSB is sampled during the fifth horizontal period, and the negative VSB is sampled during the sixth horizontal period. Positive VSIG is sampled, and positive VSB is sampled in the seventh horizontal period. In this way, VSB and VSIG, which are alternately sampled in each horizontal period, are written in each pixel row by row at each falling edge of the gate pulse.

FIG. 4 is a schematic block diagram showing another embodiment of the display device according to the present invention. The display device includes a pixel array section 11 and a peripheral circuit section. The pixel array unit 11 constitutes a horizontally long screen capable of switching between wide display and normal display. The peripheral circuit section is the pixel array section 11
To drive. The pixel array unit 11 includes a set of single color pixels arranged in a delta pattern. Pixels are arranged in a delta arrangement as in the embodiment shown in FIG. 1, but only pixels of a single color are included rather than the three primary colors. In this example, it is composed of only green pixels G. Since the pixel array unit 11 has a delta-like arrangement, linearly aligned pixel rows and zigzag-shaped pixel columns are defined as in the embodiment of FIG. In this example, the horizontally long screen typically includes 7 pixel rows and 15 pixel columns.

The peripheral circuit section has a vertical drive circuit 13, a horizontal drive circuit 14, and a mask means 15. Vertical drive circuit 1
3 sequentially selects each of the first to seventh pixel rows. The horizontal drive circuit 14 writes the video signal VSIG in each pixel column in synchronization with the sequential selection. The masking means 15 writes the side black signal VSB to a predetermined pixel column in synchronization with the sequential selection.

As a feature of the present invention, the control means 17 connected to the above-mentioned peripheral circuit section is provided. Control means 1
Reference numeral 7 controls the horizontal drive circuit 14 during wide display to control the video signal VS to the first to fifteenth pixel columns over the entire screen.
Write IG. On the other hand, the horizontal drive circuit 1 for normal display
4 and the masking means 15 to control the video signal VSIG to the 4th to 11th pixel columns included in the central portion of the screen.
And the side black signal VSB is written in the first and second pixel columns included in the left side of the screen and the 14th and 15th pixel columns included in the right side. At this time, the video signal VSIG and the side black signal VSB are mixed and written to a predetermined number of pixel rows located at the boundary between the central portion and the left and right side portions, and the left and right boundaries that are intricately zigzag are symmetrical to each other. Shape. Specifically, VSIG and VSB are written alternately for each horizontal period in the third pixel column located at the boundary between the left side portion and the central portion.
As a result, the boundary on the left end side is shaped into a sideline shape with entrance / exit for 0.5 pitch. Similarly, VSB and VSIG are alternately written to the 12th pixel column located at the boundary between the central portion and the right portion. As a result, the boundary on the right end side has the same shape as the boundary on the left end side, but it is not symmetrical with respect to the center of the screen. Therefore, in the present invention, VSIG and VSB are alternately written for each horizontal period even for the 13th pixel column. As a result, in normal display, the boundary on the left end side and the boundary on the right end side are symmetrical to each other.

The horizontal drive circuit 14 shown in FIG.
The video signal VS is sequentially applied to the pixel rows from the left to the right of the screen.
It is possible to switch between normal display in which IG is written and reverse display in which video signals are sequentially written in pixel rows from the right side to the left side of the screen. By using three display devices having such a configuration, it is possible to perform a three-plate RGB composite display as shown in FIG. For a display device having a red pixel R, normal rotation normal display is performed. In the display device including the green pixel G, reverse normal display is performed. Blue pixel B
In the display device having, the normal display of normal rotation is performed. According to the invention, the display device has a symmetrical boundary shape. Therefore, the normal display and the reverse display are correctly aligned with each other when three sheets are overlapped, and a complete RGB composite display including the boundary can be obtained.

Finally, with reference to FIG. 6, a specific example of the horizontal address circuit suitable for the switching drive between the wide display and the normal display and the horizontal inversion drive will be described. As shown in the figure, the horizontal address circuit has a single shift register 40, which transfers a predetermined start signal HST for each stage to perform dot-sequential writing of pixels (not shown). The shift register 40 has a structure in which flip-flops FF having a pair of input terminals I and output terminals O are connected in multiple stages in a number corresponding to the total number of columns of pixels. The input / output terminals of each FF are sequentially connected via two data transfer paths 41. In this example, M flip-flops are connected in multiple stages from FF _{1 in the first} stage to FF _{M in the} last stage. This M
Wide display is performed by driving all the FFs. The M flip-flops include intermediate stages from FF _J to FF _K and are selectively driven during normal display.
In this case, not in the middle stage FF ₁ ~FF _J-1 and FF
_{K + 1 ~FF M} operation is stopped the pause stage. A pair of FF _J-1 and FF _J and another pair of FF _K and FF _{K + 1} are located at the boundary between the wide display and the normal display.

The shift register 40 of this example is bidirectional, and can perform forward transfer and reverse transfer of data in a selectable manner. For this purpose, transfer gate elements L and R are respectively interposed between the input and output terminals of a pair of flip-flops located adjacent to each other. By selectively opening and closing the transfer gate elements L and R, the data transfer is controlled in the forward direction or the reverse direction to enable bidirectional point sequential writing of pixels. For example, one transfer gate element L is interposed between the input terminal of FF _{1 and} the output terminal of FF ₂ . The other transfer gate element R is interposed between the output terminal O of FF ₁ and the input terminal I of FF ₂ . Similarly, transfer gate elements R and L are respectively interposed between the input and output terminals of the FFs adjacent to each other. When the transfer gate element R is opened and the transfer gate element L is closed, the start signal HST is sequentially sent through the data transfer path 41 in the forward direction. Conversely, when the transfer gate element R is closed while the transfer gate element L is opened, the start signal HST
Are sequentially sent in the reverse direction via the data transfer path 41.

The horizontal address circuit has a wide input switch element W and a normal input switch element N. The wide input switch element W injects the start signal HST to the input terminal of the flip-flop located at the leading stage during wide display. On the other hand, the normal input switch element N injects the start signal HST to the input terminal of the flip-flop located at a specific intermediate stage during normal display. In the forward transfer, FF ₁ is the _first stage, so the wide input switch element W is connected to its input terminal I. On the other hand, in the reverse transfer, the FF _M is the first stage, so the wide input switch element W is also connected to the input terminal I thereof. In the normal display forward transfer, FF _J corresponds to a specific intermediate stage, and the normal input switch element N is connected to its input terminal I. In reverse transfer, FF _K is the first stage of normal display, and the normal input switch element N is also connected to its input terminal I. In the case of wide display, the start signal HST injected into the head stage is transferred to the last stage in both forward transfer and reverse transfer. On the other hand, in normal display, in the case of forward transfer, the start pulse HST is injected into FF _J and transferred up to FF _K. In the case of reverse transfer, it is injected into FF _K and transferred up to FF _J.

In the horizontal address circuit, a connection gate element G is interposed between the input / output terminals of a pair of flip-flops located at the boundary between wide display and normal display. Specifically, connection gate elements G are provided between FF _J-1 and FF _J and between FF _K and FF _{K + 1} , respectively. As a result, the data transfer at the wide display boundary is enabled, while the data transfer at the normal display boundary is blocked. With this configuration, the single shift register 40 ensures division of each FF in normal display and wide display. In the wide display, the connection gate element G functions equivalently to the transfer gate elements R and L described above.

FIG. 7 is a circuit diagram partially showing a specific circuit configuration example of the horizontal address circuit shown in FIG. In order to explain the bidirectional transfer of data, only two flip-flops (first stage FF and second stage FF) and their associated transfer gate elements R and L are shown. All circuit elements are composed of thin film transistors (TFTs). Both the front FF and the next FF are composed of D-type flip-flops. Each D-type flip-flop is composed of first and second clocked inverters and a third inverter, operates according to clock signals HCK and HCKX having mutually opposite phases, and converts the data input from the input terminal IN into clock signals. It is delayed by a half cycle and output to the output terminal OUT. Each of the transfer gate elements R and L is composed of a CMOS type transmission gate element. The transfer gate elements R and L are control signals R of opposite phases supplied from a control means (not shown).
It is controlled by T and RTX. One control signal RT
Is high level and the other control signal RTX is low level, one transfer gate element R is opened and the other transfer gate element L is closed. Therefore, at this time, the data is supplied to the input terminal IN of the preceding stage FF after passing through the first transfer gate element R. Here, after being delayed by a half cycle of the clock signal, it is transferred from the output terminal OUT to the input terminal IN of the next stage FF via the next transfer gate element R. In this way, the data is sequentially transferred in the forward direction. On the other hand, when the control signal RT is low level and the control signal RTX is switched to high level, one transfer gate element R is closed and the other transfer gate element L is opened. In this case, the data transferred from the opposite direction is supplied to the input terminal IN of the next-stage FF and subjected to a predetermined delay process, and then the output terminal OUT passes through the transfer gate element L and the input terminal of the previous-stage FF. Transferred to IN. The data output from the output terminal OUT after being subjected to the predetermined delay processing again reaches the next transfer gate element L.

[0030]

As described above, according to the first aspect of the present invention, a display device having a delta pixel array and capable of switching between wide display and normal display is included in the central portion of a landscape screen. The video signal is written to the pixel columns to be displayed, and the side black signal is written to the pixel columns included on the left and right sides of the landscape screen to realize normal display.
At this time, the video signal and the sampling signal are alternately written in a specific pixel row located at the boundary between the central portion and the left and right side portions every horizontal period, thereby shaping the intricately zigzag boundary. Therefore, there is an effect that both side lines of the normal display can be sharpened. According to the second aspect of the present invention, in a display device having a single-color pixel array for each of the three primary colors and capable of switching between wide display and normal display, a video signal is supplied to a pixel column included in the central portion of a horizontally long screen. In addition to writing, side black signals are written to the pixel columns included on the left and right sides of the screen to realize normal display. At this time, the video signal and the side black signal are mixed and written to a predetermined number of pixel columns located at the boundary between the central part and the left and right side parts, and the left and right boundaries intricately zigzag are shaped symmetrically with each other. There is. As a result, when three display devices for each of the three primary colors are overlapped with each other to perform a normal display of RGB synthesis, R is displayed along the left and right boundaries.
The GB three primary color pixels can be perfectly matched, and the color tone along the side line can be made normal.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a display device according to the present invention.

FIG. 2 is a block diagram showing a specific configuration example of the embodiment shown in FIG.

FIG. 3 is a waveform diagram for explaining the operation of the circuit shown in FIG.

FIG. 4 is a schematic block diagram showing another embodiment of the display device according to the present invention.

FIG. 5 is a schematic view showing an example of how to use the embodiment shown in FIG.

FIG. 6 is a block diagram showing an example of a horizontal address circuit suitable for the present invention.

7 is a circuit diagram showing a specific configuration example of the horizontal address circuit shown in FIG.

FIG. 8 is a schematic plan view showing an example of a conventional display device.

FIG. 9 is a schematic view showing another example of a conventional display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pixel array part 2 Screen 3 Vertical drive circuit 4 Horizontal drive circuit 5 Mask means 6 Signal source 7 Control means 8 Video line 9 Auxiliary line 11 Pixel array part 13 Vertical drive circuit 14 Horizontal drive circuit 15 Mask means 17 Control means

Claims (5)

[Claims] 1. A pixel array section that constitutes a horizontally long screen capable of switching between wide display and normal display, and a peripheral circuit section that drives the pixel array section, wherein the pixel array section includes three primary color pixels in a delta arrangement. And a vertical drive circuit that sequentially selects each pixel row for each horizontal period, and that defines a pixel row that is linearly aligned and pixel columns that intertwine in zigzag. A display device having a horizontal drive circuit for writing a video signal to a pixel column and a masking means for writing a side black signal to the pixel column, the control device being connected to the peripheral circuit section, and for a wide display The horizontal drive circuit is controlled to write a video signal to the pixel columns over the entire screen, while at the time of normal display, the horizontal drive circuit and the mask means are controlled to display an image on a pixel column included in a part of the screen. Write a signal and write a side black signal to the pixel columns included in the remaining part of the screen, and write a video signal and a side black signal alternately every horizontal period to a specific pixel column located at the boundary of both parts and enter into a zigzag pattern. A display device characterized by shaping the boundary. 2. The pixel array section includes a set of pixels each including a fine liquid crystal cell and an active element coupled to each other, and the peripheral circuit section drives each liquid crystal cell by an active matrix through each active element. The display device according to claim 1, wherein: 3. A pixel array section forming a horizontally long screen capable of switching between wide display and normal display, and a peripheral circuit section for driving the pixel array section, wherein the pixel array section is arranged in a delta pattern. It includes a set of pixels of one color and defines a linearly aligned pixel row and a zigzag intricate pixel column, and the peripheral circuit unit is synchronized with the vertical drive circuit that sequentially selects each pixel row. A display device having a horizontal drive circuit for writing a video signal to a pixel column and a masking means for writing a side black signal to the pixel column, the control device being connected to the peripheral circuit section, The horizontal drive circuit is controlled to write the video signal to the pixel columns over the entire screen, while the normal drive is controlled to control the horizontal drive circuit and the masking means to apply the video signal to the pixel column included in the central portion of the screen. While writing, side black signals are written to the pixel columns included in the left and right sides of the screen, and the video signals and side black signals are mixed for a predetermined number of pixel columns located at the boundary between the central portion and the left and right sides. A display device characterized by shaping left and right boundaries intricately arranged in writing zigzag symmetrically to each other. 4. The horizontal drive circuit comprises a normal display in which video signals are sequentially written in pixel columns from left to right of the screen, and a video signal is sequentially written in pixel columns from right to left of the screen. 4. The display device according to claim 3, wherein it is possible to switch between reverse display for writing and. 5. The pixel array section includes a set of pixels each including a combination of a fine liquid crystal cell and an active element, and the peripheral circuit section drives each liquid crystal cell by an active matrix via each active element. The display device according to claim 3, characterized in that: